MipsInstrFormats.td revision 1206f1968b0886ab41739aebe113dd4813f3fc46
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39class MMRel; 40 41def Std2MicroMips : InstrMapping { 42 let FilterClass = "MMRel"; 43 // Instructions with the same BaseOpcode and isNVStore values form a row. 44 let RowFields = ["BaseOpcode"]; 45 // Instructions with the same predicate sense form a column. 46 let ColFields = ["Arch"]; 47 // The key column is the unpredicated instructions. 48 let KeyCol = ["se"]; 49 // Value columns are PredSense=true and PredSense=false 50 let ValueCols = [["se"], ["micromips"]]; 51} 52 53class StdArch { 54 string Arch = "se"; 55} 56 57// Generic Mips Format 58class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 59 InstrItinClass itin, Format f>: Instruction 60{ 61 field bits<32> Inst; 62 Format Form = f; 63 64 let Namespace = "Mips"; 65 66 let Size = 4; 67 68 bits<6> Opcode = 0; 69 70 // Top 6 bits are the 'opcode' field 71 let Inst{31-26} = Opcode; 72 73 let OutOperandList = outs; 74 let InOperandList = ins; 75 76 let AsmString = asmstr; 77 let Pattern = pattern; 78 let Itinerary = itin; 79 80 // 81 // Attributes specific to Mips instructions... 82 // 83 bits<4> FormBits = Form.Value; 84 85 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 86 let TSFlags{3-0} = FormBits; 87 88 let DecoderNamespace = "Mips"; 89 90 field bits<32> SoftFail = 0; 91} 92 93// Mips32/64 Instruction Format 94class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 95 InstrItinClass itin, Format f, string opstr = ""> : 96 MipsInst<outs, ins, asmstr, pattern, itin, f> { 97 let Predicates = [HasStdEnc]; 98 string BaseOpcode = opstr; 99 string Arch; 100} 101 102// Mips Pseudo Instructions Format 103class MipsPseudo<dag outs, dag ins, list<dag> pattern, 104 InstrItinClass itin = IIPseudo> : 105 MipsInst<outs, ins, "", pattern, itin, Pseudo> { 106 let isCodeGenOnly = 1; 107 let isPseudo = 1; 108} 109 110// Mips32/64 Pseudo Instruction Format 111class PseudoSE<dag outs, dag ins, list<dag> pattern, 112 InstrItinClass itin = IIPseudo>: 113 MipsPseudo<outs, ins, pattern, itin> { 114 let Predicates = [HasStdEnc]; 115} 116 117// Pseudo-instructions for alternate assembly syntax (never used by codegen). 118// These are aliases that require C++ handling to convert to the target 119// instruction, while InstAliases can be handled directly by tblgen. 120class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 122 let isPseudo = 1; 123 let Pattern = []; 124} 125//===----------------------------------------------------------------------===// 126// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 127//===----------------------------------------------------------------------===// 128 129class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 130 list<dag> pattern, InstrItinClass itin>: 131 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 132{ 133 bits<5> rd; 134 bits<5> rs; 135 bits<5> rt; 136 bits<5> shamt; 137 bits<6> funct; 138 139 let Opcode = op; 140 let funct = _funct; 141 142 let Inst{25-21} = rs; 143 let Inst{20-16} = rt; 144 let Inst{15-11} = rd; 145 let Inst{10-6} = shamt; 146 let Inst{5-0} = funct; 147} 148 149//===----------------------------------------------------------------------===// 150// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 151//===----------------------------------------------------------------------===// 152 153class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 154 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 155{ 156 bits<5> rt; 157 bits<5> rs; 158 bits<16> imm16; 159 160 let Opcode = op; 161 162 let Inst{25-21} = rs; 163 let Inst{20-16} = rt; 164 let Inst{15-0} = imm16; 165} 166 167class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 168 list<dag> pattern, InstrItinClass itin>: 169 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 170{ 171 bits<5> rs; 172 bits<5> rt; 173 bits<16> imm16; 174 175 let Opcode = op; 176 177 let Inst{25-21} = rs; 178 let Inst{20-16} = rt; 179 let Inst{15-0} = imm16; 180} 181 182//===----------------------------------------------------------------------===// 183// Format J instruction class in Mips : <|opcode|address|> 184//===----------------------------------------------------------------------===// 185 186class FJ<bits<6> op> : StdArch 187{ 188 bits<26> target; 189 190 bits<32> Inst; 191 192 let Inst{31-26} = op; 193 let Inst{25-0} = target; 194} 195 196//===----------------------------------------------------------------------===// 197// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 198//===----------------------------------------------------------------------===// 199class MFC3OP_FM<bits<6> op, bits<5> mfmt> 200{ 201 bits<5> rt; 202 bits<5> rd; 203 bits<3> sel; 204 205 bits<32> Inst; 206 207 let Inst{31-26} = op; 208 let Inst{25-21} = mfmt; 209 let Inst{20-16} = rt; 210 let Inst{15-11} = rd; 211 let Inst{10-3} = 0; 212 let Inst{2-0} = sel; 213} 214 215class ADD_FM<bits<6> op, bits<6> funct> : StdArch { 216 bits<5> rd; 217 bits<5> rs; 218 bits<5> rt; 219 220 bits<32> Inst; 221 222 let Inst{31-26} = op; 223 let Inst{25-21} = rs; 224 let Inst{20-16} = rt; 225 let Inst{15-11} = rd; 226 let Inst{10-6} = 0; 227 let Inst{5-0} = funct; 228} 229 230class ADDI_FM<bits<6> op> : StdArch { 231 bits<5> rs; 232 bits<5> rt; 233 bits<16> imm16; 234 235 bits<32> Inst; 236 237 let Inst{31-26} = op; 238 let Inst{25-21} = rs; 239 let Inst{20-16} = rt; 240 let Inst{15-0} = imm16; 241} 242 243class SRA_FM<bits<6> funct, bit rotate> : StdArch { 244 bits<5> rd; 245 bits<5> rt; 246 bits<5> shamt; 247 248 bits<32> Inst; 249 250 let Inst{31-26} = 0; 251 let Inst{25-22} = 0; 252 let Inst{21} = rotate; 253 let Inst{20-16} = rt; 254 let Inst{15-11} = rd; 255 let Inst{10-6} = shamt; 256 let Inst{5-0} = funct; 257} 258 259class SRLV_FM<bits<6> funct, bit rotate> : StdArch { 260 bits<5> rd; 261 bits<5> rt; 262 bits<5> rs; 263 264 bits<32> Inst; 265 266 let Inst{31-26} = 0; 267 let Inst{25-21} = rs; 268 let Inst{20-16} = rt; 269 let Inst{15-11} = rd; 270 let Inst{10-7} = 0; 271 let Inst{6} = rotate; 272 let Inst{5-0} = funct; 273} 274 275class BEQ_FM<bits<6> op> : StdArch { 276 bits<5> rs; 277 bits<5> rt; 278 bits<16> offset; 279 280 bits<32> Inst; 281 282 let Inst{31-26} = op; 283 let Inst{25-21} = rs; 284 let Inst{20-16} = rt; 285 let Inst{15-0} = offset; 286} 287 288class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch { 289 bits<5> rs; 290 bits<16> offset; 291 292 bits<32> Inst; 293 294 let Inst{31-26} = op; 295 let Inst{25-21} = rs; 296 let Inst{20-16} = funct; 297 let Inst{15-0} = offset; 298} 299 300class SLTI_FM<bits<6> op> : StdArch { 301 bits<5> rt; 302 bits<5> rs; 303 bits<16> imm16; 304 305 bits<32> Inst; 306 307 let Inst{31-26} = op; 308 let Inst{25-21} = rs; 309 let Inst{20-16} = rt; 310 let Inst{15-0} = imm16; 311} 312 313class MFLO_FM<bits<6> funct> : StdArch { 314 bits<5> rd; 315 316 bits<32> Inst; 317 318 let Inst{31-26} = 0; 319 let Inst{25-16} = 0; 320 let Inst{15-11} = rd; 321 let Inst{10-6} = 0; 322 let Inst{5-0} = funct; 323} 324 325class MTLO_FM<bits<6> funct> : StdArch { 326 bits<5> rs; 327 328 bits<32> Inst; 329 330 let Inst{31-26} = 0; 331 let Inst{25-21} = rs; 332 let Inst{20-6} = 0; 333 let Inst{5-0} = funct; 334} 335 336class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch { 337 bits<5> rd; 338 bits<5> rt; 339 340 bits<32> Inst; 341 342 let Inst{31-26} = 0x1f; 343 let Inst{25-21} = 0; 344 let Inst{20-16} = rt; 345 let Inst{15-11} = rd; 346 let Inst{10-6} = funct; 347 let Inst{5-0} = funct2; 348} 349 350class CLO_FM<bits<6> funct> : StdArch { 351 bits<5> rd; 352 bits<5> rs; 353 bits<5> rt; 354 355 bits<32> Inst; 356 357 let Inst{31-26} = 0x1c; 358 let Inst{25-21} = rs; 359 let Inst{20-16} = rt; 360 let Inst{15-11} = rd; 361 let Inst{10-6} = 0; 362 let Inst{5-0} = funct; 363 let rt = rd; 364} 365 366class LUI_FM : StdArch { 367 bits<5> rt; 368 bits<16> imm16; 369 370 bits<32> Inst; 371 372 let Inst{31-26} = 0xf; 373 let Inst{25-21} = 0; 374 let Inst{20-16} = rt; 375 let Inst{15-0} = imm16; 376} 377 378class JALR_FM : StdArch { 379 bits<5> rd; 380 bits<5> rs; 381 382 bits<32> Inst; 383 384 let Inst{31-26} = 0; 385 let Inst{25-21} = rs; 386 let Inst{20-16} = 0; 387 let Inst{15-11} = rd; 388 let Inst{10-6} = 0; 389 let Inst{5-0} = 9; 390} 391 392class BGEZAL_FM<bits<5> funct> : StdArch { 393 bits<5> rs; 394 bits<16> offset; 395 396 bits<32> Inst; 397 398 let Inst{31-26} = 1; 399 let Inst{25-21} = rs; 400 let Inst{20-16} = funct; 401 let Inst{15-0} = offset; 402} 403 404class SYNC_FM { 405 bits<5> stype; 406 407 bits<32> Inst; 408 409 let Inst{31-26} = 0; 410 let Inst{10-6} = stype; 411 let Inst{5-0} = 0xf; 412} 413 414class MULT_FM<bits<6> op, bits<6> funct> : StdArch { 415 bits<5> rs; 416 bits<5> rt; 417 418 bits<32> Inst; 419 420 let Inst{31-26} = op; 421 let Inst{25-21} = rs; 422 let Inst{20-16} = rt; 423 let Inst{15-6} = 0; 424 let Inst{5-0} = funct; 425} 426 427class EXT_FM<bits<6> funct> : StdArch { 428 bits<5> rt; 429 bits<5> rs; 430 bits<5> pos; 431 bits<5> size; 432 433 bits<32> Inst; 434 435 let Inst{31-26} = 0x1f; 436 let Inst{25-21} = rs; 437 let Inst{20-16} = rt; 438 let Inst{15-11} = size; 439 let Inst{10-6} = pos; 440 let Inst{5-0} = funct; 441} 442 443class RDHWR_FM { 444 bits<5> rt; 445 bits<5> rd; 446 447 bits<32> Inst; 448 449 let Inst{31-26} = 0x1f; 450 let Inst{25-21} = 0; 451 let Inst{20-16} = rt; 452 let Inst{15-11} = rd; 453 let Inst{10-6} = 0; 454 let Inst{5-0} = 0x3b; 455} 456 457class TEQ_FM<bits<6> funct> : StdArch { 458 bits<5> rs; 459 bits<5> rt; 460 bits<10> code_; 461 462 bits<32> Inst; 463 464 let Inst{31-26} = 0; 465 let Inst{25-21} = rs; 466 let Inst{20-16} = rt; 467 let Inst{15-6} = code_; 468 let Inst{5-0} = funct; 469} 470 471class TEQI_FM<bits<5> funct> : StdArch { 472 bits<5> rs; 473 bits<16> imm16; 474 475 bits<32> Inst; 476 477 let Inst{31-26} = 1; 478 let Inst{25-21} = rs; 479 let Inst{20-16} = funct; 480 let Inst{15-0} = imm16; 481} 482//===----------------------------------------------------------------------===// 483// System calls format <op|code_|funct> 484//===----------------------------------------------------------------------===// 485 486class SYS_FM<bits<6> funct> 487{ 488 bits<20> code_; 489 bits<32> Inst; 490 let Inst{31-26} = 0x0; 491 let Inst{25-6} = code_; 492 let Inst{5-0} = funct; 493} 494 495//===----------------------------------------------------------------------===// 496// Break instruction format <op|code_1|funct> 497//===----------------------------------------------------------------------===// 498 499class BRK_FM<bits<6> funct> 500{ 501 bits<10> code_1; 502 bits<10> code_2; 503 bits<32> Inst; 504 let Inst{31-26} = 0x0; 505 let Inst{25-16} = code_1; 506 let Inst{15-6} = code_2; 507 let Inst{5-0} = funct; 508} 509 510//===----------------------------------------------------------------------===// 511// Exception return format <Cop0|1|0|funct> 512//===----------------------------------------------------------------------===// 513 514class ER_FM<bits<6> funct> 515{ 516 bits<32> Inst; 517 let Inst{31-26} = 0x10; 518 let Inst{25} = 1; 519 let Inst{24-6} = 0; 520 let Inst{5-0} = funct; 521} 522 523 524//===----------------------------------------------------------------------===// 525// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> 526//===----------------------------------------------------------------------===// 527 528class EI_FM<bits<1> sc> 529{ 530 bits<32> Inst; 531 bits<5> rt; 532 let Inst{31-26} = 0x10; 533 let Inst{25-21} = 0xb; 534 let Inst{20-16} = rt; 535 let Inst{15-11} = 0xc; 536 let Inst{10-6} = 0; 537 let Inst{5} = sc; 538 let Inst{4-0} = 0; 539} 540 541//===----------------------------------------------------------------------===// 542// 543// FLOATING POINT INSTRUCTION FORMATS 544// 545// opcode - operation code. 546// fs - src reg. 547// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 548// fd - dst reg, only used on 3 regs instr. 549// fmt - double or single precision. 550// funct - combined with opcode field give us an operation code. 551// 552//===----------------------------------------------------------------------===// 553 554//===----------------------------------------------------------------------===// 555// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 556//===----------------------------------------------------------------------===// 557 558class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 559 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 560{ 561 bits<5> ft; 562 bits<5> base; 563 bits<16> imm16; 564 565 let Opcode = op; 566 567 let Inst{25-21} = base; 568 let Inst{20-16} = ft; 569 let Inst{15-0} = imm16; 570} 571 572class ADDS_FM<bits<6> funct, bits<5> fmt> { 573 bits<5> fd; 574 bits<5> fs; 575 bits<5> ft; 576 577 bits<32> Inst; 578 579 let Inst{31-26} = 0x11; 580 let Inst{25-21} = fmt; 581 let Inst{20-16} = ft; 582 let Inst{15-11} = fs; 583 let Inst{10-6} = fd; 584 let Inst{5-0} = funct; 585} 586 587class ABSS_FM<bits<6> funct, bits<5> fmt> { 588 bits<5> fd; 589 bits<5> fs; 590 591 bits<32> Inst; 592 593 let Inst{31-26} = 0x11; 594 let Inst{25-21} = fmt; 595 let Inst{20-16} = 0; 596 let Inst{15-11} = fs; 597 let Inst{10-6} = fd; 598 let Inst{5-0} = funct; 599} 600 601class MFC1_FM<bits<5> funct> { 602 bits<5> rt; 603 bits<5> fs; 604 605 bits<32> Inst; 606 607 let Inst{31-26} = 0x11; 608 let Inst{25-21} = funct; 609 let Inst{20-16} = rt; 610 let Inst{15-11} = fs; 611 let Inst{10-0} = 0; 612} 613 614class LW_FM<bits<6> op> : StdArch { 615 bits<5> rt; 616 bits<21> addr; 617 618 bits<32> Inst; 619 620 let Inst{31-26} = op; 621 let Inst{25-21} = addr{20-16}; 622 let Inst{20-16} = rt; 623 let Inst{15-0} = addr{15-0}; 624} 625 626class MADDS_FM<bits<3> funct, bits<3> fmt> { 627 bits<5> fd; 628 bits<5> fr; 629 bits<5> fs; 630 bits<5> ft; 631 632 bits<32> Inst; 633 634 let Inst{31-26} = 0x13; 635 let Inst{25-21} = fr; 636 let Inst{20-16} = ft; 637 let Inst{15-11} = fs; 638 let Inst{10-6} = fd; 639 let Inst{5-3} = funct; 640 let Inst{2-0} = fmt; 641} 642 643class LWXC1_FM<bits<6> funct> { 644 bits<5> fd; 645 bits<5> base; 646 bits<5> index; 647 648 bits<32> Inst; 649 650 let Inst{31-26} = 0x13; 651 let Inst{25-21} = base; 652 let Inst{20-16} = index; 653 let Inst{15-11} = 0; 654 let Inst{10-6} = fd; 655 let Inst{5-0} = funct; 656} 657 658class SWXC1_FM<bits<6> funct> { 659 bits<5> fs; 660 bits<5> base; 661 bits<5> index; 662 663 bits<32> Inst; 664 665 let Inst{31-26} = 0x13; 666 let Inst{25-21} = base; 667 let Inst{20-16} = index; 668 let Inst{15-11} = fs; 669 let Inst{10-6} = 0; 670 let Inst{5-0} = funct; 671} 672 673class BC1F_FM<bit nd, bit tf> { 674 bits<3> fcc; 675 bits<16> offset; 676 677 bits<32> Inst; 678 679 let Inst{31-26} = 0x11; 680 let Inst{25-21} = 0x8; 681 let Inst{20-18} = fcc; 682 let Inst{17} = nd; 683 let Inst{16} = tf; 684 let Inst{15-0} = offset; 685} 686 687class CEQS_FM<bits<5> fmt> { 688 bits<5> fs; 689 bits<5> ft; 690 bits<4> cond; 691 692 bits<32> Inst; 693 694 let Inst{31-26} = 0x11; 695 let Inst{25-21} = fmt; 696 let Inst{20-16} = ft; 697 let Inst{15-11} = fs; 698 let Inst{10-8} = 0; // cc 699 let Inst{7-4} = 0x3; 700 let Inst{3-0} = cond; 701} 702 703class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 704 let cond = c; 705} 706 707class CMov_I_F_FM<bits<6> funct, bits<5> fmt> { 708 bits<5> fd; 709 bits<5> fs; 710 bits<5> rt; 711 712 bits<32> Inst; 713 714 let Inst{31-26} = 0x11; 715 let Inst{25-21} = fmt; 716 let Inst{20-16} = rt; 717 let Inst{15-11} = fs; 718 let Inst{10-6} = fd; 719 let Inst{5-0} = funct; 720} 721 722class CMov_F_I_FM<bit tf> : StdArch { 723 bits<5> rd; 724 bits<5> rs; 725 bits<3> fcc; 726 727 bits<32> Inst; 728 729 let Inst{31-26} = 0; 730 let Inst{25-21} = rs; 731 let Inst{20-18} = fcc; 732 let Inst{17} = 0; 733 let Inst{16} = tf; 734 let Inst{15-11} = rd; 735 let Inst{10-6} = 0; 736 let Inst{5-0} = 1; 737} 738 739class CMov_F_F_FM<bits<5> fmt, bit tf> { 740 bits<5> fd; 741 bits<5> fs; 742 bits<3> fcc; 743 744 bits<32> Inst; 745 746 let Inst{31-26} = 0x11; 747 let Inst{25-21} = fmt; 748 let Inst{20-18} = fcc; 749 let Inst{17} = 0; 750 let Inst{16} = tf; 751 let Inst{15-11} = fs; 752 let Inst{10-6} = fd; 753 let Inst{5-0} = 0x11; 754} 755