MipsInstrFormats.td revision 407883b69b3bc10ebf053f5922d877b2e786d124
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39class MMRel; 40 41def Std2MicroMips : InstrMapping { 42 let FilterClass = "MMRel"; 43 // Instructions with the same BaseOpcode and isNVStore values form a row. 44 let RowFields = ["BaseOpcode"]; 45 // Instructions with the same predicate sense form a column. 46 let ColFields = ["Arch"]; 47 // The key column is the unpredicated instructions. 48 let KeyCol = ["se"]; 49 // Value columns are PredSense=true and PredSense=false 50 let ValueCols = [["se"], ["micromips"]]; 51} 52 53class StdArch { 54 string Arch = "se"; 55} 56 57// Generic Mips Format 58class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 59 InstrItinClass itin, Format f>: Instruction 60{ 61 field bits<32> Inst; 62 Format Form = f; 63 64 let Namespace = "Mips"; 65 66 let Size = 4; 67 68 bits<6> Opcode = 0; 69 70 // Top 6 bits are the 'opcode' field 71 let Inst{31-26} = Opcode; 72 73 let OutOperandList = outs; 74 let InOperandList = ins; 75 76 let AsmString = asmstr; 77 let Pattern = pattern; 78 let Itinerary = itin; 79 80 // 81 // Attributes specific to Mips instructions... 82 // 83 bits<4> FormBits = Form.Value; 84 85 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 86 let TSFlags{3-0} = FormBits; 87 88 let DecoderNamespace = "Mips"; 89 90 field bits<32> SoftFail = 0; 91} 92 93// Mips32/64 Instruction Format 94class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 95 InstrItinClass itin, Format f, string opstr = ""> : 96 MipsInst<outs, ins, asmstr, pattern, itin, f> { 97 let Predicates = [HasStdEnc]; 98 string BaseOpcode = opstr; 99 string Arch; 100 let MnemonicContainsDot = 1; 101} 102 103// Mips Pseudo Instructions Format 104class MipsPseudo<dag outs, dag ins, list<dag> pattern, 105 InstrItinClass itin = IIPseudo> : 106 MipsInst<outs, ins, "", pattern, itin, Pseudo> { 107 let isCodeGenOnly = 1; 108 let isPseudo = 1; 109} 110 111// Mips32/64 Pseudo Instruction Format 112class PseudoSE<dag outs, dag ins, list<dag> pattern, 113 InstrItinClass itin = IIPseudo>: 114 MipsPseudo<outs, ins, pattern, itin> { 115 let Predicates = [HasStdEnc]; 116} 117 118// Pseudo-instructions for alternate assembly syntax (never used by codegen). 119// These are aliases that require C++ handling to convert to the target 120// instruction, while InstAliases can be handled directly by tblgen. 121class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 122 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 123 let isPseudo = 1; 124 let Pattern = []; 125} 126//===----------------------------------------------------------------------===// 127// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 128//===----------------------------------------------------------------------===// 129 130class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 131 list<dag> pattern, InstrItinClass itin>: 132 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 133{ 134 bits<5> rd; 135 bits<5> rs; 136 bits<5> rt; 137 bits<5> shamt; 138 bits<6> funct; 139 140 let Opcode = op; 141 let funct = _funct; 142 143 let Inst{25-21} = rs; 144 let Inst{20-16} = rt; 145 let Inst{15-11} = rd; 146 let Inst{10-6} = shamt; 147 let Inst{5-0} = funct; 148} 149 150//===----------------------------------------------------------------------===// 151// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 152//===----------------------------------------------------------------------===// 153 154class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 155 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 156{ 157 bits<5> rt; 158 bits<5> rs; 159 bits<16> imm16; 160 161 let Opcode = op; 162 163 let Inst{25-21} = rs; 164 let Inst{20-16} = rt; 165 let Inst{15-0} = imm16; 166} 167 168class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 169 list<dag> pattern, InstrItinClass itin>: 170 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 171{ 172 bits<5> rs; 173 bits<5> rt; 174 bits<16> imm16; 175 176 let Opcode = op; 177 178 let Inst{25-21} = rs; 179 let Inst{20-16} = rt; 180 let Inst{15-0} = imm16; 181} 182 183//===----------------------------------------------------------------------===// 184// Format J instruction class in Mips : <|opcode|address|> 185//===----------------------------------------------------------------------===// 186 187class FJ<bits<6> op> 188{ 189 bits<26> target; 190 191 bits<32> Inst; 192 193 let Inst{31-26} = op; 194 let Inst{25-0} = target; 195} 196 197//===----------------------------------------------------------------------===// 198// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 199//===----------------------------------------------------------------------===// 200class MFC3OP_FM<bits<6> op, bits<5> mfmt> 201{ 202 bits<5> rt; 203 bits<5> rd; 204 bits<3> sel; 205 206 bits<32> Inst; 207 208 let Inst{31-26} = op; 209 let Inst{25-21} = mfmt; 210 let Inst{20-16} = rt; 211 let Inst{15-11} = rd; 212 let Inst{10-3} = 0; 213 let Inst{2-0} = sel; 214} 215 216class ADD_FM<bits<6> op, bits<6> funct> : StdArch { 217 bits<5> rd; 218 bits<5> rs; 219 bits<5> rt; 220 221 bits<32> Inst; 222 223 let Inst{31-26} = op; 224 let Inst{25-21} = rs; 225 let Inst{20-16} = rt; 226 let Inst{15-11} = rd; 227 let Inst{10-6} = 0; 228 let Inst{5-0} = funct; 229} 230 231class ADDI_FM<bits<6> op> : StdArch { 232 bits<5> rs; 233 bits<5> rt; 234 bits<16> imm16; 235 236 bits<32> Inst; 237 238 let Inst{31-26} = op; 239 let Inst{25-21} = rs; 240 let Inst{20-16} = rt; 241 let Inst{15-0} = imm16; 242} 243 244class SRA_FM<bits<6> funct, bit rotate> : StdArch { 245 bits<5> rd; 246 bits<5> rt; 247 bits<5> shamt; 248 249 bits<32> Inst; 250 251 let Inst{31-26} = 0; 252 let Inst{25-22} = 0; 253 let Inst{21} = rotate; 254 let Inst{20-16} = rt; 255 let Inst{15-11} = rd; 256 let Inst{10-6} = shamt; 257 let Inst{5-0} = funct; 258} 259 260class SRLV_FM<bits<6> funct, bit rotate> : StdArch { 261 bits<5> rd; 262 bits<5> rt; 263 bits<5> rs; 264 265 bits<32> Inst; 266 267 let Inst{31-26} = 0; 268 let Inst{25-21} = rs; 269 let Inst{20-16} = rt; 270 let Inst{15-11} = rd; 271 let Inst{10-7} = 0; 272 let Inst{6} = rotate; 273 let Inst{5-0} = funct; 274} 275 276class BEQ_FM<bits<6> op> { 277 bits<5> rs; 278 bits<5> rt; 279 bits<16> offset; 280 281 bits<32> Inst; 282 283 let Inst{31-26} = op; 284 let Inst{25-21} = rs; 285 let Inst{20-16} = rt; 286 let Inst{15-0} = offset; 287} 288 289class BGEZ_FM<bits<6> op, bits<5> funct> { 290 bits<5> rs; 291 bits<16> offset; 292 293 bits<32> Inst; 294 295 let Inst{31-26} = op; 296 let Inst{25-21} = rs; 297 let Inst{20-16} = funct; 298 let Inst{15-0} = offset; 299} 300 301class B_FM { 302 bits<16> offset; 303 304 bits<32> Inst; 305 306 let Inst{31-26} = 4; 307 let Inst{25-21} = 0; 308 let Inst{20-16} = 0; 309 let Inst{15-0} = offset; 310} 311 312class SLTI_FM<bits<6> op> : StdArch { 313 bits<5> rt; 314 bits<5> rs; 315 bits<16> imm16; 316 317 bits<32> Inst; 318 319 let Inst{31-26} = op; 320 let Inst{25-21} = rs; 321 let Inst{20-16} = rt; 322 let Inst{15-0} = imm16; 323} 324 325class MFLO_FM<bits<6> funct> { 326 bits<5> rd; 327 328 bits<32> Inst; 329 330 let Inst{31-26} = 0; 331 let Inst{25-16} = 0; 332 let Inst{15-11} = rd; 333 let Inst{10-6} = 0; 334 let Inst{5-0} = funct; 335} 336 337class MTLO_FM<bits<6> funct> { 338 bits<5> rs; 339 340 bits<32> Inst; 341 342 let Inst{31-26} = 0; 343 let Inst{25-21} = rs; 344 let Inst{20-6} = 0; 345 let Inst{5-0} = funct; 346} 347 348class SEB_FM<bits<5> funct, bits<6> funct2> { 349 bits<5> rd; 350 bits<5> rt; 351 352 bits<32> Inst; 353 354 let Inst{31-26} = 0x1f; 355 let Inst{25-21} = 0; 356 let Inst{20-16} = rt; 357 let Inst{15-11} = rd; 358 let Inst{10-6} = funct; 359 let Inst{5-0} = funct2; 360} 361 362class CLO_FM<bits<6> funct> { 363 bits<5> rd; 364 bits<5> rs; 365 bits<5> rt; 366 367 bits<32> Inst; 368 369 let Inst{31-26} = 0x1c; 370 let Inst{25-21} = rs; 371 let Inst{20-16} = rt; 372 let Inst{15-11} = rd; 373 let Inst{10-6} = 0; 374 let Inst{5-0} = funct; 375 let rt = rd; 376} 377 378class LUI_FM { 379 bits<5> rt; 380 bits<16> imm16; 381 382 bits<32> Inst; 383 384 let Inst{31-26} = 0xf; 385 let Inst{25-21} = 0; 386 let Inst{20-16} = rt; 387 let Inst{15-0} = imm16; 388} 389 390class JALR_FM { 391 bits<5> rd; 392 bits<5> rs; 393 394 bits<32> Inst; 395 396 let Inst{31-26} = 0; 397 let Inst{25-21} = rs; 398 let Inst{20-16} = 0; 399 let Inst{15-11} = rd; 400 let Inst{10-6} = 0; 401 let Inst{5-0} = 9; 402} 403 404class BAL_FM { 405 bits<16> offset; 406 407 bits<32> Inst; 408 409 let Inst{31-26} = 1; 410 let Inst{25-21} = 0; 411 let Inst{20-16} = 0x11; 412 let Inst{15-0} = offset; 413} 414 415class BGEZAL_FM<bits<5> funct> { 416 bits<5> rs; 417 bits<16> offset; 418 419 bits<32> Inst; 420 421 let Inst{31-26} = 1; 422 let Inst{25-21} = rs; 423 let Inst{20-16} = funct; 424 let Inst{15-0} = offset; 425} 426 427class SYNC_FM { 428 bits<5> stype; 429 430 bits<32> Inst; 431 432 let Inst{31-26} = 0; 433 let Inst{10-6} = stype; 434 let Inst{5-0} = 0xf; 435} 436 437class MULT_FM<bits<6> op, bits<6> funct> : StdArch { 438 bits<5> rs; 439 bits<5> rt; 440 441 bits<32> Inst; 442 443 let Inst{31-26} = op; 444 let Inst{25-21} = rs; 445 let Inst{20-16} = rt; 446 let Inst{15-6} = 0; 447 let Inst{5-0} = funct; 448} 449 450class EXT_FM<bits<6> funct> { 451 bits<5> rt; 452 bits<5> rs; 453 bits<5> pos; 454 bits<5> size; 455 456 bits<32> Inst; 457 458 let Inst{31-26} = 0x1f; 459 let Inst{25-21} = rs; 460 let Inst{20-16} = rt; 461 let Inst{15-11} = size; 462 let Inst{10-6} = pos; 463 let Inst{5-0} = funct; 464} 465 466class RDHWR_FM { 467 bits<5> rt; 468 bits<5> rd; 469 470 bits<32> Inst; 471 472 let Inst{31-26} = 0x1f; 473 let Inst{25-21} = 0; 474 let Inst{20-16} = rt; 475 let Inst{15-11} = rd; 476 let Inst{10-6} = 0; 477 let Inst{5-0} = 0x3b; 478} 479 480class TEQ_FM<bits<6> funct> { 481 bits<5> rs; 482 bits<5> rt; 483 bits<10> code_; 484 485 bits<32> Inst; 486 487 let Inst{31-26} = 0; 488 let Inst{25-21} = rs; 489 let Inst{20-16} = rt; 490 let Inst{15-6} = code_; 491 let Inst{5-0} = funct; 492} 493 494//===----------------------------------------------------------------------===// 495// System calls format <op|code_|funct> 496//===----------------------------------------------------------------------===// 497 498class SYS_FM<bits<6> funct> 499{ 500 bits<20> code_; 501 bits<32> Inst; 502 let Inst{31-26} = 0x0; 503 let Inst{25-6} = code_; 504 let Inst{5-0} = funct; 505} 506 507//===----------------------------------------------------------------------===// 508// Break instruction format <op|code_1|funct> 509//===----------------------------------------------------------------------===// 510 511class BRK_FM<bits<6> funct> 512{ 513 bits<10> code_1; 514 bits<10> code_2; 515 bits<32> Inst; 516 let Inst{31-26} = 0x0; 517 let Inst{25-16} = code_1; 518 let Inst{15-6} = code_2; 519 let Inst{5-0} = funct; 520} 521 522//===----------------------------------------------------------------------===// 523// Exception return format <Cop0|1|0|funct> 524//===----------------------------------------------------------------------===// 525 526class ER_FM<bits<6> funct> 527{ 528 bits<32> Inst; 529 let Inst{31-26} = 0x10; 530 let Inst{25} = 1; 531 let Inst{24-6} = 0; 532 let Inst{5-0} = funct; 533} 534 535//===----------------------------------------------------------------------===// 536// 537// FLOATING POINT INSTRUCTION FORMATS 538// 539// opcode - operation code. 540// fs - src reg. 541// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 542// fd - dst reg, only used on 3 regs instr. 543// fmt - double or single precision. 544// funct - combined with opcode field give us an operation code. 545// 546//===----------------------------------------------------------------------===// 547 548//===----------------------------------------------------------------------===// 549// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 550//===----------------------------------------------------------------------===// 551 552class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 553 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 554{ 555 bits<5> ft; 556 bits<5> base; 557 bits<16> imm16; 558 559 let Opcode = op; 560 561 let Inst{25-21} = base; 562 let Inst{20-16} = ft; 563 let Inst{15-0} = imm16; 564} 565 566class ADDS_FM<bits<6> funct, bits<5> fmt> { 567 bits<5> fd; 568 bits<5> fs; 569 bits<5> ft; 570 571 bits<32> Inst; 572 573 let Inst{31-26} = 0x11; 574 let Inst{25-21} = fmt; 575 let Inst{20-16} = ft; 576 let Inst{15-11} = fs; 577 let Inst{10-6} = fd; 578 let Inst{5-0} = funct; 579} 580 581class ABSS_FM<bits<6> funct, bits<5> fmt> { 582 bits<5> fd; 583 bits<5> fs; 584 585 bits<32> Inst; 586 587 let Inst{31-26} = 0x11; 588 let Inst{25-21} = fmt; 589 let Inst{20-16} = 0; 590 let Inst{15-11} = fs; 591 let Inst{10-6} = fd; 592 let Inst{5-0} = funct; 593} 594 595class MFC1_FM<bits<5> funct> { 596 bits<5> rt; 597 bits<5> fs; 598 599 bits<32> Inst; 600 601 let Inst{31-26} = 0x11; 602 let Inst{25-21} = funct; 603 let Inst{20-16} = rt; 604 let Inst{15-11} = fs; 605 let Inst{10-0} = 0; 606} 607 608class LW_FM<bits<6> op> : StdArch { 609 bits<5> rt; 610 bits<21> addr; 611 612 bits<32> Inst; 613 614 let Inst{31-26} = op; 615 let Inst{25-21} = addr{20-16}; 616 let Inst{20-16} = rt; 617 let Inst{15-0} = addr{15-0}; 618} 619 620class MADDS_FM<bits<3> funct, bits<3> fmt> { 621 bits<5> fd; 622 bits<5> fr; 623 bits<5> fs; 624 bits<5> ft; 625 626 bits<32> Inst; 627 628 let Inst{31-26} = 0x13; 629 let Inst{25-21} = fr; 630 let Inst{20-16} = ft; 631 let Inst{15-11} = fs; 632 let Inst{10-6} = fd; 633 let Inst{5-3} = funct; 634 let Inst{2-0} = fmt; 635} 636 637class LWXC1_FM<bits<6> funct> { 638 bits<5> fd; 639 bits<5> base; 640 bits<5> index; 641 642 bits<32> Inst; 643 644 let Inst{31-26} = 0x13; 645 let Inst{25-21} = base; 646 let Inst{20-16} = index; 647 let Inst{15-11} = 0; 648 let Inst{10-6} = fd; 649 let Inst{5-0} = funct; 650} 651 652class SWXC1_FM<bits<6> funct> { 653 bits<5> fs; 654 bits<5> base; 655 bits<5> index; 656 657 bits<32> Inst; 658 659 let Inst{31-26} = 0x13; 660 let Inst{25-21} = base; 661 let Inst{20-16} = index; 662 let Inst{15-11} = fs; 663 let Inst{10-6} = 0; 664 let Inst{5-0} = funct; 665} 666 667class BC1F_FM<bit nd, bit tf> { 668 bits<3> fcc; 669 bits<16> offset; 670 671 bits<32> Inst; 672 673 let Inst{31-26} = 0x11; 674 let Inst{25-21} = 0x8; 675 let Inst{20-18} = fcc; 676 let Inst{17} = nd; 677 let Inst{16} = tf; 678 let Inst{15-0} = offset; 679} 680 681class CEQS_FM<bits<5> fmt> { 682 bits<5> fs; 683 bits<5> ft; 684 bits<4> cond; 685 686 bits<32> Inst; 687 688 let Inst{31-26} = 0x11; 689 let Inst{25-21} = fmt; 690 let Inst{20-16} = ft; 691 let Inst{15-11} = fs; 692 let Inst{10-8} = 0; // cc 693 let Inst{7-4} = 0x3; 694 let Inst{3-0} = cond; 695} 696 697class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 698 let cond = c; 699} 700 701class CMov_I_F_FM<bits<6> funct, bits<5> fmt> { 702 bits<5> fd; 703 bits<5> fs; 704 bits<5> rt; 705 706 bits<32> Inst; 707 708 let Inst{31-26} = 0x11; 709 let Inst{25-21} = fmt; 710 let Inst{20-16} = rt; 711 let Inst{15-11} = fs; 712 let Inst{10-6} = fd; 713 let Inst{5-0} = funct; 714} 715 716class CMov_F_I_FM<bit tf> { 717 bits<5> rd; 718 bits<5> rs; 719 bits<3> fcc; 720 721 bits<32> Inst; 722 723 let Inst{31-26} = 0; 724 let Inst{25-21} = rs; 725 let Inst{20-18} = fcc; 726 let Inst{17} = 0; 727 let Inst{16} = tf; 728 let Inst{15-11} = rd; 729 let Inst{10-6} = 0; 730 let Inst{5-0} = 1; 731} 732 733class CMov_F_F_FM<bits<5> fmt, bit tf> { 734 bits<5> fd; 735 bits<5> fs; 736 bits<3> fcc; 737 738 bits<32> Inst; 739 740 let Inst{31-26} = 0x11; 741 let Inst{25-21} = fmt; 742 let Inst{20-18} = fcc; 743 let Inst{17} = 0; 744 let Inst{16} = tf; 745 let Inst{15-11} = fs; 746 let Inst{10-6} = fd; 747 let Inst{5-0} = 0x11; 748} 749