MipsInstrFormats.td revision 5f560bb2ebd9b489750fafd0c2d7c5136d18c622 
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39// Generic Mips Format
40class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41               InstrItinClass itin, Format f>: Instruction
42{
43  field bits<32> Inst;
44  Format Form = f;
45
46  let Namespace = "Mips";
47
48  let Size = 4;
49
50  bits<6> Opcode = 0;
51
52  // Top 6 bits are the 'opcode' field
53  let Inst{31-26} = Opcode;
54
55  let OutOperandList = outs;
56  let InOperandList  = ins;
57
58  let AsmString   = asmstr;
59  let Pattern     = pattern;
60  let Itinerary   = itin;
61
62  //
63  // Attributes specific to Mips instructions...
64  //
65  bits<4> FormBits = Form.Value;
66
67  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68  let TSFlags{3-0}   = FormBits;
69
70  let DecoderNamespace = "Mips";
71
72  field bits<32> SoftFail = 0;
73}
74
75// Mips32/64 Instruction Format
76class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77             InstrItinClass itin, Format f>:
78  MipsInst<outs, ins, asmstr, pattern, itin, f> {
79  let Predicates = [HasStdEnc];
80}
81
82// Mips Pseudo Instructions Format
83class MipsPseudo<dag outs, dag ins, list<dag> pattern,
84                 InstrItinClass itin = IIPseudo> :
85  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
86  let isCodeGenOnly = 1;
87  let isPseudo = 1;
88}
89
90// Mips32/64 Pseudo Instruction Format
91class PseudoSE<dag outs, dag ins, list<dag> pattern,
92               InstrItinClass itin = IIPseudo>:
93  MipsPseudo<outs, ins, pattern, itin> {
94  let Predicates = [HasStdEnc];
95}
96
97// Pseudo-instructions for alternate assembly syntax (never used by codegen).
98// These are aliases that require C++ handling to convert to the target
99// instruction, while InstAliases can be handled directly by tblgen.
100class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
101  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
102  let isPseudo = 1;
103  let Pattern = [];
104}
105//===----------------------------------------------------------------------===//
106// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
107//===----------------------------------------------------------------------===//
108
109class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
110         list<dag> pattern, InstrItinClass itin>:
111  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
112{
113  bits<5>  rd;
114  bits<5>  rs;
115  bits<5>  rt;
116  bits<5>  shamt;
117  bits<6>  funct;
118
119  let Opcode = op;
120  let funct  = _funct;
121
122  let Inst{25-21} = rs;
123  let Inst{20-16} = rt;
124  let Inst{15-11} = rd;
125  let Inst{10-6}  = shamt;
126  let Inst{5-0}   = funct;
127}
128
129//===----------------------------------------------------------------------===//
130// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
131//===----------------------------------------------------------------------===//
132
133class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
134         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
135{
136  bits<5>  rt;
137  bits<5>  rs;
138  bits<16> imm16;
139
140  let Opcode = op;
141
142  let Inst{25-21} = rs;
143  let Inst{20-16} = rt;
144  let Inst{15-0}  = imm16;
145}
146
147class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
148                  list<dag> pattern, InstrItinClass itin>:
149  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
150{
151  bits<5>  rs;
152  bits<5>  rt;
153  bits<16> imm16;
154
155  let Opcode = op;
156
157  let Inst{25-21} = rs;
158  let Inst{20-16} = rt;
159  let Inst{15-0}  = imm16;
160}
161
162//===----------------------------------------------------------------------===//
163// Format J instruction class in Mips : <|opcode|address|>
164//===----------------------------------------------------------------------===//
165
166class FJ<bits<6> op>
167{
168  bits<26> target;
169
170  bits<32> Inst;
171
172  let Inst{31-26} = op;
173  let Inst{25-0}  = target;
174}
175
176 //===----------------------------------------------------------------------===//
177// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
178//===----------------------------------------------------------------------===//
179class MFC3OP_FM<bits<6> op, bits<5> mfmt>
180{
181  bits<5> rt;
182  bits<5> rd;
183  bits<3> sel;
184
185  bits<32> Inst;
186
187  let Inst{31-26} = op;
188  let Inst{25-21} = mfmt;
189  let Inst{20-16} = rt;
190  let Inst{15-11} = rd;
191  let Inst{10-3}  = 0;
192  let Inst{2-0}   = sel;
193}
194
195class ADD_FM<bits<6> op, bits<6> funct> {
196  bits<5> rd;
197  bits<5> rs;
198  bits<5> rt;
199
200  bits<32> Inst;
201
202  let Inst{31-26} = op;
203  let Inst{25-21} = rs;
204  let Inst{20-16} = rt;
205  let Inst{15-11} = rd;
206  let Inst{10-6}  = 0;
207  let Inst{5-0}   = funct;
208}
209
210class ADDI_FM<bits<6> op> {
211  bits<5>  rs;
212  bits<5>  rt;
213  bits<16> imm16;
214
215  bits<32> Inst;
216
217  let Inst{31-26} = op;
218  let Inst{25-21} = rs;
219  let Inst{20-16} = rt;
220  let Inst{15-0}  = imm16;
221}
222
223class SRA_FM<bits<6> funct, bit rotate> {
224  bits<5> rd;
225  bits<5> rt;
226  bits<5> shamt;
227
228  bits<32> Inst;
229
230  let Inst{31-26} = 0;
231  let Inst{25-22} = 0;
232  let Inst{21}    = rotate;
233  let Inst{20-16} = rt;
234  let Inst{15-11} = rd;
235  let Inst{10-6}  = shamt;
236  let Inst{5-0}   = funct;
237}
238
239class SRLV_FM<bits<6> funct, bit rotate> {
240  bits<5> rd;
241  bits<5> rt;
242  bits<5> rs;
243
244  bits<32> Inst;
245
246  let Inst{31-26} = 0;
247  let Inst{25-21} = rs;
248  let Inst{20-16} = rt;
249  let Inst{15-11} = rd;
250  let Inst{10-7}  = 0;
251  let Inst{6}     = rotate;
252  let Inst{5-0}   = funct;
253}
254
255class BEQ_FM<bits<6> op> {
256  bits<5>  rs;
257  bits<5>  rt;
258  bits<16> offset;
259
260  bits<32> Inst;
261
262  let Inst{31-26} = op;
263  let Inst{25-21} = rs;
264  let Inst{20-16} = rt;
265  let Inst{15-0}  = offset;
266}
267
268class BGEZ_FM<bits<6> op, bits<5> funct> {
269  bits<5>  rs;
270  bits<16> offset;
271
272  bits<32> Inst;
273
274  let Inst{31-26} = op;
275  let Inst{25-21} = rs;
276  let Inst{20-16} = funct;
277  let Inst{15-0}  = offset;
278}
279
280class B_FM {
281  bits<16> offset;
282
283  bits<32> Inst;
284
285  let Inst{31-26} = 4;
286  let Inst{25-21} = 0;
287  let Inst{20-16} = 0;
288  let Inst{15-0}  = offset;
289}
290
291class SLTI_FM<bits<6> op> {
292  bits<5> rt;
293  bits<5> rs;
294  bits<16> imm16;
295
296  bits<32> Inst;
297
298  let Inst{31-26} = op;
299  let Inst{25-21} = rs;
300  let Inst{20-16} = rt;
301  let Inst{15-0}  = imm16;
302}
303
304class MFLO_FM<bits<6> funct> {
305  bits<5> rd;
306
307  bits<32> Inst;
308
309  let Inst{31-26} = 0;
310  let Inst{25-16} = 0;
311  let Inst{15-11} = rd;
312  let Inst{10-6}  = 0;
313  let Inst{5-0}   = funct;
314}
315
316class MTLO_FM<bits<6> funct> {
317  bits<5> rs;
318
319  bits<32> Inst;
320
321  let Inst{31-26} = 0;
322  let Inst{25-21} = rs;
323  let Inst{20-6}  = 0;
324  let Inst{5-0}   = funct;
325}
326
327class SEB_FM<bits<5> funct, bits<6> funct2> {
328  bits<5> rd;
329  bits<5> rt;
330
331  bits<32> Inst;
332
333  let Inst{31-26} = 0x1f;
334  let Inst{25-21} = 0;
335  let Inst{20-16} = rt;
336  let Inst{15-11} = rd;
337  let Inst{10-6}  = funct;
338  let Inst{5-0}   = funct2;
339}
340
341class CLO_FM<bits<6> funct> {
342  bits<5> rd;
343  bits<5> rs;
344  bits<5> rt;
345
346  bits<32> Inst;
347
348  let Inst{31-26} = 0x1c;
349  let Inst{25-21} = rs;
350  let Inst{20-16} = rt;
351  let Inst{15-11} = rd;
352  let Inst{10-6}  = 0;
353  let Inst{5-0}   = funct;
354  let rt = rd;
355}
356
357class LUI_FM {
358  bits<5> rt;
359  bits<16> imm16;
360
361  bits<32> Inst;
362
363  let Inst{31-26} = 0xf;
364  let Inst{25-21} = 0;
365  let Inst{20-16} = rt;
366  let Inst{15-0}  = imm16;
367}
368
369class NOP_FM {
370  bits<32> Inst;
371
372  let Inst{31-0} = 0;
373}
374
375class JALR_FM {
376  bits<5> rs;
377
378  bits<32> Inst;
379
380  let Inst{31-26} = 0;
381  let Inst{25-21} = rs;
382  let Inst{20-16} = 0;
383  let Inst{15-11} = 31;
384  let Inst{10-6}  = 0;
385  let Inst{5-0}   = 9;
386}
387
388class BAL_FM {
389  bits<16> offset;
390
391  bits<32> Inst;
392
393  let Inst{31-26} = 1;
394  let Inst{25-21} = 0;
395  let Inst{20-16} = 0x11;
396  let Inst{15-0}  = offset;
397}
398
399class BGEZAL_FM<bits<5> funct> {
400  bits<5>  rs;
401  bits<16> offset;
402
403  bits<32> Inst;
404
405  let Inst{31-26} = 1;
406  let Inst{25-21} = rs;
407  let Inst{20-16} = funct;
408  let Inst{15-0}  = offset;
409}
410
411class SYNC_FM {
412  bits<5> stype;
413
414  bits<32> Inst;
415
416  let Inst{31-26} = 0;
417  let Inst{10-6}  = stype;
418  let Inst{5-0}   = 0xf;
419}
420
421class MULT_FM<bits<6> op, bits<6> funct> {
422  bits<5>  rs;
423  bits<5>  rt;
424
425  bits<32> Inst;
426
427  let Inst{31-26} = op;
428  let Inst{25-21} = rs;
429  let Inst{20-16} = rt;
430  let Inst{15-6}  = 0;
431  let Inst{5-0}   = funct;
432}
433
434class EXT_FM<bits<6> funct> {
435  bits<5> rt;
436  bits<5> rs;
437  bits<5> pos;
438  bits<5> size;
439
440  bits<32> Inst;
441
442  let Inst{31-26} = 0x1f;
443  let Inst{25-21} = rs;
444  let Inst{20-16} = rt;
445  let Inst{15-11} = size;
446  let Inst{10-6}  = pos;
447  let Inst{5-0}   = funct;
448}
449
450class RDHWR_FM {
451  bits<5> rt;
452  bits<5> rd;
453
454  bits<32> Inst;
455
456  let Inst{31-26} = 0x1f;
457  let Inst{25-21} = 0;
458  let Inst{20-16} = rt;
459  let Inst{15-11} = rd;
460  let Inst{10-6}  = 0;
461  let Inst{5-0}   = 0x3b;
462}
463
464//===----------------------------------------------------------------------===//
465//
466//  FLOATING POINT INSTRUCTION FORMATS
467//
468//  opcode  - operation code.
469//  fs      - src reg.
470//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
471//  fd      - dst reg, only used on 3 regs instr.
472//  fmt     - double or single precision.
473//  funct   - combined with opcode field give us an operation code.
474//
475//===----------------------------------------------------------------------===//
476
477//===----------------------------------------------------------------------===//
478// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
479//===----------------------------------------------------------------------===//
480
481class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
482  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
483{
484  bits<5>  ft;
485  bits<5>  base;
486  bits<16> imm16;
487
488  let Opcode = op;
489
490  let Inst{25-21} = base;
491  let Inst{20-16} = ft;
492  let Inst{15-0}  = imm16;
493}
494
495class ADDS_FM<bits<6> funct, bits<5> fmt> {
496  bits<5> fd;
497  bits<5> fs;
498  bits<5> ft;
499
500  bits<32> Inst;
501
502  let Inst{31-26} = 0x11;
503  let Inst{25-21} = fmt;
504  let Inst{20-16} = ft;
505  let Inst{15-11} = fs;
506  let Inst{10-6}  = fd;
507  let Inst{5-0}   = funct;
508}
509
510class ABSS_FM<bits<6> funct, bits<5> fmt> {
511  bits<5> fd;
512  bits<5> fs;
513
514  bits<32> Inst;
515
516  let Inst{31-26} = 0x11;
517  let Inst{25-21} = fmt;
518  let Inst{20-16} = 0;
519  let Inst{15-11} = fs;
520  let Inst{10-6}  = fd;
521  let Inst{5-0}   = funct;
522}
523
524class MFC1_FM<bits<5> funct> {
525  bits<5> rt;
526  bits<5> fs;
527
528  bits<32> Inst;
529
530  let Inst{31-26} = 0x11;
531  let Inst{25-21} = funct;
532  let Inst{20-16} = rt;
533  let Inst{15-11} = fs;
534  let Inst{10-0}  = 0;
535}
536
537class LW_FM<bits<6> op> {
538  bits<5> rt;
539  bits<21> addr;
540
541  bits<32> Inst;
542
543  let Inst{31-26} = op;
544  let Inst{25-21} = addr{20-16};
545  let Inst{20-16} = rt;
546  let Inst{15-0}  = addr{15-0};
547}
548
549class MADDS_FM<bits<3> funct, bits<3> fmt> {
550  bits<5> fd;
551  bits<5> fr;
552  bits<5> fs;
553  bits<5> ft;
554
555  bits<32> Inst;
556
557  let Inst{31-26} = 0x13;
558  let Inst{25-21} = fr;
559  let Inst{20-16} = ft;
560  let Inst{15-11} = fs;
561  let Inst{10-6}  = fd;
562  let Inst{5-3}   = funct;
563  let Inst{2-0}   = fmt;
564}
565
566class LWXC1_FM<bits<6> funct> {
567  bits<5> fd;
568  bits<5> base;
569  bits<5> index;
570
571  bits<32> Inst;
572
573  let Inst{31-26} = 0x13;
574  let Inst{25-21} = base;
575  let Inst{20-16} = index;
576  let Inst{15-11} = 0;
577  let Inst{10-6}  = fd;
578  let Inst{5-0}   = funct;
579}
580
581class SWXC1_FM<bits<6> funct> {
582  bits<5> fs;
583  bits<5> base;
584  bits<5> index;
585
586  bits<32> Inst;
587
588  let Inst{31-26} = 0x13;
589  let Inst{25-21} = base;
590  let Inst{20-16} = index;
591  let Inst{15-11} = fs;
592  let Inst{10-6}  = 0;
593  let Inst{5-0}   = funct;
594}
595
596class BC1F_FM<bit nd, bit tf> {
597  bits<16> offset;
598
599  bits<32> Inst;
600
601  let Inst{31-26} = 0x11;
602  let Inst{25-21} = 0x8;
603  let Inst{20-18} = 0; // cc
604  let Inst{17} = nd;
605  let Inst{16} = tf;
606  let Inst{15-0} = offset;
607}
608
609class CEQS_FM<bits<5> fmt> {
610  bits<5> fs;
611  bits<5> ft;
612  bits<4> cond;
613
614  bits<32> Inst;
615
616  let Inst{31-26} = 0x11;
617  let Inst{25-21} = fmt;
618  let Inst{20-16} = ft;
619  let Inst{15-11} = fs;
620  let Inst{10-8} = 0; // cc
621  let Inst{7-4} = 0x3;
622  let Inst{3-0} = cond;
623}
624
625class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
626  bits<5> fd;
627  bits<5> fs;
628  bits<5> rt;
629
630  bits<32> Inst;
631
632  let Inst{31-26} = 0x11;
633  let Inst{25-21} = fmt;
634  let Inst{20-16} = rt;
635  let Inst{15-11} = fs;
636  let Inst{10-6} = fd;
637  let Inst{5-0} = funct;
638}
639
640class CMov_F_I_FM<bit tf> {
641  bits<5> rd;
642  bits<5> rs;
643
644  bits<32> Inst;
645
646  let Inst{31-26} = 0;
647  let Inst{25-21} = rs;
648  let Inst{20-18} = 0; // cc
649  let Inst{17} = 0;
650  let Inst{16} = tf;
651  let Inst{15-11} = rd;
652  let Inst{10-6} = 0;
653  let Inst{5-0} = 1;
654}
655
656class CMov_F_F_FM<bits<5> fmt, bit tf> {
657  bits<5> fd;
658  bits<5> fs;
659
660  bits<32> Inst;
661
662  let Inst{31-26} = 0x11;
663  let Inst{25-21} = fmt;
664  let Inst{20-18} = 0; // cc
665  let Inst{17} = 0;
666  let Inst{16} = tf;
667  let Inst{15-11} = fs;
668  let Inst{10-6} = fd;
669  let Inst{5-0} = 0x11;
670}
671