MipsInstrFormats.td revision 9d577c861414c28967d77c2a1edf64b68efdeaee
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39// Generic Mips Format 40class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 41 InstrItinClass itin, Format f>: Instruction 42{ 43 field bits<32> Inst; 44 Format Form = f; 45 46 let Namespace = "Mips"; 47 48 let Size = 4; 49 50 bits<6> Opcode = 0; 51 52 // Top 6 bits are the 'opcode' field 53 let Inst{31-26} = Opcode; 54 55 let OutOperandList = outs; 56 let InOperandList = ins; 57 58 let AsmString = asmstr; 59 let Pattern = pattern; 60 let Itinerary = itin; 61 62 // 63 // Attributes specific to Mips instructions... 64 // 65 bits<4> FormBits = Form.Value; 66 67 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 68 let TSFlags{3-0} = FormBits; 69 70 let DecoderNamespace = "Mips"; 71 72 field bits<32> SoftFail = 0; 73} 74 75// Mips32/64 Instruction Format 76class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 77 InstrItinClass itin, Format f>: 78 MipsInst<outs, ins, asmstr, pattern, itin, f> { 79 let Predicates = [HasStandardEncoding]; 80} 81 82// Mips Pseudo Instructions Format 83class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: 84 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> { 85 let isCodeGenOnly = 1; 86 let isPseudo = 1; 87} 88 89// Mips32/64 Pseudo Instruction Format 90class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>: 91 MipsPseudo<outs, ins, asmstr, pattern> { 92 let Predicates = [HasStandardEncoding]; 93} 94 95// Pseudo-instructions for alternate assembly syntax (never used by codegen). 96// These are aliases that require C++ handling to convert to the target 97// instruction, while InstAliases can be handled directly by tblgen. 98class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 99 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 100 let isPseudo = 1; 101 let Pattern = []; 102} 103//===----------------------------------------------------------------------===// 104// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 105//===----------------------------------------------------------------------===// 106 107class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 108 list<dag> pattern, InstrItinClass itin>: 109 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 110{ 111 bits<5> rd; 112 bits<5> rs; 113 bits<5> rt; 114 bits<5> shamt; 115 bits<6> funct; 116 117 let Opcode = op; 118 let funct = _funct; 119 120 let Inst{25-21} = rs; 121 let Inst{20-16} = rt; 122 let Inst{15-11} = rd; 123 let Inst{10-6} = shamt; 124 let Inst{5-0} = funct; 125} 126 127//===----------------------------------------------------------------------===// 128// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 129//===----------------------------------------------------------------------===// 130 131class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 132 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 133{ 134 bits<5> rt; 135 bits<5> rs; 136 bits<16> imm16; 137 138 let Opcode = op; 139 140 let Inst{25-21} = rs; 141 let Inst{20-16} = rt; 142 let Inst{15-0} = imm16; 143} 144 145class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 146 list<dag> pattern, InstrItinClass itin>: 147 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 148{ 149 bits<5> rs; 150 bits<5> rt; 151 bits<16> imm16; 152 153 let Opcode = op; 154 155 let Inst{25-21} = rs; 156 let Inst{20-16} = rt; 157 let Inst{15-0} = imm16; 158} 159 160//===----------------------------------------------------------------------===// 161// Format J instruction class in Mips : <|opcode|address|> 162//===----------------------------------------------------------------------===// 163 164class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 165 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ> 166{ 167 bits<26> addr; 168 169 let Opcode = op; 170 171 let Inst{25-0} = addr; 172} 173 174//===----------------------------------------------------------------------===// 175// 176// FLOATING POINT INSTRUCTION FORMATS 177// 178// opcode - operation code. 179// fs - src reg. 180// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 181// fd - dst reg, only used on 3 regs instr. 182// fmt - double or single precision. 183// funct - combined with opcode field give us an operation code. 184// 185//===----------------------------------------------------------------------===// 186 187//===----------------------------------------------------------------------===// 188// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|> 189//===----------------------------------------------------------------------===// 190 191class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins, 192 string asmstr, list<dag> pattern> : 193 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFR> 194{ 195 bits<5> fd; 196 bits<5> fs; 197 bits<5> ft; 198 bits<5> fmt; 199 bits<6> funct; 200 201 let Opcode = op; 202 let funct = _funct; 203 let fmt = _fmt; 204 205 let Inst{25-21} = fmt; 206 let Inst{20-16} = ft; 207 let Inst{15-11} = fs; 208 let Inst{10-6} = fd; 209 let Inst{5-0} = funct; 210} 211 212//===----------------------------------------------------------------------===// 213// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 214//===----------------------------------------------------------------------===// 215 216class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 217 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 218{ 219 bits<5> ft; 220 bits<5> base; 221 bits<16> imm16; 222 223 let Opcode = op; 224 225 let Inst{25-21} = base; 226 let Inst{20-16} = ft; 227 let Inst{15-0} = imm16; 228} 229 230//===----------------------------------------------------------------------===// 231// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|> 232//===----------------------------------------------------------------------===// 233 234class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> : 235 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 236{ 237 bits<5> fs; 238 bits<5> ft; 239 bits<4> cc; 240 bits<5> fmt; 241 242 let Opcode = 0x11; 243 let fmt = _fmt; 244 245 let Inst{25-21} = fmt; 246 let Inst{20-16} = ft; 247 let Inst{15-11} = fs; 248 let Inst{10-6} = 0; 249 let Inst{5-4} = 0b11; 250 let Inst{3-0} = cc; 251} 252 253 254class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr, 255 list<dag> pattern> : 256 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 257{ 258 bits<5> rd; 259 bits<5> rs; 260 bits<3> cc; 261 bits<1> tf; 262 263 let Opcode = 0; 264 let tf = _tf; 265 266 let Inst{25-21} = rs; 267 let Inst{20-18} = cc; 268 let Inst{17} = 0; 269 let Inst{16} = tf; 270 let Inst{15-11} = rd; 271 let Inst{10-6} = 0; 272 let Inst{5-0} = 1; 273} 274 275class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr, 276 list<dag> pattern> : 277 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 278{ 279 bits<5> fd; 280 bits<5> fs; 281 bits<3> cc; 282 bits<5> fmt; 283 bits<1> tf; 284 285 let Opcode = 17; 286 let fmt = _fmt; 287 let tf = _tf; 288 289 let Inst{25-21} = fmt; 290 let Inst{20-18} = cc; 291 let Inst{17} = 0; 292 let Inst{16} = tf; 293 let Inst{15-11} = fs; 294 let Inst{10-6} = fd; 295 let Inst{5-0} = 17; 296} 297 298// FP unary instructions without patterns. 299class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr, 300 RegisterClass DstRC, RegisterClass SrcRC> : 301 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), 302 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> { 303 let ft = 0; 304} 305 306// FP unary instructions with patterns. 307class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr, 308 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> : 309 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), 310 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), 311 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> { 312 let ft = 0; 313} 314 315class FFR2P<bits<6> funct, bits<5> fmt, string opstr, 316 string fmtstr, RegisterClass RC, SDNode OpNode> : 317 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft), 318 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"), 319 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>; 320 321// Floating point madd/msub/nmadd/nmsub. 322class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr, 323 list<dag> pattern> 324 : InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> { 325 bits<5> fd; 326 bits<5> fr; 327 bits<5> fs; 328 bits<5> ft; 329 330 let Opcode = 0x13; 331 let Inst{25-21} = fr; 332 let Inst{20-16} = ft; 333 let Inst{15-11} = fs; 334 let Inst{10-6} = fd; 335 let Inst{5-3} = funct; 336 let Inst{2-0} = fmt; 337} 338 339// FP indexed load/store instructions. 340class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr, 341 list<dag> pattern> : 342 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 343{ 344 bits<5> base; 345 bits<5> index; 346 bits<5> fs; 347 bits<5> fd; 348 349 let Opcode = 0x13; 350 351 let Inst{25-21} = base; 352 let Inst{20-16} = index; 353 let Inst{15-11} = fs; 354 let Inst{10-6} = fd; 355 let Inst{5-0} = funct; 356} 357