MipsInstrFormats.td revision c4388d41994dc7e4492392f0c57c7b281ff165e6 
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39// Generic Mips Format
40class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
41             InstrItinClass itin, Format f>: Instruction
42{
43  field bits<32> Inst;
44  Format Form = f;
45
46  let Namespace = "Mips";
47
48  let Size = 4;
49
50  bits<6> Opcode = 0;
51
52  // Top 6 bits are the 'opcode' field
53  let Inst{31-26} = Opcode;
54
55  let OutOperandList = outs;
56  let InOperandList  = ins;
57
58  let AsmString   = asmstr;
59  let Pattern     = pattern;
60  let Itinerary   = itin;
61
62  //
63  // Attributes specific to Mips instructions...
64  //
65  bits<4> FormBits = Form.Value;
66
67  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68  let TSFlags{3-0}   = FormBits;
69
70  let DecoderNamespace = "Mips";
71
72  field bits<32> SoftFail = 0;
73
74  let Predicates = [HasStandardEncoding];
75
76}
77
78// Mips Pseudo Instructions Format
79class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
80  InstSE<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
81  let isCodeGenOnly = 1;
82  let isPseudo = 1;
83}
84
85//===----------------------------------------------------------------------===//
86// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
87//===----------------------------------------------------------------------===//
88
89class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
90         list<dag> pattern, InstrItinClass itin>:
91  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
92{
93  bits<5>  rd;
94  bits<5>  rs;
95  bits<5>  rt;
96  bits<5>  shamt;
97  bits<6>  funct;
98
99  let Opcode = op;
100  let funct  = _funct;
101
102  let Inst{25-21} = rs;
103  let Inst{20-16} = rt;
104  let Inst{15-11} = rd;
105  let Inst{10-6}  = shamt;
106  let Inst{5-0}   = funct;
107}
108
109//===----------------------------------------------------------------------===//
110// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
111//===----------------------------------------------------------------------===//
112
113class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
114         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
115{
116  bits<5>  rt;
117  bits<5>  rs;
118  bits<16> imm16;
119
120  let Opcode = op;
121
122  let Inst{25-21} = rs;
123  let Inst{20-16} = rt;
124  let Inst{15-0}  = imm16;
125}
126
127class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
128                  list<dag> pattern, InstrItinClass itin>:
129  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
130{
131  bits<5>  rs;
132  bits<5>  rt;
133  bits<16> imm16;
134
135  let Opcode = op;
136
137  let Inst{25-21} = rs;
138  let Inst{20-16} = rt;
139  let Inst{15-0}  = imm16;
140}
141
142//===----------------------------------------------------------------------===//
143// Format J instruction class in Mips : <|opcode|address|>
144//===----------------------------------------------------------------------===//
145
146class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
147         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ>
148{
149  bits<26> addr;
150
151  let Opcode = op;
152
153  let Inst{25-0} = addr;
154}
155
156//===----------------------------------------------------------------------===//
157//
158//  FLOATING POINT INSTRUCTION FORMATS
159//
160//  opcode  - operation code.
161//  fs      - src reg.
162//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
163//  fd      - dst reg, only used on 3 regs instr.
164//  fmt     - double or single precision.
165//  funct   - combined with opcode field give us an operation code.
166//
167//===----------------------------------------------------------------------===//
168
169//===----------------------------------------------------------------------===//
170// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
171//===----------------------------------------------------------------------===//
172
173class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
174          string asmstr, list<dag> pattern> :
175  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFR>
176{
177  bits<5>  fd;
178  bits<5>  fs;
179  bits<5>  ft;
180  bits<5>  fmt;
181  bits<6>  funct;
182
183  let Opcode = op;
184  let funct  = _funct;
185  let fmt    = _fmt;
186
187  let Inst{25-21} = fmt;
188  let Inst{20-16} = ft;
189  let Inst{15-11} = fs;
190  let Inst{10-6}  = fd;
191  let Inst{5-0}   = funct;
192}
193
194//===----------------------------------------------------------------------===//
195// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
196//===----------------------------------------------------------------------===//
197
198class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
199  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
200{
201  bits<5>  ft;
202  bits<5>  base;
203  bits<16> imm16;
204
205  let Opcode = op;
206
207  let Inst{25-21} = base;
208  let Inst{20-16} = ft;
209  let Inst{15-0}  = imm16;
210}
211
212//===----------------------------------------------------------------------===//
213// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
214//===----------------------------------------------------------------------===//
215
216class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
217  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
218{
219  bits<5>  fs;
220  bits<5>  ft;
221  bits<4>  cc;
222  bits<5>  fmt;
223
224  let Opcode = 0x11;
225  let fmt    = _fmt;
226
227  let Inst{25-21} = fmt;
228  let Inst{20-16} = ft;
229  let Inst{15-11} = fs;
230  let Inst{10-6}  = 0;
231  let Inst{5-4}   = 0b11;
232  let Inst{3-0}   = cc;
233}
234
235
236class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
237            list<dag> pattern> :
238  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
239{
240  bits<5>  rd;
241  bits<5>  rs;
242  bits<3>  cc;
243  bits<1>  tf;
244
245  let Opcode = 0;
246  let tf = _tf;
247
248  let Inst{25-21} = rs;
249  let Inst{20-18} = cc;
250  let Inst{17} = 0;
251  let Inst{16} = tf;
252  let Inst{15-11} = rd;
253  let Inst{10-6}  = 0;
254  let Inst{5-0}   = 1;
255}
256
257class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
258             list<dag> pattern> :
259  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
260{
261  bits<5>  fd;
262  bits<5>  fs;
263  bits<3>  cc;
264  bits<5>  fmt;
265  bits<1>  tf;
266
267  let Opcode = 17;
268  let fmt = _fmt;
269  let tf = _tf;
270
271  let Inst{25-21} = fmt;
272  let Inst{20-18} = cc;
273  let Inst{17} = 0;
274  let Inst{16} = tf;
275  let Inst{15-11} = fs;
276  let Inst{10-6}  = fd;
277  let Inst{5-0}   = 17;
278}
279
280// FP unary instructions without patterns.
281class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
282           RegisterClass DstRC, RegisterClass SrcRC> :
283  FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
284      !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
285  let ft = 0;
286}
287
288// FP unary instructions with patterns.
289class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
290            RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
291  FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
292      !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
293      [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
294  let ft = 0;
295}
296
297class FFR2P<bits<6> funct, bits<5> fmt, string opstr,
298            string fmtstr, RegisterClass RC, SDNode OpNode> :
299  FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
300      !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
301      [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
302
303// Floating point madd/msub/nmadd/nmsub.
304class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr,
305                list<dag> pattern>
306  : InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> {
307  bits<5> fd;
308  bits<5> fr;
309  bits<5> fs;
310  bits<5> ft;
311
312  let Opcode = 0x13;
313  let Inst{25-21} = fr;
314  let Inst{20-16} = ft;
315  let Inst{15-11} = fs;
316  let Inst{10-6} = fd;
317  let Inst{5-3} = funct;
318  let Inst{2-0} = fmt;
319}
320
321// FP indexed load/store instructions.
322class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr,
323               list<dag> pattern> :
324  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
325{
326  bits<5>  base;
327  bits<5>  index;
328  bits<5>  fs;
329  bits<5>  fd;
330
331  let Opcode = 0x13;
332
333  let Inst{25-21} = base;
334  let Inst{20-16} = index;
335  let Inst{15-11} = fs;
336  let Inst{10-6} = fd;
337  let Inst{5-0} = funct;
338}
339