MipsInstrFormats.td revision c567b1cd0d6bf973a21df4b5c8cae37e5e7518f8
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39// Generic Mips Format 40class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 41 InstrItinClass itin, Format f>: Instruction 42{ 43 field bits<32> Inst; 44 Format Form = f; 45 46 let Namespace = "Mips"; 47 48 let Size = 4; 49 50 bits<6> Opcode = 0; 51 52 // Top 6 bits are the 'opcode' field 53 let Inst{31-26} = Opcode; 54 55 let OutOperandList = outs; 56 let InOperandList = ins; 57 58 let AsmString = asmstr; 59 let Pattern = pattern; 60 let Itinerary = itin; 61 62 // 63 // Attributes specific to Mips instructions... 64 // 65 bits<4> FormBits = Form.Value; 66 67 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 68 let TSFlags{3-0} = FormBits; 69 70 let DecoderNamespace = "Mips"; 71 72 field bits<32> SoftFail = 0; 73} 74 75// Mips32/64 Instruction Format 76class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 77 InstrItinClass itin, Format f>: 78 MipsInst<outs, ins, asmstr, pattern, itin, f> { 79 let Predicates = [HasStdEnc]; 80} 81 82// Mips Pseudo Instructions Format 83class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: 84 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> { 85 let isCodeGenOnly = 1; 86 let isPseudo = 1; 87} 88 89// Mips32/64 Pseudo Instruction Format 90class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>: 91 MipsPseudo<outs, ins, asmstr, pattern> { 92 let Predicates = [HasStdEnc]; 93} 94 95// Pseudo-instructions for alternate assembly syntax (never used by codegen). 96// These are aliases that require C++ handling to convert to the target 97// instruction, while InstAliases can be handled directly by tblgen. 98class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 99 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 100 let isPseudo = 1; 101 let Pattern = []; 102} 103//===----------------------------------------------------------------------===// 104// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 105//===----------------------------------------------------------------------===// 106 107class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 108 list<dag> pattern, InstrItinClass itin>: 109 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 110{ 111 bits<5> rd; 112 bits<5> rs; 113 bits<5> rt; 114 bits<5> shamt; 115 bits<6> funct; 116 117 let Opcode = op; 118 let funct = _funct; 119 120 let Inst{25-21} = rs; 121 let Inst{20-16} = rt; 122 let Inst{15-11} = rd; 123 let Inst{10-6} = shamt; 124 let Inst{5-0} = funct; 125} 126 127//===----------------------------------------------------------------------===// 128// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 129//===----------------------------------------------------------------------===// 130 131class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 132 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 133{ 134 bits<5> rt; 135 bits<5> rs; 136 bits<16> imm16; 137 138 let Opcode = op; 139 140 let Inst{25-21} = rs; 141 let Inst{20-16} = rt; 142 let Inst{15-0} = imm16; 143} 144 145class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 146 list<dag> pattern, InstrItinClass itin>: 147 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 148{ 149 bits<5> rs; 150 bits<5> rt; 151 bits<16> imm16; 152 153 let Opcode = op; 154 155 let Inst{25-21} = rs; 156 let Inst{20-16} = rt; 157 let Inst{15-0} = imm16; 158} 159 160//===----------------------------------------------------------------------===// 161// Format J instruction class in Mips : <|opcode|address|> 162//===----------------------------------------------------------------------===// 163 164class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 165 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ> 166{ 167 bits<26> addr; 168 169 let Opcode = op; 170 171 let Inst{25-0} = addr; 172} 173 174 //===----------------------------------------------------------------------===// 175// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 176//===----------------------------------------------------------------------===// 177class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>: 178 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR> 179{ 180 bits<5> mfmt; 181 bits<5> rt; 182 bits<5> rd; 183 bits<3> sel; 184 185 let Opcode = op; 186 let mfmt = _mfmt; 187 188 let Inst{25-21} = mfmt; 189 let Inst{20-16} = rt; 190 let Inst{15-11} = rd; 191 let Inst{10-3} = 0; 192 let Inst{2-0} = sel; 193} 194 195//===----------------------------------------------------------------------===// 196// 197// FLOATING POINT INSTRUCTION FORMATS 198// 199// opcode - operation code. 200// fs - src reg. 201// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 202// fd - dst reg, only used on 3 regs instr. 203// fmt - double or single precision. 204// funct - combined with opcode field give us an operation code. 205// 206//===----------------------------------------------------------------------===// 207 208//===----------------------------------------------------------------------===// 209// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 210//===----------------------------------------------------------------------===// 211 212class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 213 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 214{ 215 bits<5> ft; 216 bits<5> base; 217 bits<16> imm16; 218 219 let Opcode = op; 220 221 let Inst{25-21} = base; 222 let Inst{20-16} = ft; 223 let Inst{15-0} = imm16; 224} 225 226class ADDS_FM<bits<6> funct, bits<5> fmt> { 227 bits<5> fd; 228 bits<5> fs; 229 bits<5> ft; 230 231 bits<32> Inst; 232 233 let Inst{31-26} = 0x11; 234 let Inst{25-21} = fmt; 235 let Inst{20-16} = ft; 236 let Inst{15-11} = fs; 237 let Inst{10-6} = fd; 238 let Inst{5-0} = funct; 239} 240 241class ABSS_FM<bits<6> funct, bits<5> fmt> { 242 bits<5> fd; 243 bits<5> fs; 244 245 bits<32> Inst; 246 247 let Inst{31-26} = 0x11; 248 let Inst{25-21} = fmt; 249 let Inst{20-16} = 0; 250 let Inst{15-11} = fs; 251 let Inst{10-6} = fd; 252 let Inst{5-0} = funct; 253} 254 255class MFC1_FM<bits<5> funct> { 256 bits<5> rt; 257 bits<5> fs; 258 259 bits<32> Inst; 260 261 let Inst{31-26} = 0x11; 262 let Inst{25-21} = funct; 263 let Inst{20-16} = rt; 264 let Inst{15-11} = fs; 265 let Inst{10-0} = 0; 266} 267 268class LW_FM<bits<6> op> { 269 bits<5> rt; 270 bits<21> addr; 271 272 bits<32> Inst; 273 274 let Inst{31-26} = op; 275 let Inst{25-21} = addr{20-16}; 276 let Inst{20-16} = rt; 277 let Inst{15-0} = addr{15-0}; 278} 279 280class MADDS_FM<bits<3> funct, bits<3> fmt> { 281 bits<5> fd; 282 bits<5> fr; 283 bits<5> fs; 284 bits<5> ft; 285 286 bits<32> Inst; 287 288 let Inst{31-26} = 0x13; 289 let Inst{25-21} = fr; 290 let Inst{20-16} = ft; 291 let Inst{15-11} = fs; 292 let Inst{10-6} = fd; 293 let Inst{5-3} = funct; 294 let Inst{2-0} = fmt; 295} 296 297class LWXC1_FM<bits<6> funct> { 298 bits<5> fd; 299 bits<5> base; 300 bits<5> index; 301 302 bits<32> Inst; 303 304 let Inst{31-26} = 0x13; 305 let Inst{25-21} = base; 306 let Inst{20-16} = index; 307 let Inst{15-11} = 0; 308 let Inst{10-6} = fd; 309 let Inst{5-0} = funct; 310} 311 312class SWXC1_FM<bits<6> funct> { 313 bits<5> fs; 314 bits<5> base; 315 bits<5> index; 316 317 bits<32> Inst; 318 319 let Inst{31-26} = 0x13; 320 let Inst{25-21} = base; 321 let Inst{20-16} = index; 322 let Inst{15-11} = fs; 323 let Inst{10-6} = 0; 324 let Inst{5-0} = funct; 325} 326 327class BC1F_FM<bit nd, bit tf> { 328 bits<16> offset; 329 330 bits<32> Inst; 331 332 let Inst{31-26} = 0x11; 333 let Inst{25-21} = 0x8; 334 let Inst{20-18} = 0; // cc 335 let Inst{17} = nd; 336 let Inst{16} = tf; 337 let Inst{15-0} = offset; 338} 339 340class CEQS_FM<bits<5> fmt> { 341 bits<5> fs; 342 bits<5> ft; 343 bits<4> cond; 344 345 bits<32> Inst; 346 347 let Inst{31-26} = 0x11; 348 let Inst{25-21} = fmt; 349 let Inst{20-16} = ft; 350 let Inst{15-11} = fs; 351 let Inst{10-8} = 0; // cc 352 let Inst{7-4} = 0x3; 353 let Inst{3-0} = cond; 354} 355 356class CMov_I_F_FM<bits<6> funct, bits<5> fmt> { 357 bits<5> fd; 358 bits<5> fs; 359 bits<5> rt; 360 361 bits<32> Inst; 362 363 let Inst{31-26} = 0x11; 364 let Inst{25-21} = fmt; 365 let Inst{20-16} = rt; 366 let Inst{15-11} = fs; 367 let Inst{10-6} = fd; 368 let Inst{5-0} = funct; 369} 370 371class CMov_F_I_FM<bit tf> { 372 bits<5> rd; 373 bits<5> rs; 374 375 bits<32> Inst; 376 377 let Inst{31-26} = 0; 378 let Inst{25-21} = rs; 379 let Inst{20-18} = 0; // cc 380 let Inst{17} = 0; 381 let Inst{16} = tf; 382 let Inst{15-11} = rd; 383 let Inst{10-6} = 0; 384 let Inst{5-0} = 1; 385} 386 387class CMov_F_F_FM<bits<5> fmt, bit tf> { 388 bits<5> fd; 389 bits<5> fs; 390 391 bits<32> Inst; 392 393 let Inst{31-26} = 0x11; 394 let Inst{25-21} = fmt; 395 let Inst{20-18} = 0; // cc 396 let Inst{17} = 0; 397 let Inst{16} = tf; 398 let Inst{15-11} = fs; 399 let Inst{10-6} = fd; 400 let Inst{5-0} = 0x11; 401} 402