MipsInstrFormats.td revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39class MMRel;
40
41def Std2MicroMips : InstrMapping {
42  let FilterClass = "MMRel";
43  // Instructions with the same BaseOpcode and isNVStore values form a row.
44  let RowFields = ["BaseOpcode"];
45  // Instructions with the same predicate sense form a column.
46  let ColFields = ["Arch"];
47  // The key column is the unpredicated instructions.
48  let KeyCol = ["se"];
49  // Value columns are PredSense=true and PredSense=false
50  let ValueCols = [["se"], ["micromips"]];
51}
52
53class StdArch {
54  string Arch = "se";
55}
56
57// Generic Mips Format
58class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
59               InstrItinClass itin, Format f>: Instruction
60{
61  field bits<32> Inst;
62  Format Form = f;
63
64  let Namespace = "Mips";
65
66  let Size = 4;
67
68  bits<6> Opcode = 0;
69
70  // Top 6 bits are the 'opcode' field
71  let Inst{31-26} = Opcode;
72
73  let OutOperandList = outs;
74  let InOperandList  = ins;
75
76  let AsmString   = asmstr;
77  let Pattern     = pattern;
78  let Itinerary   = itin;
79
80  //
81  // Attributes specific to Mips instructions...
82  //
83  bits<4> FormBits = Form.Value;
84
85  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
86  let TSFlags{3-0}   = FormBits;
87
88  let DecoderNamespace = "Mips";
89
90  field bits<32> SoftFail = 0;
91}
92
93// Mips32/64 Instruction Format
94class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
95             InstrItinClass itin, Format f, string opstr = ""> :
96  MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
97  let EncodingPredicates = [HasStdEnc];
98  string BaseOpcode = opstr;
99  string Arch;
100}
101
102// Mips Pseudo Instructions Format
103class MipsPseudo<dag outs, dag ins, list<dag> pattern,
104                 InstrItinClass itin = IIPseudo> :
105  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
106  let isCodeGenOnly = 1;
107  let isPseudo = 1;
108}
109
110// Mips32/64 Pseudo Instruction Format
111class PseudoSE<dag outs, dag ins, list<dag> pattern,
112               InstrItinClass itin = IIPseudo> :
113  MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
114  let EncodingPredicates = [HasStdEnc];
115}
116
117// Pseudo-instructions for alternate assembly syntax (never used by codegen).
118// These are aliases that require C++ handling to convert to the target
119// instruction, while InstAliases can be handled directly by tblgen.
120class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
121  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
122  let isPseudo = 1;
123  let Pattern = [];
124}
125//===----------------------------------------------------------------------===//
126// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
127//===----------------------------------------------------------------------===//
128
129class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
130         list<dag> pattern, InstrItinClass itin>:
131  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
132{
133  bits<5>  rd;
134  bits<5>  rs;
135  bits<5>  rt;
136  bits<5>  shamt;
137  bits<6>  funct;
138
139  let Opcode = op;
140  let funct  = _funct;
141
142  let Inst{25-21} = rs;
143  let Inst{20-16} = rt;
144  let Inst{15-11} = rd;
145  let Inst{10-6}  = shamt;
146  let Inst{5-0}   = funct;
147}
148
149//===----------------------------------------------------------------------===//
150// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
151//===----------------------------------------------------------------------===//
152
153class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
154         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
155{
156  bits<5>  rt;
157  bits<5>  rs;
158  bits<16> imm16;
159
160  let Opcode = op;
161
162  let Inst{25-21} = rs;
163  let Inst{20-16} = rt;
164  let Inst{15-0}  = imm16;
165}
166
167class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
168                  list<dag> pattern, InstrItinClass itin>:
169  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
170{
171  bits<5>  rs;
172  bits<5>  rt;
173  bits<16> imm16;
174
175  let Opcode = op;
176
177  let Inst{25-21} = rs;
178  let Inst{20-16} = rt;
179  let Inst{15-0}  = imm16;
180}
181
182//===----------------------------------------------------------------------===//
183// Format J instruction class in Mips : <|opcode|address|>
184//===----------------------------------------------------------------------===//
185
186class FJ<bits<6> op> : StdArch
187{
188  bits<26> target;
189
190  bits<32> Inst;
191
192  let Inst{31-26} = op;
193  let Inst{25-0}  = target;
194}
195
196//===----------------------------------------------------------------------===//
197// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
198//===----------------------------------------------------------------------===//
199class MFC3OP_FM<bits<6> op, bits<5> mfmt>
200{
201  bits<5> rt;
202  bits<5> rd;
203  bits<3> sel;
204
205  bits<32> Inst;
206
207  let Inst{31-26} = op;
208  let Inst{25-21} = mfmt;
209  let Inst{20-16} = rt;
210  let Inst{15-11} = rd;
211  let Inst{10-3}  = 0;
212  let Inst{2-0}   = sel;
213}
214
215class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
216  bits<5> rd;
217  bits<5> rs;
218  bits<5> rt;
219
220  bits<32> Inst;
221
222  let Inst{31-26} = op;
223  let Inst{25-21} = rs;
224  let Inst{20-16} = rt;
225  let Inst{15-11} = rd;
226  let Inst{10-6}  = 0;
227  let Inst{5-0}   = funct;
228}
229
230class ADDI_FM<bits<6> op> : StdArch {
231  bits<5>  rs;
232  bits<5>  rt;
233  bits<16> imm16;
234
235  bits<32> Inst;
236
237  let Inst{31-26} = op;
238  let Inst{25-21} = rs;
239  let Inst{20-16} = rt;
240  let Inst{15-0}  = imm16;
241}
242
243class SRA_FM<bits<6> funct, bit rotate> : StdArch {
244  bits<5> rd;
245  bits<5> rt;
246  bits<5> shamt;
247
248  bits<32> Inst;
249
250  let Inst{31-26} = 0;
251  let Inst{25-22} = 0;
252  let Inst{21}    = rotate;
253  let Inst{20-16} = rt;
254  let Inst{15-11} = rd;
255  let Inst{10-6}  = shamt;
256  let Inst{5-0}   = funct;
257}
258
259class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
260  bits<5> rd;
261  bits<5> rt;
262  bits<5> rs;
263
264  bits<32> Inst;
265
266  let Inst{31-26} = 0;
267  let Inst{25-21} = rs;
268  let Inst{20-16} = rt;
269  let Inst{15-11} = rd;
270  let Inst{10-7}  = 0;
271  let Inst{6}     = rotate;
272  let Inst{5-0}   = funct;
273}
274
275class BEQ_FM<bits<6> op> : StdArch {
276  bits<5>  rs;
277  bits<5>  rt;
278  bits<16> offset;
279
280  bits<32> Inst;
281
282  let Inst{31-26} = op;
283  let Inst{25-21} = rs;
284  let Inst{20-16} = rt;
285  let Inst{15-0}  = offset;
286}
287
288class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
289  bits<5>  rs;
290  bits<16> offset;
291
292  bits<32> Inst;
293
294  let Inst{31-26} = op;
295  let Inst{25-21} = rs;
296  let Inst{20-16} = funct;
297  let Inst{15-0}  = offset;
298}
299
300class SLTI_FM<bits<6> op> : StdArch {
301  bits<5> rt;
302  bits<5> rs;
303  bits<16> imm16;
304
305  bits<32> Inst;
306
307  let Inst{31-26} = op;
308  let Inst{25-21} = rs;
309  let Inst{20-16} = rt;
310  let Inst{15-0}  = imm16;
311}
312
313class MFLO_FM<bits<6> funct> : StdArch {
314  bits<5> rd;
315
316  bits<32> Inst;
317
318  let Inst{31-26} = 0;
319  let Inst{25-16} = 0;
320  let Inst{15-11} = rd;
321  let Inst{10-6}  = 0;
322  let Inst{5-0}   = funct;
323}
324
325class MTLO_FM<bits<6> funct> : StdArch {
326  bits<5> rs;
327
328  bits<32> Inst;
329
330  let Inst{31-26} = 0;
331  let Inst{25-21} = rs;
332  let Inst{20-6}  = 0;
333  let Inst{5-0}   = funct;
334}
335
336class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
337  bits<5> rd;
338  bits<5> rt;
339
340  bits<32> Inst;
341
342  let Inst{31-26} = 0x1f;
343  let Inst{25-21} = 0;
344  let Inst{20-16} = rt;
345  let Inst{15-11} = rd;
346  let Inst{10-6}  = funct;
347  let Inst{5-0}   = funct2;
348}
349
350class CLO_FM<bits<6> funct> : StdArch {
351  bits<5> rd;
352  bits<5> rs;
353  bits<5> rt;
354
355  bits<32> Inst;
356
357  let Inst{31-26} = 0x1c;
358  let Inst{25-21} = rs;
359  let Inst{20-16} = rt;
360  let Inst{15-11} = rd;
361  let Inst{10-6}  = 0;
362  let Inst{5-0}   = funct;
363  let rt = rd;
364}
365
366class LUI_FM : StdArch {
367  bits<5> rt;
368  bits<16> imm16;
369
370  bits<32> Inst;
371
372  let Inst{31-26} = 0xf;
373  let Inst{25-21} = 0;
374  let Inst{20-16} = rt;
375  let Inst{15-0}  = imm16;
376}
377
378class JALR_FM {
379  bits<5> rd;
380  bits<5> rs;
381
382  bits<32> Inst;
383
384  let Inst{31-26} = 0;
385  let Inst{25-21} = rs;
386  let Inst{20-16} = 0;
387  let Inst{15-11} = rd;
388  let Inst{10-6}  = 0;
389  let Inst{5-0}   = 9;
390}
391
392class BGEZAL_FM<bits<5> funct> : StdArch {
393  bits<5>  rs;
394  bits<16> offset;
395
396  bits<32> Inst;
397
398  let Inst{31-26} = 1;
399  let Inst{25-21} = rs;
400  let Inst{20-16} = funct;
401  let Inst{15-0}  = offset;
402}
403
404class SYNC_FM : StdArch {
405  bits<5> stype;
406
407  bits<32> Inst;
408
409  let Inst{31-26} = 0;
410  let Inst{10-6}  = stype;
411  let Inst{5-0}   = 0xf;
412}
413
414class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
415  bits<5>  rs;
416  bits<5>  rt;
417
418  bits<32> Inst;
419
420  let Inst{31-26} = op;
421  let Inst{25-21} = rs;
422  let Inst{20-16} = rt;
423  let Inst{15-6}  = 0;
424  let Inst{5-0}   = funct;
425}
426
427class EXT_FM<bits<6> funct> : StdArch {
428  bits<5> rt;
429  bits<5> rs;
430  bits<5> pos;
431  bits<5> size;
432
433  bits<32> Inst;
434
435  let Inst{31-26} = 0x1f;
436  let Inst{25-21} = rs;
437  let Inst{20-16} = rt;
438  let Inst{15-11} = size;
439  let Inst{10-6}  = pos;
440  let Inst{5-0}   = funct;
441}
442
443class RDHWR_FM {
444  bits<5> rt;
445  bits<5> rd;
446
447  bits<32> Inst;
448
449  let Inst{31-26} = 0x1f;
450  let Inst{25-21} = 0;
451  let Inst{20-16} = rt;
452  let Inst{15-11} = rd;
453  let Inst{10-6}  = 0;
454  let Inst{5-0}   = 0x3b;
455}
456
457class TEQ_FM<bits<6> funct> : StdArch {
458  bits<5> rs;
459  bits<5> rt;
460  bits<10> code_;
461
462  bits<32> Inst;
463
464  let Inst{31-26} = 0;
465  let Inst{25-21} = rs;
466  let Inst{20-16} = rt;
467  let Inst{15-6}  = code_;
468  let Inst{5-0}   = funct;
469}
470
471class TEQI_FM<bits<5> funct> : StdArch {
472  bits<5> rs;
473  bits<16> imm16;
474
475  bits<32> Inst;
476
477  let Inst{31-26} = 1;
478  let Inst{25-21} = rs;
479  let Inst{20-16}   = funct;
480  let Inst{15-0}  = imm16;
481}
482
483class WAIT_FM : StdArch {
484  bits<32> Inst;
485
486  let Inst{31-26} = 0x10;
487  let Inst{25}    = 1;
488  let Inst{24-6}  = 0;
489  let Inst{5-0}   = 0x20;
490}
491
492class EXTS_FM<bits<6> funct> : StdArch {
493  bits<5> rt;
494  bits<5> rs;
495  bits<5> pos;
496  bits<5> lenm1;
497
498  bits<32> Inst;
499
500  let Inst{31-26} = 0x1c;
501  let Inst{25-21} = rs;
502  let Inst{20-16} = rt;
503  let Inst{15-11} = lenm1;
504  let Inst{10-6}  = pos;
505  let Inst{5-0}   = funct;
506}
507
508class MTMR_FM<bits<6> funct> : StdArch {
509  bits<5> rs;
510
511  bits<32> Inst;
512
513  let Inst{31-26} = 0x1c;
514  let Inst{25-21} = rs;
515  let Inst{20-6}  = 0;
516  let Inst{5-0}   = funct;
517}
518
519class POP_FM<bits<6> funct> : StdArch {
520  bits<5> rd;
521  bits<5> rs;
522
523  bits<32> Inst;
524
525  let Inst{31-26} = 0x1c;
526  let Inst{25-21} = rs;
527  let Inst{20-16} = 0;
528  let Inst{15-11} = rd;
529  let Inst{10-6}  = 0;
530  let Inst{5-0}   = funct;
531}
532
533class SEQ_FM<bits<6> funct> : StdArch {
534  bits<5> rd;
535  bits<5> rs;
536  bits<5> rt;
537
538  bits<32> Inst;
539
540  let Inst{31-26} = 0x1c;
541  let Inst{25-21} = rs;
542  let Inst{20-16} = rt;
543  let Inst{15-11} = rd;
544  let Inst{10-6}  = 0;
545  let Inst{5-0}   = funct;
546}
547
548class SEQI_FM<bits<6> funct> : StdArch {
549  bits<5> rs;
550  bits<5> rt;
551  bits<10> imm10;
552
553  bits<32> Inst;
554
555  let Inst{31-26} = 0x1c;
556  let Inst{25-21} = rs;
557  let Inst{20-16} = rt;
558  let Inst{15-6}  = imm10;
559  let Inst{5-0}   = funct;
560}
561
562//===----------------------------------------------------------------------===//
563//  System calls format <op|code_|funct>
564//===----------------------------------------------------------------------===//
565
566class SYS_FM<bits<6> funct> : StdArch
567{
568  bits<20> code_;
569  bits<32> Inst;
570  let Inst{31-26} = 0x0;
571  let Inst{25-6} = code_;
572  let Inst{5-0}  = funct;
573}
574
575//===----------------------------------------------------------------------===//
576//  Break instruction format <op|code_1|funct>
577//===----------------------------------------------------------------------===//
578
579class BRK_FM<bits<6> funct> : StdArch
580{
581  bits<10> code_1;
582  bits<10> code_2;
583  bits<32> Inst;
584  let Inst{31-26} = 0x0;
585  let Inst{25-16} = code_1;
586  let Inst{15-6}  = code_2;
587  let Inst{5-0}   = funct;
588}
589
590//===----------------------------------------------------------------------===//
591//  Exception return format <Cop0|1|0|funct>
592//===----------------------------------------------------------------------===//
593
594class ER_FM<bits<6> funct> : StdArch
595{
596  bits<32> Inst;
597  let Inst{31-26} = 0x10;
598  let Inst{25}    = 1;
599  let Inst{24-6}  = 0;
600  let Inst{5-0}   = funct;
601}
602
603
604//===----------------------------------------------------------------------===//
605//  Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
606//===----------------------------------------------------------------------===//
607
608class EI_FM<bits<1> sc> : StdArch
609{
610  bits<32> Inst;
611  bits<5> rt;
612  let Inst{31-26} = 0x10;
613  let Inst{25-21} = 0xb;
614  let Inst{20-16} = rt;
615  let Inst{15-11} = 0xc;
616  let Inst{10-6}  = 0;
617  let Inst{5}     = sc;
618  let Inst{4-0}   = 0;
619}
620
621//===----------------------------------------------------------------------===//
622//
623//  FLOATING POINT INSTRUCTION FORMATS
624//
625//  opcode  - operation code.
626//  fs      - src reg.
627//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
628//  fd      - dst reg, only used on 3 regs instr.
629//  fmt     - double or single precision.
630//  funct   - combined with opcode field give us an operation code.
631//
632//===----------------------------------------------------------------------===//
633
634//===----------------------------------------------------------------------===//
635// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
636//===----------------------------------------------------------------------===//
637
638class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
639  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
640{
641  bits<5>  ft;
642  bits<5>  base;
643  bits<16> imm16;
644
645  let Opcode = op;
646
647  let Inst{25-21} = base;
648  let Inst{20-16} = ft;
649  let Inst{15-0}  = imm16;
650}
651
652class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
653  bits<5> fd;
654  bits<5> fs;
655  bits<5> ft;
656
657  bits<32> Inst;
658
659  let Inst{31-26} = 0x11;
660  let Inst{25-21} = fmt;
661  let Inst{20-16} = ft;
662  let Inst{15-11} = fs;
663  let Inst{10-6}  = fd;
664  let Inst{5-0}   = funct;
665}
666
667class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
668  bits<5> fd;
669  bits<5> fs;
670
671  bits<32> Inst;
672
673  let Inst{31-26} = 0x11;
674  let Inst{25-21} = fmt;
675  let Inst{20-16} = 0;
676  let Inst{15-11} = fs;
677  let Inst{10-6}  = fd;
678  let Inst{5-0}   = funct;
679}
680
681class MFC1_FM<bits<5> funct> : StdArch {
682  bits<5> rt;
683  bits<5> fs;
684
685  bits<32> Inst;
686
687  let Inst{31-26} = 0x11;
688  let Inst{25-21} = funct;
689  let Inst{20-16} = rt;
690  let Inst{15-11} = fs;
691  let Inst{10-0}  = 0;
692}
693
694class LW_FM<bits<6> op> : StdArch {
695  bits<5> rt;
696  bits<21> addr;
697
698  bits<32> Inst;
699
700  let Inst{31-26} = op;
701  let Inst{25-21} = addr{20-16};
702  let Inst{20-16} = rt;
703  let Inst{15-0}  = addr{15-0};
704}
705
706class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
707  bits<5> fd;
708  bits<5> fr;
709  bits<5> fs;
710  bits<5> ft;
711
712  bits<32> Inst;
713
714  let Inst{31-26} = 0x13;
715  let Inst{25-21} = fr;
716  let Inst{20-16} = ft;
717  let Inst{15-11} = fs;
718  let Inst{10-6}  = fd;
719  let Inst{5-3}   = funct;
720  let Inst{2-0}   = fmt;
721}
722
723class LWXC1_FM<bits<6> funct> : StdArch {
724  bits<5> fd;
725  bits<5> base;
726  bits<5> index;
727
728  bits<32> Inst;
729
730  let Inst{31-26} = 0x13;
731  let Inst{25-21} = base;
732  let Inst{20-16} = index;
733  let Inst{15-11} = 0;
734  let Inst{10-6}  = fd;
735  let Inst{5-0}   = funct;
736}
737
738class SWXC1_FM<bits<6> funct> : StdArch {
739  bits<5> fs;
740  bits<5> base;
741  bits<5> index;
742
743  bits<32> Inst;
744
745  let Inst{31-26} = 0x13;
746  let Inst{25-21} = base;
747  let Inst{20-16} = index;
748  let Inst{15-11} = fs;
749  let Inst{10-6}  = 0;
750  let Inst{5-0}   = funct;
751}
752
753class BC1F_FM<bit nd, bit tf> : StdArch {
754  bits<3>  fcc;
755  bits<16> offset;
756
757  bits<32> Inst;
758
759  let Inst{31-26} = 0x11;
760  let Inst{25-21} = 0x8;
761  let Inst{20-18} = fcc;
762  let Inst{17} = nd;
763  let Inst{16} = tf;
764  let Inst{15-0} = offset;
765}
766
767class CEQS_FM<bits<5> fmt> : StdArch {
768  bits<5> fs;
769  bits<5> ft;
770  bits<4> cond;
771
772  bits<32> Inst;
773
774  let Inst{31-26} = 0x11;
775  let Inst{25-21} = fmt;
776  let Inst{20-16} = ft;
777  let Inst{15-11} = fs;
778  let Inst{10-8} = 0; // cc
779  let Inst{7-4} = 0x3;
780  let Inst{3-0} = cond;
781}
782
783class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
784  let cond = c;
785}
786
787class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
788  bits<5> fd;
789  bits<5> fs;
790  bits<5> rt;
791
792  bits<32> Inst;
793
794  let Inst{31-26} = 0x11;
795  let Inst{25-21} = fmt;
796  let Inst{20-16} = rt;
797  let Inst{15-11} = fs;
798  let Inst{10-6} = fd;
799  let Inst{5-0} = funct;
800}
801
802class CMov_F_I_FM<bit tf> : StdArch {
803  bits<5> rd;
804  bits<5> rs;
805  bits<3> fcc;
806
807  bits<32> Inst;
808
809  let Inst{31-26} = 0;
810  let Inst{25-21} = rs;
811  let Inst{20-18} = fcc;
812  let Inst{17} = 0;
813  let Inst{16} = tf;
814  let Inst{15-11} = rd;
815  let Inst{10-6} = 0;
816  let Inst{5-0} = 1;
817}
818
819class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
820  bits<5> fd;
821  bits<5> fs;
822  bits<3> fcc;
823
824  bits<32> Inst;
825
826  let Inst{31-26} = 0x11;
827  let Inst{25-21} = fmt;
828  let Inst{20-18} = fcc;
829  let Inst{17} = 0;
830  let Inst{16} = tf;
831  let Inst{15-11} = fs;
832  let Inst{10-6} = fd;
833  let Inst{5-0} = 0x11;
834}
835
836class BARRIER_FM<bits<5> op> : StdArch {
837  bits<32> Inst;
838
839  let Inst{31-26} = 0; // SPECIAL
840  let Inst{25-21} = 0;
841  let Inst{20-16} = 0; // rt = 0
842  let Inst{15-11} = 0; // rd = 0
843  let Inst{10-6} = op; // Operation
844  let Inst{5-0} = 0;   // SLL
845}
846
847class SDBBP_FM : StdArch {
848  bits<20> code_;
849
850  bits<32> Inst;
851
852  let Inst{31-26} = 0b011100; // SPECIAL2
853  let Inst{25-6} = code_;
854  let Inst{5-0} = 0b111111;   // SDBBP
855}
856
857class JR_HB_FM<bits<6> op> : StdArch{
858  bits<5> rs;
859
860  bits<32> Inst;
861
862  let Inst{31-26} = 0; // SPECIAL
863  let Inst{25-21} = rs;
864  let Inst{20-11} = 0;
865  let Inst{10} = 1;
866  let Inst{9-6} = 0;
867  let Inst{5-0} = op;
868}
869
870class JALR_HB_FM<bits<6> op> : StdArch {
871  bits<5> rd;
872  bits<5> rs;
873
874  bits<32> Inst;
875
876  let Inst{31-26} = 0; // SPECIAL
877  let Inst{25-21} = rs;
878  let Inst{20-16} = 0;
879  let Inst{15-11} = rd;
880  let Inst{10} = 1;
881  let Inst{9-6} = 0;
882  let Inst{5-0} = op;
883}
884
885class COP0_TLB_FM<bits<6> op> : StdArch {
886  bits<32> Inst;
887
888  let Inst{31-26} = 0x10; // COP0
889  let Inst{25} = 1;       // CO
890  let Inst{24-6} = 0;
891  let Inst{5-0} = op;     // Operation
892}
893
894class CACHEOP_FM<bits<6> op> : StdArch {
895  bits<21> addr;
896  bits<5> hint;
897  bits<5> base = addr{20-16};
898  bits<16> offset = addr{15-0};
899
900  bits<32> Inst;
901
902  let Inst{31-26} = op;
903  let Inst{25-21} = base;
904  let Inst{20-16} = hint;
905  let Inst{15-0}  = offset;
906}
907