MipsInstrFormats.td revision dbf51ee4596791d8cf38538b80805b2c3a577836 
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39// Generic Mips Format
40class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41               InstrItinClass itin, Format f>: Instruction
42{
43  field bits<32> Inst;
44  Format Form = f;
45
46  let Namespace = "Mips";
47
48  let Size = 4;
49
50  bits<6> Opcode = 0;
51
52  // Top 6 bits are the 'opcode' field
53  let Inst{31-26} = Opcode;
54
55  let OutOperandList = outs;
56  let InOperandList  = ins;
57
58  let AsmString   = asmstr;
59  let Pattern     = pattern;
60  let Itinerary   = itin;
61
62  //
63  // Attributes specific to Mips instructions...
64  //
65  bits<4> FormBits = Form.Value;
66
67  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68  let TSFlags{3-0}   = FormBits;
69
70  let DecoderNamespace = "Mips";
71
72  field bits<32> SoftFail = 0;
73}
74
75// Mips32/64 Instruction Format
76class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77             InstrItinClass itin, Format f>:
78  MipsInst<outs, ins, asmstr, pattern, itin, f> {
79  let Predicates = [HasStdEnc];
80}
81
82// Mips Pseudo Instructions Format
83class MipsPseudo<dag outs, dag ins, list<dag> pattern,
84                 InstrItinClass itin = IIPseudo> :
85  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
86  let isCodeGenOnly = 1;
87  let isPseudo = 1;
88}
89
90// Mips32/64 Pseudo Instruction Format
91class PseudoSE<dag outs, dag ins, list<dag> pattern,
92               InstrItinClass itin = IIPseudo>:
93  MipsPseudo<outs, ins, pattern, itin> {
94  let Predicates = [HasStdEnc];
95}
96
97// Pseudo-instructions for alternate assembly syntax (never used by codegen).
98// These are aliases that require C++ handling to convert to the target
99// instruction, while InstAliases can be handled directly by tblgen.
100class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
101  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
102  let isPseudo = 1;
103  let Pattern = [];
104}
105//===----------------------------------------------------------------------===//
106// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
107//===----------------------------------------------------------------------===//
108
109class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
110         list<dag> pattern, InstrItinClass itin>:
111  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
112{
113  bits<5>  rd;
114  bits<5>  rs;
115  bits<5>  rt;
116  bits<5>  shamt;
117  bits<6>  funct;
118
119  let Opcode = op;
120  let funct  = _funct;
121
122  let Inst{25-21} = rs;
123  let Inst{20-16} = rt;
124  let Inst{15-11} = rd;
125  let Inst{10-6}  = shamt;
126  let Inst{5-0}   = funct;
127}
128
129//===----------------------------------------------------------------------===//
130// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
131//===----------------------------------------------------------------------===//
132
133class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
134         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
135{
136  bits<5>  rt;
137  bits<5>  rs;
138  bits<16> imm16;
139
140  let Opcode = op;
141
142  let Inst{25-21} = rs;
143  let Inst{20-16} = rt;
144  let Inst{15-0}  = imm16;
145}
146
147class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
148                  list<dag> pattern, InstrItinClass itin>:
149  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
150{
151  bits<5>  rs;
152  bits<5>  rt;
153  bits<16> imm16;
154
155  let Opcode = op;
156
157  let Inst{25-21} = rs;
158  let Inst{20-16} = rt;
159  let Inst{15-0}  = imm16;
160}
161
162//===----------------------------------------------------------------------===//
163// Format J instruction class in Mips : <|opcode|address|>
164//===----------------------------------------------------------------------===//
165
166class FJ<bits<6> op>
167{
168  bits<26> target;
169
170  bits<32> Inst;
171
172  let Inst{31-26} = op;
173  let Inst{25-0}  = target;
174}
175
176 //===----------------------------------------------------------------------===//
177// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
178//===----------------------------------------------------------------------===//
179class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
180  InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>
181{
182  bits<5> mfmt;
183  bits<5> rt;
184  bits<5> rd;
185  bits<3> sel;
186
187  let Opcode = op;
188  let mfmt = _mfmt;
189
190  let Inst{25-21} = mfmt;
191  let Inst{20-16} = rt;
192  let Inst{15-11} = rd;
193  let Inst{10-3}  = 0;
194  let Inst{2-0}   = sel;
195}
196
197class ADD_FM<bits<6> op, bits<6> funct> {
198  bits<5> rd;
199  bits<5> rs;
200  bits<5> rt;
201
202  bits<32> Inst;
203
204  let Inst{31-26} = op;
205  let Inst{25-21} = rs;
206  let Inst{20-16} = rt;
207  let Inst{15-11} = rd;
208  let Inst{10-6}  = 0;
209  let Inst{5-0}   = funct;
210}
211
212class ADDI_FM<bits<6> op> {
213  bits<5>  rs;
214  bits<5>  rt;
215  bits<16> imm16;
216
217  bits<32> Inst;
218
219  let Inst{31-26} = op;
220  let Inst{25-21} = rs;
221  let Inst{20-16} = rt;
222  let Inst{15-0}  = imm16;
223}
224
225class SRA_FM<bits<6> funct, bit rotate> {
226  bits<5> rd;
227  bits<5> rt;
228  bits<5> shamt;
229
230  bits<32> Inst;
231
232  let Inst{31-26} = 0;
233  let Inst{25-22} = 0;
234  let Inst{21}    = rotate;
235  let Inst{20-16} = rt;
236  let Inst{15-11} = rd;
237  let Inst{10-6}  = shamt;
238  let Inst{5-0}   = funct;
239}
240
241class SRLV_FM<bits<6> funct, bit rotate> {
242  bits<5> rd;
243  bits<5> rt;
244  bits<5> rs;
245
246  bits<32> Inst;
247
248  let Inst{31-26} = 0;
249  let Inst{25-21} = rs;
250  let Inst{20-16} = rt;
251  let Inst{15-11} = rd;
252  let Inst{10-7}  = 0;
253  let Inst{6}     = rotate;
254  let Inst{5-0}   = funct;
255}
256
257class BEQ_FM<bits<6> op> {
258  bits<5>  rs;
259  bits<5>  rt;
260  bits<16> offset;
261
262  bits<32> Inst;
263
264  let Inst{31-26} = op;
265  let Inst{25-21} = rs;
266  let Inst{20-16} = rt;
267  let Inst{15-0}  = offset;
268}
269
270class BGEZ_FM<bits<6> op, bits<5> funct> {
271  bits<5>  rs;
272  bits<16> offset;
273
274  bits<32> Inst;
275
276  let Inst{31-26} = op;
277  let Inst{25-21} = rs;
278  let Inst{20-16} = funct;
279  let Inst{15-0}  = offset;
280}
281
282class B_FM {
283  bits<16> offset;
284
285  bits<32> Inst;
286
287  let Inst{31-26} = 4;
288  let Inst{25-21} = 0;
289  let Inst{20-16} = 0;
290  let Inst{15-0}  = offset;
291}
292
293class SLTI_FM<bits<6> op> {
294  bits<5> rt;
295  bits<5> rs;
296  bits<16> imm16;
297
298  bits<32> Inst;
299
300  let Inst{31-26} = op;
301  let Inst{25-21} = rs;
302  let Inst{20-16} = rt;
303  let Inst{15-0}  = imm16;
304}
305
306class MFLO_FM<bits<6> funct> {
307  bits<5> rd;
308
309  bits<32> Inst;
310
311  let Inst{31-26} = 0;
312  let Inst{25-16} = 0;
313  let Inst{15-11} = rd;
314  let Inst{10-6}  = 0;
315  let Inst{5-0}   = funct;
316}
317
318class MTLO_FM<bits<6> funct> {
319  bits<5> rs;
320
321  bits<32> Inst;
322
323  let Inst{31-26} = 0;
324  let Inst{25-21} = rs;
325  let Inst{20-6}  = 0;
326  let Inst{5-0}   = funct;
327}
328
329class SEB_FM<bits<5> funct, bits<6> funct2> {
330  bits<5> rd;
331  bits<5> rt;
332
333  bits<32> Inst;
334
335  let Inst{31-26} = 0x1f;
336  let Inst{25-21} = 0;
337  let Inst{20-16} = rt;
338  let Inst{15-11} = rd;
339  let Inst{10-6}  = funct;
340  let Inst{5-0}   = funct2;
341}
342
343class CLO_FM<bits<6> funct> {
344  bits<5> rd;
345  bits<5> rs;
346  bits<5> rt;
347
348  bits<32> Inst;
349
350  let Inst{31-26} = 0x1c;
351  let Inst{25-21} = rs;
352  let Inst{20-16} = rt;
353  let Inst{15-11} = rd;
354  let Inst{10-6}  = 0;
355  let Inst{5-0}   = funct;
356  let rt = rd;
357}
358
359class LUI_FM {
360  bits<5> rt;
361  bits<16> imm16;
362
363  bits<32> Inst;
364
365  let Inst{31-26} = 0xf;
366  let Inst{25-21} = 0;
367  let Inst{20-16} = rt;
368  let Inst{15-0}  = imm16;
369}
370
371class NOP_FM {
372  bits<32> Inst;
373
374  let Inst{31-0} = 0;
375}
376
377class JALR_FM {
378  bits<5> rs;
379
380  bits<32> Inst;
381
382  let Inst{31-26} = 0;
383  let Inst{25-21} = rs;
384  let Inst{20-16} = 0;
385  let Inst{15-11} = 31;
386  let Inst{10-6}  = 0;
387  let Inst{5-0}   = 9;
388}
389
390class BAL_FM {
391  bits<16> offset;
392
393  bits<32> Inst;
394
395  let Inst{31-26} = 1;
396  let Inst{25-21} = 0;
397  let Inst{20-16} = 0x11;
398  let Inst{15-0}  = offset;
399}
400
401class BGEZAL_FM<bits<5> funct> {
402  bits<5>  rs;
403  bits<16> offset;
404
405  bits<32> Inst;
406
407  let Inst{31-26} = 1;
408  let Inst{25-21} = rs;
409  let Inst{20-16} = funct;
410  let Inst{15-0}  = offset;
411}
412
413class SYNC_FM {
414  bits<5> stype;
415
416  bits<32> Inst;
417
418  let Inst{31-26} = 0;
419  let Inst{10-6}  = stype;
420  let Inst{5-0}   = 0xf;
421}
422
423class MULT_FM<bits<6> op, bits<6> funct> {
424  bits<5>  rs;
425  bits<5>  rt;
426
427  bits<32> Inst;
428
429  let Inst{31-26} = op;
430  let Inst{25-21} = rs;
431  let Inst{20-16} = rt;
432  let Inst{15-6}  = 0;
433  let Inst{5-0}   = funct;
434}
435
436class EXT_FM<bits<6> funct> {
437  bits<5> rt;
438  bits<5> rs;
439  bits<5> pos;
440  bits<5> size;
441
442  bits<32> Inst;
443
444  let Inst{31-26} = 0x1f;
445  let Inst{25-21} = rs;
446  let Inst{20-16} = rt;
447  let Inst{15-11} = size;
448  let Inst{10-6}  = pos;
449  let Inst{5-0}   = funct;
450}
451
452class RDHWR_FM {
453  bits<5> rt;
454  bits<5> rd;
455
456  bits<32> Inst;
457
458  let Inst{31-26} = 0x1f;
459  let Inst{25-21} = 0;
460  let Inst{20-16} = rt;
461  let Inst{15-11} = rd;
462  let Inst{10-6}  = 0;
463  let Inst{5-0}   = 0x3b;
464}
465
466//===----------------------------------------------------------------------===//
467//
468//  FLOATING POINT INSTRUCTION FORMATS
469//
470//  opcode  - operation code.
471//  fs      - src reg.
472//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
473//  fd      - dst reg, only used on 3 regs instr.
474//  fmt     - double or single precision.
475//  funct   - combined with opcode field give us an operation code.
476//
477//===----------------------------------------------------------------------===//
478
479//===----------------------------------------------------------------------===//
480// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
481//===----------------------------------------------------------------------===//
482
483class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
484  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
485{
486  bits<5>  ft;
487  bits<5>  base;
488  bits<16> imm16;
489
490  let Opcode = op;
491
492  let Inst{25-21} = base;
493  let Inst{20-16} = ft;
494  let Inst{15-0}  = imm16;
495}
496
497class ADDS_FM<bits<6> funct, bits<5> fmt> {
498  bits<5> fd;
499  bits<5> fs;
500  bits<5> ft;
501
502  bits<32> Inst;
503
504  let Inst{31-26} = 0x11;
505  let Inst{25-21} = fmt;
506  let Inst{20-16} = ft;
507  let Inst{15-11} = fs;
508  let Inst{10-6}  = fd;
509  let Inst{5-0}   = funct;
510}
511
512class ABSS_FM<bits<6> funct, bits<5> fmt> {
513  bits<5> fd;
514  bits<5> fs;
515
516  bits<32> Inst;
517
518  let Inst{31-26} = 0x11;
519  let Inst{25-21} = fmt;
520  let Inst{20-16} = 0;
521  let Inst{15-11} = fs;
522  let Inst{10-6}  = fd;
523  let Inst{5-0}   = funct;
524}
525
526class MFC1_FM<bits<5> funct> {
527  bits<5> rt;
528  bits<5> fs;
529
530  bits<32> Inst;
531
532  let Inst{31-26} = 0x11;
533  let Inst{25-21} = funct;
534  let Inst{20-16} = rt;
535  let Inst{15-11} = fs;
536  let Inst{10-0}  = 0;
537}
538
539class LW_FM<bits<6> op> {
540  bits<5> rt;
541  bits<21> addr;
542
543  bits<32> Inst;
544
545  let Inst{31-26} = op;
546  let Inst{25-21} = addr{20-16};
547  let Inst{20-16} = rt;
548  let Inst{15-0}  = addr{15-0};
549}
550
551class MADDS_FM<bits<3> funct, bits<3> fmt> {
552  bits<5> fd;
553  bits<5> fr;
554  bits<5> fs;
555  bits<5> ft;
556
557  bits<32> Inst;
558
559  let Inst{31-26} = 0x13;
560  let Inst{25-21} = fr;
561  let Inst{20-16} = ft;
562  let Inst{15-11} = fs;
563  let Inst{10-6}  = fd;
564  let Inst{5-3}   = funct;
565  let Inst{2-0}   = fmt;
566}
567
568class LWXC1_FM<bits<6> funct> {
569  bits<5> fd;
570  bits<5> base;
571  bits<5> index;
572
573  bits<32> Inst;
574
575  let Inst{31-26} = 0x13;
576  let Inst{25-21} = base;
577  let Inst{20-16} = index;
578  let Inst{15-11} = 0;
579  let Inst{10-6}  = fd;
580  let Inst{5-0}   = funct;
581}
582
583class SWXC1_FM<bits<6> funct> {
584  bits<5> fs;
585  bits<5> base;
586  bits<5> index;
587
588  bits<32> Inst;
589
590  let Inst{31-26} = 0x13;
591  let Inst{25-21} = base;
592  let Inst{20-16} = index;
593  let Inst{15-11} = fs;
594  let Inst{10-6}  = 0;
595  let Inst{5-0}   = funct;
596}
597
598class BC1F_FM<bit nd, bit tf> {
599  bits<16> offset;
600
601  bits<32> Inst;
602
603  let Inst{31-26} = 0x11;
604  let Inst{25-21} = 0x8;
605  let Inst{20-18} = 0; // cc
606  let Inst{17} = nd;
607  let Inst{16} = tf;
608  let Inst{15-0} = offset;
609}
610
611class CEQS_FM<bits<5> fmt> {
612  bits<5> fs;
613  bits<5> ft;
614  bits<4> cond;
615
616  bits<32> Inst;
617
618  let Inst{31-26} = 0x11;
619  let Inst{25-21} = fmt;
620  let Inst{20-16} = ft;
621  let Inst{15-11} = fs;
622  let Inst{10-8} = 0; // cc
623  let Inst{7-4} = 0x3;
624  let Inst{3-0} = cond;
625}
626
627class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
628  bits<5> fd;
629  bits<5> fs;
630  bits<5> rt;
631
632  bits<32> Inst;
633
634  let Inst{31-26} = 0x11;
635  let Inst{25-21} = fmt;
636  let Inst{20-16} = rt;
637  let Inst{15-11} = fs;
638  let Inst{10-6} = fd;
639  let Inst{5-0} = funct;
640}
641
642class CMov_F_I_FM<bit tf> {
643  bits<5> rd;
644  bits<5> rs;
645
646  bits<32> Inst;
647
648  let Inst{31-26} = 0;
649  let Inst{25-21} = rs;
650  let Inst{20-18} = 0; // cc
651  let Inst{17} = 0;
652  let Inst{16} = tf;
653  let Inst{15-11} = rd;
654  let Inst{10-6} = 0;
655  let Inst{5-0} = 1;
656}
657
658class CMov_F_F_FM<bits<5> fmt, bit tf> {
659  bits<5> fd;
660  bits<5> fs;
661
662  bits<32> Inst;
663
664  let Inst{31-26} = 0x11;
665  let Inst{25-21} = fmt;
666  let Inst{20-18} = 0; // cc
667  let Inst{17} = 0;
668  let Inst{16} = tf;
669  let Inst{15-11} = fs;
670  let Inst{10-6} = fd;
671  let Inst{5-0} = 0x11;
672}
673