MipsInstrInfo.cpp revision 0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 
1//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsInstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/TargetRegistry.h"
24
25#define GET_INSTRINFO_CTOR
26#include "MipsGenInstrInfo.inc"
27
28using namespace llvm;
29
30MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
31  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32    TM(tm), UncondBrOpc(UncondBr) {}
33
34const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) {
35  if (TM.getSubtargetImpl()->inMips16Mode())
36    return llvm::createMips16InstrInfo(TM);
37
38  return llvm::createMipsSEInstrInfo(TM);
39}
40
41bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
42  return op.isImm() && op.getImm() == 0;
43}
44
45/// insertNoop - If data hazard condition is found insert the target nop
46/// instruction.
47void MipsInstrInfo::
48insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
49{
50  DebugLoc DL;
51  BuildMI(MBB, MI, DL, get(Mips::NOP));
52}
53
54MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
55                                                unsigned Flag) const {
56  MachineFunction &MF = *MBB.getParent();
57  MachineFrameInfo &MFI = *MF.getFrameInfo();
58  unsigned Align = MFI.getObjectAlignment(FI);
59
60  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
61                                 MFI.getObjectSize(FI), Align);
62}
63
64//===----------------------------------------------------------------------===//
65// Branch Analysis
66//===----------------------------------------------------------------------===//
67
68void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
69                                  MachineBasicBlock *&BB,
70                                  SmallVectorImpl<MachineOperand> &Cond) const {
71  assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
72  int NumOp = Inst->getNumExplicitOperands();
73
74  // for both int and fp branches, the last explicit operand is the
75  // MBB.
76  BB = Inst->getOperand(NumOp-1).getMBB();
77  Cond.push_back(MachineOperand::CreateImm(Opc));
78
79  for (int i=0; i<NumOp-1; i++)
80    Cond.push_back(Inst->getOperand(i));
81}
82
83bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
84                                  MachineBasicBlock *&TBB,
85                                  MachineBasicBlock *&FBB,
86                                  SmallVectorImpl<MachineOperand> &Cond,
87                                  bool AllowModify) const {
88  SmallVector<MachineInstr*, 2> BranchInstrs;
89  BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
90
91  return (BT == BT_None) || (BT == BT_Indirect);
92}
93
94void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
95                                MachineBasicBlock *TBB, DebugLoc DL,
96                                const SmallVectorImpl<MachineOperand>& Cond)
97  const {
98  unsigned Opc = Cond[0].getImm();
99  const MCInstrDesc &MCID = get(Opc);
100  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
101
102  for (unsigned i = 1; i < Cond.size(); ++i) {
103    if (Cond[i].isReg())
104      MIB.addReg(Cond[i].getReg());
105    else if (Cond[i].isImm())
106      MIB.addImm(Cond[i].getImm());
107    else
108       assert(true && "Cannot copy operand");
109  }
110  MIB.addMBB(TBB);
111}
112
113unsigned MipsInstrInfo::
114InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
115             MachineBasicBlock *FBB,
116             const SmallVectorImpl<MachineOperand> &Cond,
117             DebugLoc DL) const {
118  // Shouldn't be a fall through.
119  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
120
121  // # of condition operands:
122  //  Unconditional branches: 0
123  //  Floating point branches: 1 (opc)
124  //  Int BranchZero: 2 (opc, reg)
125  //  Int Branch: 3 (opc, reg0, reg1)
126  assert((Cond.size() <= 3) &&
127         "# of Mips branch conditions must be <= 3!");
128
129  // Two-way Conditional branch.
130  if (FBB) {
131    BuildCondBr(MBB, TBB, DL, Cond);
132    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
133    return 2;
134  }
135
136  // One way branch.
137  // Unconditional branch.
138  if (Cond.empty())
139    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
140  else // Conditional branch.
141    BuildCondBr(MBB, TBB, DL, Cond);
142  return 1;
143}
144
145unsigned MipsInstrInfo::
146RemoveBranch(MachineBasicBlock &MBB) const
147{
148  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
149  MachineBasicBlock::reverse_iterator FirstBr;
150  unsigned removed;
151
152  // Skip all the debug instructions.
153  while (I != REnd && I->isDebugValue())
154    ++I;
155
156  FirstBr = I;
157
158  // Up to 2 branches are removed.
159  // Note that indirect branches are not removed.
160  for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
161    if (!getAnalyzableBrOpc(I->getOpcode()))
162      break;
163
164  MBB.erase(I.base(), FirstBr.base());
165
166  return removed;
167}
168
169/// ReverseBranchCondition - Return the inverse opcode of the
170/// specified Branch instruction.
171bool MipsInstrInfo::
172ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
173{
174  assert( (Cond.size() && Cond.size() <= 3) &&
175          "Invalid Mips branch condition!");
176  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
177  return false;
178}
179
180MipsInstrInfo::BranchType MipsInstrInfo::
181AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
182              MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond,
183              bool AllowModify,
184              SmallVectorImpl<MachineInstr*> &BranchInstrs) const {
185
186  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
187
188  // Skip all the debug instructions.
189  while (I != REnd && I->isDebugValue())
190    ++I;
191
192  if (I == REnd || !isUnpredicatedTerminator(&*I)) {
193    // This block ends with no branches (it just falls through to its succ).
194    // Leave TBB/FBB null.
195    TBB = FBB = NULL;
196    return BT_NoBranch;
197  }
198
199  MachineInstr *LastInst = &*I;
200  unsigned LastOpc = LastInst->getOpcode();
201  BranchInstrs.push_back(LastInst);
202
203  // Not an analyzable branch (e.g., indirect jump).
204  if (!getAnalyzableBrOpc(LastOpc))
205    return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
206
207  // Get the second to last instruction in the block.
208  unsigned SecondLastOpc = 0;
209  MachineInstr *SecondLastInst = NULL;
210
211  if (++I != REnd) {
212    SecondLastInst = &*I;
213    SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
214
215    // Not an analyzable branch (must be an indirect jump).
216    if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
217      return BT_None;
218  }
219
220  // If there is only one terminator instruction, process it.
221  if (!SecondLastOpc) {
222    // Unconditional branch
223    if (LastOpc == UncondBrOpc) {
224      TBB = LastInst->getOperand(0).getMBB();
225      return BT_Uncond;
226    }
227
228    // Conditional branch
229    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
230    return BT_Cond;
231  }
232
233  // If we reached here, there are two branches.
234  // If there are three terminators, we don't know what sort of block this is.
235  if (++I != REnd && isUnpredicatedTerminator(&*I))
236    return BT_None;
237
238  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
239
240  // If second to last instruction is an unconditional branch,
241  // analyze it and remove the last instruction.
242  if (SecondLastOpc == UncondBrOpc) {
243    // Return if the last instruction cannot be removed.
244    if (!AllowModify)
245      return BT_None;
246
247    TBB = SecondLastInst->getOperand(0).getMBB();
248    LastInst->eraseFromParent();
249    BranchInstrs.pop_back();
250    return BT_Uncond;
251  }
252
253  // Conditional branch followed by an unconditional branch.
254  // The last one must be unconditional.
255  if (LastOpc != UncondBrOpc)
256    return BT_None;
257
258  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
259  FBB = LastInst->getOperand(0).getMBB();
260
261  return BT_CondUncond;
262}
263
264/// Return the number of bytes of code the specified instruction may be.
265unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
266  switch (MI->getOpcode()) {
267  default:
268    return MI->getDesc().getSize();
269  case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
270    const MachineFunction *MF = MI->getParent()->getParent();
271    const char *AsmStr = MI->getOperand(0).getSymbolName();
272    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
273  }
274  }
275}
276
277MachineInstrBuilder
278MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
279                                  MachineBasicBlock::iterator I) const {
280  MachineInstrBuilder MIB;
281  MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
282
283  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J)
284    MIB.addOperand(I->getOperand(J));
285
286  MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
287  return MIB;
288}
289