MipsInstrInfo.cpp revision 0bc1adbbc4fdc6d85a671ed70a1bbd345dba445d 
1//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsAnalyzeImmediate.h"
15#include "MipsInstrInfo.h"
16#include "MipsTargetMachine.h"
17#include "MipsMachineFunction.h"
18#include "InstPrinter/MipsInstPrinter.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/TargetRegistry.h"
23#include "llvm/ADT/STLExtras.h"
24
25#define GET_INSTRINFO_CTOR
26#include "MipsGenInstrInfo.inc"
27
28using namespace llvm;
29
30MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
31  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32    TM(tm), RI(*TM.getSubtargetImpl(), *this), UncondBrOpc(UncondBr) {}
33
34const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
35  return RI;
36}
37
38bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
39  return op.isImm() && op.getImm() == 0;
40}
41
42/// insertNoop - If data hazard condition is found insert the target nop
43/// instruction.
44void MipsInstrInfo::
45insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
46{
47  DebugLoc DL;
48  BuildMI(MBB, MI, DL, get(Mips::NOP));
49}
50
51MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
52                                                unsigned Flag) const {
53  MachineFunction &MF = *MBB.getParent();
54  MachineFrameInfo &MFI = *MF.getFrameInfo();
55  unsigned Align = MFI.getObjectAlignment(FI);
56
57  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
58                                 MFI.getObjectSize(FI), Align);
59}
60
61MachineInstr*
62MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
63                                        uint64_t Offset, const MDNode *MDPtr,
64                                        DebugLoc DL) const {
65  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
66    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
67  return &*MIB;
68}
69
70//===----------------------------------------------------------------------===//
71// Branch Analysis
72//===----------------------------------------------------------------------===//
73
74void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
75                                  MachineBasicBlock *&BB,
76                                  SmallVectorImpl<MachineOperand> &Cond) const {
77  assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
78  int NumOp = Inst->getNumExplicitOperands();
79
80  // for both int and fp branches, the last explicit operand is the
81  // MBB.
82  BB = Inst->getOperand(NumOp-1).getMBB();
83  Cond.push_back(MachineOperand::CreateImm(Opc));
84
85  for (int i=0; i<NumOp-1; i++)
86    Cond.push_back(Inst->getOperand(i));
87}
88
89bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
90                                  MachineBasicBlock *&TBB,
91                                  MachineBasicBlock *&FBB,
92                                  SmallVectorImpl<MachineOperand> &Cond,
93                                  bool AllowModify) const
94{
95  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
96
97  // Skip all the debug instructions.
98  while (I != REnd && I->isDebugValue())
99    ++I;
100
101  if (I == REnd || !isUnpredicatedTerminator(&*I)) {
102    // If this block ends with no branches (it just falls through to its succ)
103    // just return false, leaving TBB/FBB null.
104    TBB = FBB = NULL;
105    return false;
106  }
107
108  MachineInstr *LastInst = &*I;
109  unsigned LastOpc = LastInst->getOpcode();
110
111  // Not an analyzable branch (must be an indirect jump).
112  if (!GetAnalyzableBrOpc(LastOpc))
113    return true;
114
115  // Get the second to last instruction in the block.
116  unsigned SecondLastOpc = 0;
117  MachineInstr *SecondLastInst = NULL;
118
119  if (++I != REnd) {
120    SecondLastInst = &*I;
121    SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
122
123    // Not an analyzable branch (must be an indirect jump).
124    if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
125      return true;
126  }
127
128  // If there is only one terminator instruction, process it.
129  if (!SecondLastOpc) {
130    // Unconditional branch
131    if (LastOpc == UncondBrOpc) {
132      TBB = LastInst->getOperand(0).getMBB();
133      return false;
134    }
135
136    // Conditional branch
137    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
138    return false;
139  }
140
141  // If we reached here, there are two branches.
142  // If there are three terminators, we don't know what sort of block this is.
143  if (++I != REnd && isUnpredicatedTerminator(&*I))
144    return true;
145
146  // If second to last instruction is an unconditional branch,
147  // analyze it and remove the last instruction.
148  if (SecondLastOpc == UncondBrOpc) {
149    // Return if the last instruction cannot be removed.
150    if (!AllowModify)
151      return true;
152
153    TBB = SecondLastInst->getOperand(0).getMBB();
154    LastInst->eraseFromParent();
155    return false;
156  }
157
158  // Conditional branch followed by an unconditional branch.
159  // The last one must be unconditional.
160  if (LastOpc != UncondBrOpc)
161    return true;
162
163  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
164  FBB = LastInst->getOperand(0).getMBB();
165
166  return false;
167}
168
169void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
170                                MachineBasicBlock *TBB, DebugLoc DL,
171                                const SmallVectorImpl<MachineOperand>& Cond)
172  const {
173  unsigned Opc = Cond[0].getImm();
174  const MCInstrDesc &MCID = get(Opc);
175  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
176
177  for (unsigned i = 1; i < Cond.size(); ++i)
178    MIB.addReg(Cond[i].getReg());
179
180  MIB.addMBB(TBB);
181}
182
183unsigned MipsInstrInfo::
184InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
185             MachineBasicBlock *FBB,
186             const SmallVectorImpl<MachineOperand> &Cond,
187             DebugLoc DL) const {
188  // Shouldn't be a fall through.
189  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
190
191  // # of condition operands:
192  //  Unconditional branches: 0
193  //  Floating point branches: 1 (opc)
194  //  Int BranchZero: 2 (opc, reg)
195  //  Int Branch: 3 (opc, reg0, reg1)
196  assert((Cond.size() <= 3) &&
197         "# of Mips branch conditions must be <= 3!");
198
199  // Two-way Conditional branch.
200  if (FBB) {
201    BuildCondBr(MBB, TBB, DL, Cond);
202    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
203    return 2;
204  }
205
206  // One way branch.
207  // Unconditional branch.
208  if (Cond.empty())
209    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
210  else // Conditional branch.
211    BuildCondBr(MBB, TBB, DL, Cond);
212  return 1;
213}
214
215unsigned MipsInstrInfo::
216RemoveBranch(MachineBasicBlock &MBB) const
217{
218  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
219  MachineBasicBlock::reverse_iterator FirstBr;
220  unsigned removed;
221
222  // Skip all the debug instructions.
223  while (I != REnd && I->isDebugValue())
224    ++I;
225
226  FirstBr = I;
227
228  // Up to 2 branches are removed.
229  // Note that indirect branches are not removed.
230  for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
231    if (!GetAnalyzableBrOpc(I->getOpcode()))
232      break;
233
234  MBB.erase(I.base(), FirstBr.base());
235
236  return removed;
237}
238
239/// ReverseBranchCondition - Return the inverse opcode of the
240/// specified Branch instruction.
241bool MipsInstrInfo::
242ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
243{
244  assert( (Cond.size() && Cond.size() <= 3) &&
245          "Invalid Mips branch condition!");
246  Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
247  return false;
248}
249
250/// Return the number of bytes of code the specified instruction may be.
251unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
252  switch (MI->getOpcode()) {
253  default:
254    return MI->getDesc().getSize();
255  case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
256    const MachineFunction *MF = MI->getParent()->getParent();
257    const char *AsmStr = MI->getOperand(0).getSymbolName();
258    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
259  }
260  }
261}
262
263unsigned
264llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
265                          MachineBasicBlock& MBB,
266                          MachineBasicBlock::iterator II, DebugLoc DL,
267                          bool LastInstrIsADDiu,
268                          MipsAnalyzeImmediate::Inst *LastInst) {
269  MipsAnalyzeImmediate AnalyzeImm;
270  unsigned Size = IsN64 ? 64 : 32;
271  unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
272  unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
273  unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
274
275  const MipsAnalyzeImmediate::InstSeq &Seq =
276    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
277  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
278
279  if (LastInst && (Seq.size() == 1)) {
280    *LastInst = *Inst;
281    return 0;
282  }
283
284  // The first instruction can be a LUi, which is different from other
285  // instructions (ADDiu, ORI and SLL) in that it does not have a register
286  // operand.
287  if (Inst->Opc == LUi)
288    BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
289      .addImm(SignExtend64<16>(Inst->ImmOpnd));
290  else
291    BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
292      .addImm(SignExtend64<16>(Inst->ImmOpnd));
293
294  // Build the remaining instructions in Seq. Skip the last instruction if
295  // LastInst is not 0.
296  for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
297    BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
298      .addImm(SignExtend64<16>(Inst->ImmOpnd));
299
300  if (LastInst)
301    *LastInst = *Inst;
302
303  return Seq.size() - !!LastInst;
304}
305