MipsInstrInfo.cpp revision 3ee306cbc0a295409c464ffaad5ef694de8eb09a 
1//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsAnalyzeImmediate.h"
15#include "MipsInstrInfo.h"
16#include "MipsTargetMachine.h"
17#include "MipsMachineFunction.h"
18#include "InstPrinter/MipsInstPrinter.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/TargetRegistry.h"
23#include "llvm/ADT/STLExtras.h"
24
25#define GET_INSTRINFO_CTOR
26#include "MipsGenInstrInfo.inc"
27
28using namespace llvm;
29
30MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
31  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32    TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
33    InMips16Mode(TM.getSubtarget<MipsSubtarget>().inMips16Mode()),
34    RI(*TM.getSubtargetImpl(), *this),
35    UncondBrOpc(TM.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J) {}
36
37const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
38  return RI;
39}
40
41static bool isZeroImm(const MachineOperand &op) {
42  return op.isImm() && op.getImm() == 0;
43}
44
45/// isLoadFromStackSlot - If the specified machine instruction is a direct
46/// load from a stack slot, return the virtual or physical register number of
47/// the destination along with the FrameIndex of the loaded stack slot.  If
48/// not, return 0.  This predicate must return 0 if the instruction has
49/// any side effects other than loading from the stack slot.
50unsigned MipsInstrInfo::
51isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
52{
53  unsigned Opc = MI->getOpcode();
54
55  if ((Opc == Mips::LW)    || (Opc == Mips::LW_P8)  || (Opc == Mips::LD) ||
56      (Opc == Mips::LD_P8) || (Opc == Mips::LWC1)   || (Opc == Mips::LWC1_P8) ||
57      (Opc == Mips::LDC1)  || (Opc == Mips::LDC164) ||
58      (Opc == Mips::LDC164_P8)) {
59    if ((MI->getOperand(1).isFI()) && // is a stack slot
60        (MI->getOperand(2).isImm()) &&  // the imm is zero
61        (isZeroImm(MI->getOperand(2)))) {
62      FrameIndex = MI->getOperand(1).getIndex();
63      return MI->getOperand(0).getReg();
64    }
65  }
66
67  return 0;
68}
69
70/// isStoreToStackSlot - If the specified machine instruction is a direct
71/// store to a stack slot, return the virtual or physical register number of
72/// the source reg along with the FrameIndex of the loaded stack slot.  If
73/// not, return 0.  This predicate must return 0 if the instruction has
74/// any side effects other than storing to the stack slot.
75unsigned MipsInstrInfo::
76isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
77{
78  unsigned Opc = MI->getOpcode();
79
80  if ((Opc == Mips::SW)    || (Opc == Mips::SW_P8)  || (Opc == Mips::SD) ||
81      (Opc == Mips::SD_P8) || (Opc == Mips::SWC1)   || (Opc == Mips::SWC1_P8) ||
82      (Opc == Mips::SDC1)  || (Opc == Mips::SDC164) ||
83      (Opc == Mips::SDC164_P8)) {
84    if ((MI->getOperand(1).isFI()) && // is a stack slot
85        (MI->getOperand(2).isImm()) &&  // the imm is zero
86        (isZeroImm(MI->getOperand(2)))) {
87      FrameIndex = MI->getOperand(1).getIndex();
88      return MI->getOperand(0).getReg();
89    }
90  }
91  return 0;
92}
93
94/// insertNoop - If data hazard condition is found insert the target nop
95/// instruction.
96void MipsInstrInfo::
97insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
98{
99  DebugLoc DL;
100  BuildMI(MBB, MI, DL, get(Mips::NOP));
101}
102
103void MipsInstrInfo::
104copyPhysReg(MachineBasicBlock &MBB,
105            MachineBasicBlock::iterator I, DebugLoc DL,
106            unsigned DestReg, unsigned SrcReg,
107            bool KillSrc) const {
108  unsigned Opc = 0, ZeroReg = 0;
109
110  if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
111    if (Mips::CPURegsRegClass.contains(SrcReg)) {
112      if (InMips16Mode)
113        Opc=Mips::Mov32R16;
114      else {
115        Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
116      }
117    }
118    else if (Mips::CCRRegClass.contains(SrcReg))
119      Opc = Mips::CFC1;
120    else if (Mips::FGR32RegClass.contains(SrcReg))
121      Opc = Mips::MFC1;
122    else if (SrcReg == Mips::HI)
123      Opc = Mips::MFHI, SrcReg = 0;
124    else if (SrcReg == Mips::LO)
125      Opc = Mips::MFLO, SrcReg = 0;
126  }
127  else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
128    if (Mips::CCRRegClass.contains(DestReg))
129      Opc = Mips::CTC1;
130    else if (Mips::FGR32RegClass.contains(DestReg))
131      Opc = Mips::MTC1;
132    else if (DestReg == Mips::HI)
133      Opc = Mips::MTHI, DestReg = 0;
134    else if (DestReg == Mips::LO)
135      Opc = Mips::MTLO, DestReg = 0;
136  }
137  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
138    Opc = Mips::FMOV_S;
139  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
140    Opc = Mips::FMOV_D32;
141  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
142    Opc = Mips::FMOV_D64;
143  else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
144    Opc = Mips::MOVCCRToCCR;
145  else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146    if (Mips::CPU64RegsRegClass.contains(SrcReg))
147      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
148    else if (SrcReg == Mips::HI64)
149      Opc = Mips::MFHI64, SrcReg = 0;
150    else if (SrcReg == Mips::LO64)
151      Opc = Mips::MFLO64, SrcReg = 0;
152    else if (Mips::FGR64RegClass.contains(SrcReg))
153      Opc = Mips::DMFC1;
154  }
155  else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
156    if (DestReg == Mips::HI64)
157      Opc = Mips::MTHI64, DestReg = 0;
158    else if (DestReg == Mips::LO64)
159      Opc = Mips::MTLO64, DestReg = 0;
160    else if (Mips::FGR64RegClass.contains(DestReg))
161      Opc = Mips::DMTC1;
162  }
163
164  assert(Opc && "Cannot copy registers");
165
166  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
167
168  if (DestReg)
169    MIB.addReg(DestReg, RegState::Define);
170
171  if (ZeroReg)
172    MIB.addReg(ZeroReg);
173
174  if (SrcReg)
175    MIB.addReg(SrcReg, getKillRegState(KillSrc));
176}
177
178static MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI,
179                                        unsigned Flag) {
180  MachineFunction &MF = *MBB.getParent();
181  MachineFrameInfo &MFI = *MF.getFrameInfo();
182  unsigned Align = MFI.getObjectAlignment(FI);
183
184  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
185                                 MFI.getObjectSize(FI), Align);
186}
187
188void MipsInstrInfo::
189storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
190                    unsigned SrcReg, bool isKill, int FI,
191                    const TargetRegisterClass *RC,
192                    const TargetRegisterInfo *TRI) const {
193  DebugLoc DL;
194  if (I != MBB.end()) DL = I->getDebugLoc();
195  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
196
197  unsigned Opc = 0;
198
199  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
200    Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
201  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
202    Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
203  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
204    Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
205  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
206    Opc = Mips::SDC1;
207  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
208    Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
209
210  assert(Opc && "Register class not handled!");
211  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
212    .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
213}
214
215void MipsInstrInfo::
216loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
217                     unsigned DestReg, int FI,
218                     const TargetRegisterClass *RC,
219                     const TargetRegisterInfo *TRI) const
220{
221  DebugLoc DL;
222  if (I != MBB.end()) DL = I->getDebugLoc();
223  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
224  unsigned Opc = 0;
225
226  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
227    Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
228  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
229    Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
230  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
231    Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
232  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
233    Opc = Mips::LDC1;
234  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
235    Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
236
237  assert(Opc && "Register class not handled!");
238  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
239    .addMemOperand(MMO);
240}
241
242void MipsInstrInfo::ExpandRetRA(MachineBasicBlock &MBB,
243                                MachineBasicBlock::iterator I,
244                                unsigned Opc) const {
245  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(Opc))
246    .addReg(Mips::RA);
247}
248
249void MipsInstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
250                                MachineBasicBlock::iterator I,
251                                unsigned Opc) const {
252  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(Opc));
253}
254
255void MipsInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
256                                          MachineBasicBlock::iterator I) const {
257  const TargetInstrInfo *TII = TM.getInstrInfo();
258  unsigned DstReg = I->getOperand(0).getReg();
259  unsigned SrcReg = I->getOperand(1).getReg();
260  unsigned N = I->getOperand(2).getImm();
261  const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
262  DebugLoc dl = I->getDebugLoc();
263
264  assert(N < 2 && "Invalid immediate");
265  unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
266  unsigned SubReg = TM.getRegisterInfo()->getSubReg(SrcReg, SubIdx);
267
268  BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
269}
270
271void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
272                                       MachineBasicBlock::iterator I) const {
273  const TargetInstrInfo *TII = TM.getInstrInfo();
274  unsigned DstReg = I->getOperand(0).getReg();
275  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
276  const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
277  DebugLoc dl = I->getDebugLoc();
278  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
279
280  // mtc1 Lo, $fp
281  // mtc1 Hi, $fp + 1
282  BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpeven))
283    .addReg(LoReg);
284  BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpodd))
285    .addReg(HiReg);
286}
287
288bool MipsInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
289  MachineBasicBlock &MBB = *MI->getParent();
290
291  switch(MI->getDesc().getOpcode()) {
292  default:
293    return false;
294  case Mips::RetRA:
295    ExpandRetRA(MBB, MI, Mips::RET);
296    break;
297  case Mips::RetRA16:
298    ExpandRetRA16(MBB, MI, Mips::JrRa16);
299    break;
300  case Mips::BuildPairF64:
301    ExpandBuildPairF64(MBB, MI);
302    break;
303  case Mips::ExtractElementF64:
304    ExpandExtractElementF64(MBB, MI);
305    break;
306  }
307
308  MBB.erase(MI);
309  return true;
310}
311
312MachineInstr*
313MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
314                                        uint64_t Offset, const MDNode *MDPtr,
315                                        DebugLoc DL) const {
316  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
317    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
318  return &*MIB;
319}
320
321//===----------------------------------------------------------------------===//
322// Branch Analysis
323//===----------------------------------------------------------------------===//
324
325static unsigned GetAnalyzableBrOpc(unsigned Opc) {
326  return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
327          Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
328          Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
329          Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
330          Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
331          Opc == Mips::J) ?
332         Opc : 0;
333}
334
335/// GetOppositeBranchOpc - Return the inverse of the specified
336/// opcode, e.g. turning BEQ to BNE.
337unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
338{
339  switch (Opc) {
340  default:           llvm_unreachable("Illegal opcode!");
341  case Mips::BEQ:    return Mips::BNE;
342  case Mips::BNE:    return Mips::BEQ;
343  case Mips::BGTZ:   return Mips::BLEZ;
344  case Mips::BGEZ:   return Mips::BLTZ;
345  case Mips::BLTZ:   return Mips::BGEZ;
346  case Mips::BLEZ:   return Mips::BGTZ;
347  case Mips::BEQ64:  return Mips::BNE64;
348  case Mips::BNE64:  return Mips::BEQ64;
349  case Mips::BGTZ64: return Mips::BLEZ64;
350  case Mips::BGEZ64: return Mips::BLTZ64;
351  case Mips::BLTZ64: return Mips::BGEZ64;
352  case Mips::BLEZ64: return Mips::BGTZ64;
353  case Mips::BC1T:   return Mips::BC1F;
354  case Mips::BC1F:   return Mips::BC1T;
355  }
356}
357
358static void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
359                          MachineBasicBlock *&BB,
360                          SmallVectorImpl<MachineOperand> &Cond) {
361  assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
362  int NumOp = Inst->getNumExplicitOperands();
363
364  // for both int and fp branches, the last explicit operand is the
365  // MBB.
366  BB = Inst->getOperand(NumOp-1).getMBB();
367  Cond.push_back(MachineOperand::CreateImm(Opc));
368
369  for (int i=0; i<NumOp-1; i++)
370    Cond.push_back(Inst->getOperand(i));
371}
372
373bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
374                                  MachineBasicBlock *&TBB,
375                                  MachineBasicBlock *&FBB,
376                                  SmallVectorImpl<MachineOperand> &Cond,
377                                  bool AllowModify) const
378{
379  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
380
381  // Skip all the debug instructions.
382  while (I != REnd && I->isDebugValue())
383    ++I;
384
385  if (I == REnd || !isUnpredicatedTerminator(&*I)) {
386    // If this block ends with no branches (it just falls through to its succ)
387    // just return false, leaving TBB/FBB null.
388    TBB = FBB = NULL;
389    return false;
390  }
391
392  MachineInstr *LastInst = &*I;
393  unsigned LastOpc = LastInst->getOpcode();
394
395  // Not an analyzable branch (must be an indirect jump).
396  if (!GetAnalyzableBrOpc(LastOpc))
397    return true;
398
399  // Get the second to last instruction in the block.
400  unsigned SecondLastOpc = 0;
401  MachineInstr *SecondLastInst = NULL;
402
403  if (++I != REnd) {
404    SecondLastInst = &*I;
405    SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
406
407    // Not an analyzable branch (must be an indirect jump).
408    if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
409      return true;
410  }
411
412  // If there is only one terminator instruction, process it.
413  if (!SecondLastOpc) {
414    // Unconditional branch
415    if (LastOpc == UncondBrOpc) {
416      TBB = LastInst->getOperand(0).getMBB();
417      return false;
418    }
419
420    // Conditional branch
421    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
422    return false;
423  }
424
425  // If we reached here, there are two branches.
426  // If there are three terminators, we don't know what sort of block this is.
427  if (++I != REnd && isUnpredicatedTerminator(&*I))
428    return true;
429
430  // If second to last instruction is an unconditional branch,
431  // analyze it and remove the last instruction.
432  if (SecondLastOpc == UncondBrOpc) {
433    // Return if the last instruction cannot be removed.
434    if (!AllowModify)
435      return true;
436
437    TBB = SecondLastInst->getOperand(0).getMBB();
438    LastInst->eraseFromParent();
439    return false;
440  }
441
442  // Conditional branch followed by an unconditional branch.
443  // The last one must be unconditional.
444  if (LastOpc != UncondBrOpc)
445    return true;
446
447  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
448  FBB = LastInst->getOperand(0).getMBB();
449
450  return false;
451}
452
453void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
454                                MachineBasicBlock *TBB, DebugLoc DL,
455                                const SmallVectorImpl<MachineOperand>& Cond)
456  const {
457  unsigned Opc = Cond[0].getImm();
458  const MCInstrDesc &MCID = get(Opc);
459  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
460
461  for (unsigned i = 1; i < Cond.size(); ++i)
462    MIB.addReg(Cond[i].getReg());
463
464  MIB.addMBB(TBB);
465}
466
467unsigned MipsInstrInfo::
468InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
469             MachineBasicBlock *FBB,
470             const SmallVectorImpl<MachineOperand> &Cond,
471             DebugLoc DL) const {
472  // Shouldn't be a fall through.
473  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
474
475  // # of condition operands:
476  //  Unconditional branches: 0
477  //  Floating point branches: 1 (opc)
478  //  Int BranchZero: 2 (opc, reg)
479  //  Int Branch: 3 (opc, reg0, reg1)
480  assert((Cond.size() <= 3) &&
481         "# of Mips branch conditions must be <= 3!");
482
483  // Two-way Conditional branch.
484  if (FBB) {
485    BuildCondBr(MBB, TBB, DL, Cond);
486    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
487    return 2;
488  }
489
490  // One way branch.
491  // Unconditional branch.
492  if (Cond.empty())
493    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
494  else // Conditional branch.
495    BuildCondBr(MBB, TBB, DL, Cond);
496  return 1;
497}
498
499unsigned MipsInstrInfo::
500RemoveBranch(MachineBasicBlock &MBB) const
501{
502  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
503  MachineBasicBlock::reverse_iterator FirstBr;
504  unsigned removed;
505
506  // Skip all the debug instructions.
507  while (I != REnd && I->isDebugValue())
508    ++I;
509
510  FirstBr = I;
511
512  // Up to 2 branches are removed.
513  // Note that indirect branches are not removed.
514  for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
515    if (!GetAnalyzableBrOpc(I->getOpcode()))
516      break;
517
518  MBB.erase(I.base(), FirstBr.base());
519
520  return removed;
521}
522
523/// ReverseBranchCondition - Return the inverse opcode of the
524/// specified Branch instruction.
525bool MipsInstrInfo::
526ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
527{
528  assert( (Cond.size() && Cond.size() <= 3) &&
529          "Invalid Mips branch condition!");
530  Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
531  return false;
532}
533
534/// Return the number of bytes of code the specified instruction may be.
535unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
536  switch (MI->getOpcode()) {
537  default:
538    return MI->getDesc().getSize();
539  case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
540    const MachineFunction *MF = MI->getParent()->getParent();
541    const char *AsmStr = MI->getOperand(0).getSymbolName();
542    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
543  }
544  }
545}
546
547unsigned
548llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
549                          MachineBasicBlock& MBB,
550                          MachineBasicBlock::iterator II, DebugLoc DL,
551                          bool LastInstrIsADDiu,
552                          MipsAnalyzeImmediate::Inst *LastInst) {
553  MipsAnalyzeImmediate AnalyzeImm;
554  unsigned Size = IsN64 ? 64 : 32;
555  unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
556  unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
557  unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
558
559  const MipsAnalyzeImmediate::InstSeq &Seq =
560    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
561  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
562
563  if (LastInst && (Seq.size() == 1)) {
564    *LastInst = *Inst;
565    return 0;
566  }
567
568  // The first instruction can be a LUi, which is different from other
569  // instructions (ADDiu, ORI and SLL) in that it does not have a register
570  // operand.
571  if (Inst->Opc == LUi)
572    BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
573      .addImm(SignExtend64<16>(Inst->ImmOpnd));
574  else
575    BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
576      .addImm(SignExtend64<16>(Inst->ImmOpnd));
577
578  // Build the remaining instructions in Seq. Skip the last instruction if
579  // LastInst is not 0.
580  for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
581    BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
582      .addImm(SignExtend64<16>(Inst->ImmOpnd));
583
584  if (LastInst)
585    *LastInst = *Inst;
586
587  return Seq.size() - !!LastInst;
588}
589