MipsInstrInfo.cpp revision 8589010e3d1d5a902992a5039cffa9d4116982c5 
1//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsAnalyzeImmediate.h"
15#include "MipsInstrInfo.h"
16#include "MipsTargetMachine.h"
17#include "MipsMachineFunction.h"
18#include "InstPrinter/MipsInstPrinter.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/TargetRegistry.h"
23#include "llvm/ADT/STLExtras.h"
24
25#define GET_INSTRINFO_CTOR
26#include "MipsGenInstrInfo.inc"
27
28using namespace llvm;
29
30MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
31  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32    TM(tm), UncondBrOpc(UncondBr) {}
33
34bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
35  return op.isImm() && op.getImm() == 0;
36}
37
38/// insertNoop - If data hazard condition is found insert the target nop
39/// instruction.
40void MipsInstrInfo::
41insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
42{
43  DebugLoc DL;
44  BuildMI(MBB, MI, DL, get(Mips::NOP));
45}
46
47MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
48                                                unsigned Flag) const {
49  MachineFunction &MF = *MBB.getParent();
50  MachineFrameInfo &MFI = *MF.getFrameInfo();
51  unsigned Align = MFI.getObjectAlignment(FI);
52
53  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
54                                 MFI.getObjectSize(FI), Align);
55}
56
57MachineInstr*
58MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
59                                        uint64_t Offset, const MDNode *MDPtr,
60                                        DebugLoc DL) const {
61  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
62    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
63  return &*MIB;
64}
65
66//===----------------------------------------------------------------------===//
67// Branch Analysis
68//===----------------------------------------------------------------------===//
69
70void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
71                                  MachineBasicBlock *&BB,
72                                  SmallVectorImpl<MachineOperand> &Cond) const {
73  assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
74  int NumOp = Inst->getNumExplicitOperands();
75
76  // for both int and fp branches, the last explicit operand is the
77  // MBB.
78  BB = Inst->getOperand(NumOp-1).getMBB();
79  Cond.push_back(MachineOperand::CreateImm(Opc));
80
81  for (int i=0; i<NumOp-1; i++)
82    Cond.push_back(Inst->getOperand(i));
83}
84
85bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
86                                  MachineBasicBlock *&TBB,
87                                  MachineBasicBlock *&FBB,
88                                  SmallVectorImpl<MachineOperand> &Cond,
89                                  bool AllowModify) const
90{
91  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
92
93  // Skip all the debug instructions.
94  while (I != REnd && I->isDebugValue())
95    ++I;
96
97  if (I == REnd || !isUnpredicatedTerminator(&*I)) {
98    // If this block ends with no branches (it just falls through to its succ)
99    // just return false, leaving TBB/FBB null.
100    TBB = FBB = NULL;
101    return false;
102  }
103
104  MachineInstr *LastInst = &*I;
105  unsigned LastOpc = LastInst->getOpcode();
106
107  // Not an analyzable branch (must be an indirect jump).
108  if (!GetAnalyzableBrOpc(LastOpc))
109    return true;
110
111  // Get the second to last instruction in the block.
112  unsigned SecondLastOpc = 0;
113  MachineInstr *SecondLastInst = NULL;
114
115  if (++I != REnd) {
116    SecondLastInst = &*I;
117    SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
118
119    // Not an analyzable branch (must be an indirect jump).
120    if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
121      return true;
122  }
123
124  // If there is only one terminator instruction, process it.
125  if (!SecondLastOpc) {
126    // Unconditional branch
127    if (LastOpc == UncondBrOpc) {
128      TBB = LastInst->getOperand(0).getMBB();
129      return false;
130    }
131
132    // Conditional branch
133    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
134    return false;
135  }
136
137  // If we reached here, there are two branches.
138  // If there are three terminators, we don't know what sort of block this is.
139  if (++I != REnd && isUnpredicatedTerminator(&*I))
140    return true;
141
142  // If second to last instruction is an unconditional branch,
143  // analyze it and remove the last instruction.
144  if (SecondLastOpc == UncondBrOpc) {
145    // Return if the last instruction cannot be removed.
146    if (!AllowModify)
147      return true;
148
149    TBB = SecondLastInst->getOperand(0).getMBB();
150    LastInst->eraseFromParent();
151    return false;
152  }
153
154  // Conditional branch followed by an unconditional branch.
155  // The last one must be unconditional.
156  if (LastOpc != UncondBrOpc)
157    return true;
158
159  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
160  FBB = LastInst->getOperand(0).getMBB();
161
162  return false;
163}
164
165void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
166                                MachineBasicBlock *TBB, DebugLoc DL,
167                                const SmallVectorImpl<MachineOperand>& Cond)
168  const {
169  unsigned Opc = Cond[0].getImm();
170  const MCInstrDesc &MCID = get(Opc);
171  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
172
173  for (unsigned i = 1; i < Cond.size(); ++i)
174    MIB.addReg(Cond[i].getReg());
175
176  MIB.addMBB(TBB);
177}
178
179unsigned MipsInstrInfo::
180InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
181             MachineBasicBlock *FBB,
182             const SmallVectorImpl<MachineOperand> &Cond,
183             DebugLoc DL) const {
184  // Shouldn't be a fall through.
185  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
186
187  // # of condition operands:
188  //  Unconditional branches: 0
189  //  Floating point branches: 1 (opc)
190  //  Int BranchZero: 2 (opc, reg)
191  //  Int Branch: 3 (opc, reg0, reg1)
192  assert((Cond.size() <= 3) &&
193         "# of Mips branch conditions must be <= 3!");
194
195  // Two-way Conditional branch.
196  if (FBB) {
197    BuildCondBr(MBB, TBB, DL, Cond);
198    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
199    return 2;
200  }
201
202  // One way branch.
203  // Unconditional branch.
204  if (Cond.empty())
205    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
206  else // Conditional branch.
207    BuildCondBr(MBB, TBB, DL, Cond);
208  return 1;
209}
210
211unsigned MipsInstrInfo::
212RemoveBranch(MachineBasicBlock &MBB) const
213{
214  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
215  MachineBasicBlock::reverse_iterator FirstBr;
216  unsigned removed;
217
218  // Skip all the debug instructions.
219  while (I != REnd && I->isDebugValue())
220    ++I;
221
222  FirstBr = I;
223
224  // Up to 2 branches are removed.
225  // Note that indirect branches are not removed.
226  for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
227    if (!GetAnalyzableBrOpc(I->getOpcode()))
228      break;
229
230  MBB.erase(I.base(), FirstBr.base());
231
232  return removed;
233}
234
235/// ReverseBranchCondition - Return the inverse opcode of the
236/// specified Branch instruction.
237bool MipsInstrInfo::
238ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
239{
240  assert( (Cond.size() && Cond.size() <= 3) &&
241          "Invalid Mips branch condition!");
242  Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
243  return false;
244}
245
246/// Return the number of bytes of code the specified instruction may be.
247unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
248  switch (MI->getOpcode()) {
249  default:
250    return MI->getDesc().getSize();
251  case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
252    const MachineFunction *MF = MI->getParent()->getParent();
253    const char *AsmStr = MI->getOperand(0).getSymbolName();
254    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
255  }
256  }
257}
258
259unsigned
260llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
261                          MachineBasicBlock& MBB,
262                          MachineBasicBlock::iterator II, DebugLoc DL,
263                          bool LastInstrIsADDiu,
264                          MipsAnalyzeImmediate::Inst *LastInst) {
265  MipsAnalyzeImmediate AnalyzeImm;
266  unsigned Size = IsN64 ? 64 : 32;
267  unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
268  unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
269  unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
270
271  const MipsAnalyzeImmediate::InstSeq &Seq =
272    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
273  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
274
275  if (LastInst && (Seq.size() == 1)) {
276    *LastInst = *Inst;
277    return 0;
278  }
279
280  // The first instruction can be a LUi, which is different from other
281  // instructions (ADDiu, ORI and SLL) in that it does not have a register
282  // operand.
283  if (Inst->Opc == LUi)
284    BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
285      .addImm(SignExtend64<16>(Inst->ImmOpnd));
286  else
287    BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
288      .addImm(SignExtend64<16>(Inst->ImmOpnd));
289
290  // Build the remaining instructions in Seq. Skip the last instruction if
291  // LastInst is not 0.
292  for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
293    BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
294      .addImm(SignExtend64<16>(Inst->ImmOpnd));
295
296  if (LastInst)
297    *LastInst = *Inst;
298
299  return Seq.size() - !!LastInst;
300}
301