MipsInstrInfo.cpp revision 864f66085cd9543070ef01b9f7371c110ecd7898 
1//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsAnalyzeImmediate.h"
15#include "MipsInstrInfo.h"
16#include "MipsTargetMachine.h"
17#include "MipsMachineFunction.h"
18#include "InstPrinter/MipsInstPrinter.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/TargetRegistry.h"
23#include "llvm/ADT/STLExtras.h"
24
25#define GET_INSTRINFO_CTOR
26#include "MipsGenInstrInfo.inc"
27
28using namespace llvm;
29
30MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
31  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32    TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
33    RI(*TM.getSubtargetImpl(), *this),
34    UncondBrOpc(TM.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J) {}
35
36const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
37  return RI;
38}
39
40static bool isZeroImm(const MachineOperand &op) {
41  return op.isImm() && op.getImm() == 0;
42}
43
44/// isLoadFromStackSlot - If the specified machine instruction is a direct
45/// load from a stack slot, return the virtual or physical register number of
46/// the destination along with the FrameIndex of the loaded stack slot.  If
47/// not, return 0.  This predicate must return 0 if the instruction has
48/// any side effects other than loading from the stack slot.
49unsigned MipsInstrInfo::
50isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
51{
52  unsigned Opc = MI->getOpcode();
53
54  if ((Opc == Mips::LW)    || (Opc == Mips::LW_P8)  || (Opc == Mips::LD) ||
55      (Opc == Mips::LD_P8) || (Opc == Mips::LWC1)   || (Opc == Mips::LWC1_P8) ||
56      (Opc == Mips::LDC1)  || (Opc == Mips::LDC164) ||
57      (Opc == Mips::LDC164_P8)) {
58    if ((MI->getOperand(1).isFI()) && // is a stack slot
59        (MI->getOperand(2).isImm()) &&  // the imm is zero
60        (isZeroImm(MI->getOperand(2)))) {
61      FrameIndex = MI->getOperand(1).getIndex();
62      return MI->getOperand(0).getReg();
63    }
64  }
65
66  return 0;
67}
68
69/// isStoreToStackSlot - If the specified machine instruction is a direct
70/// store to a stack slot, return the virtual or physical register number of
71/// the source reg along with the FrameIndex of the loaded stack slot.  If
72/// not, return 0.  This predicate must return 0 if the instruction has
73/// any side effects other than storing to the stack slot.
74unsigned MipsInstrInfo::
75isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
76{
77  unsigned Opc = MI->getOpcode();
78
79  if ((Opc == Mips::SW)    || (Opc == Mips::SW_P8)  || (Opc == Mips::SD) ||
80      (Opc == Mips::SD_P8) || (Opc == Mips::SWC1)   || (Opc == Mips::SWC1_P8) ||
81      (Opc == Mips::SDC1)  || (Opc == Mips::SDC164) ||
82      (Opc == Mips::SDC164_P8)) {
83    if ((MI->getOperand(1).isFI()) && // is a stack slot
84        (MI->getOperand(2).isImm()) &&  // the imm is zero
85        (isZeroImm(MI->getOperand(2)))) {
86      FrameIndex = MI->getOperand(1).getIndex();
87      return MI->getOperand(0).getReg();
88    }
89  }
90  return 0;
91}
92
93/// insertNoop - If data hazard condition is found insert the target nop
94/// instruction.
95void MipsInstrInfo::
96insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
97{
98  DebugLoc DL;
99  BuildMI(MBB, MI, DL, get(Mips::NOP));
100}
101
102void MipsInstrInfo::
103copyPhysReg(MachineBasicBlock &MBB,
104            MachineBasicBlock::iterator I, DebugLoc DL,
105            unsigned DestReg, unsigned SrcReg,
106            bool KillSrc) const {
107  unsigned Opc = 0, ZeroReg = 0;
108
109  if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
110    if (Mips::CPURegsRegClass.contains(SrcReg))
111      Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
112    else if (Mips::CCRRegClass.contains(SrcReg))
113      Opc = Mips::CFC1;
114    else if (Mips::FGR32RegClass.contains(SrcReg))
115      Opc = Mips::MFC1;
116    else if (SrcReg == Mips::HI)
117      Opc = Mips::MFHI, SrcReg = 0;
118    else if (SrcReg == Mips::LO)
119      Opc = Mips::MFLO, SrcReg = 0;
120  }
121  else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
122    if (Mips::CCRRegClass.contains(DestReg))
123      Opc = Mips::CTC1;
124    else if (Mips::FGR32RegClass.contains(DestReg))
125      Opc = Mips::MTC1;
126    else if (DestReg == Mips::HI)
127      Opc = Mips::MTHI, DestReg = 0;
128    else if (DestReg == Mips::LO)
129      Opc = Mips::MTLO, DestReg = 0;
130  }
131  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
132    Opc = Mips::FMOV_S;
133  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
134    Opc = Mips::FMOV_D32;
135  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
136    Opc = Mips::FMOV_D64;
137  else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
138    Opc = Mips::MOVCCRToCCR;
139  else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
140    if (Mips::CPU64RegsRegClass.contains(SrcReg))
141      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
142    else if (SrcReg == Mips::HI64)
143      Opc = Mips::MFHI64, SrcReg = 0;
144    else if (SrcReg == Mips::LO64)
145      Opc = Mips::MFLO64, SrcReg = 0;
146    else if (Mips::FGR64RegClass.contains(SrcReg))
147      Opc = Mips::DMFC1;
148  }
149  else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
150    if (DestReg == Mips::HI64)
151      Opc = Mips::MTHI64, DestReg = 0;
152    else if (DestReg == Mips::LO64)
153      Opc = Mips::MTLO64, DestReg = 0;
154    else if (Mips::FGR64RegClass.contains(DestReg))
155      Opc = Mips::DMTC1;
156  }
157
158  assert(Opc && "Cannot copy registers");
159
160  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
161
162  if (DestReg)
163    MIB.addReg(DestReg, RegState::Define);
164
165  if (ZeroReg)
166    MIB.addReg(ZeroReg);
167
168  if (SrcReg)
169    MIB.addReg(SrcReg, getKillRegState(KillSrc));
170}
171
172static MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI,
173                                        unsigned Flag) {
174  MachineFunction &MF = *MBB.getParent();
175  MachineFrameInfo &MFI = *MF.getFrameInfo();
176  unsigned Align = MFI.getObjectAlignment(FI);
177
178  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
179                                 MFI.getObjectSize(FI), Align);
180}
181
182void MipsInstrInfo::
183storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184                    unsigned SrcReg, bool isKill, int FI,
185                    const TargetRegisterClass *RC,
186                    const TargetRegisterInfo *TRI) const {
187  DebugLoc DL;
188  if (I != MBB.end()) DL = I->getDebugLoc();
189  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
190
191  unsigned Opc = 0;
192
193  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
194    Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
195  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
196    Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
197  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
198    Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
199  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
200    Opc = Mips::SDC1;
201  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
202    Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
203
204  assert(Opc && "Register class not handled!");
205  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
206    .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
207}
208
209void MipsInstrInfo::
210loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
211                     unsigned DestReg, int FI,
212                     const TargetRegisterClass *RC,
213                     const TargetRegisterInfo *TRI) const
214{
215  DebugLoc DL;
216  if (I != MBB.end()) DL = I->getDebugLoc();
217  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
218  unsigned Opc = 0;
219
220  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
221    Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
222  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
223    Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
224  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
225    Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
226  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
227    Opc = Mips::LDC1;
228  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
229    Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
230
231  assert(Opc && "Register class not handled!");
232  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
233    .addMemOperand(MMO);
234}
235
236void MipsInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
237                                          MachineBasicBlock::iterator I) const {
238  const TargetInstrInfo *TII = TM.getInstrInfo();
239  unsigned DstReg = I->getOperand(0).getReg();
240  unsigned SrcReg = I->getOperand(1).getReg();
241  unsigned N = I->getOperand(2).getImm();
242  const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
243  DebugLoc dl = I->getDebugLoc();
244
245  assert(N < 2 && "Invalid immediate");
246  unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
247  unsigned SubReg = TM.getRegisterInfo()->getSubReg(SrcReg, SubIdx);
248
249  BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
250}
251
252void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
253                                       MachineBasicBlock::iterator I) const {
254  const TargetInstrInfo *TII = TM.getInstrInfo();
255  unsigned DstReg = I->getOperand(0).getReg();
256  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
257  const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
258  DebugLoc dl = I->getDebugLoc();
259  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
260
261  // mtc1 Lo, $fp
262  // mtc1 Hi, $fp + 1
263  BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpeven))
264    .addReg(LoReg);
265  BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpodd))
266    .addReg(HiReg);
267}
268
269bool MipsInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
270  MachineBasicBlock &MBB = *MI->getParent();
271
272  switch(MI->getDesc().getOpcode()) {
273  default:
274    return false;
275  case Mips::BuildPairF64:
276    ExpandBuildPairF64(MBB, MI);
277    break;
278  case Mips::ExtractElementF64:
279    ExpandExtractElementF64(MBB, MI);
280    break;
281  }
282
283  MBB.erase(MI);
284  return true;
285}
286
287MachineInstr*
288MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
289                                        uint64_t Offset, const MDNode *MDPtr,
290                                        DebugLoc DL) const {
291  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
292    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
293  return &*MIB;
294}
295
296//===----------------------------------------------------------------------===//
297// Branch Analysis
298//===----------------------------------------------------------------------===//
299
300static unsigned GetAnalyzableBrOpc(unsigned Opc) {
301  return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
302          Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
303          Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
304          Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
305          Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
306          Opc == Mips::J) ?
307         Opc : 0;
308}
309
310/// GetOppositeBranchOpc - Return the inverse of the specified
311/// opcode, e.g. turning BEQ to BNE.
312unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
313{
314  switch (Opc) {
315  default:           llvm_unreachable("Illegal opcode!");
316  case Mips::BEQ:    return Mips::BNE;
317  case Mips::BNE:    return Mips::BEQ;
318  case Mips::BGTZ:   return Mips::BLEZ;
319  case Mips::BGEZ:   return Mips::BLTZ;
320  case Mips::BLTZ:   return Mips::BGEZ;
321  case Mips::BLEZ:   return Mips::BGTZ;
322  case Mips::BEQ64:  return Mips::BNE64;
323  case Mips::BNE64:  return Mips::BEQ64;
324  case Mips::BGTZ64: return Mips::BLEZ64;
325  case Mips::BGEZ64: return Mips::BLTZ64;
326  case Mips::BLTZ64: return Mips::BGEZ64;
327  case Mips::BLEZ64: return Mips::BGTZ64;
328  case Mips::BC1T:   return Mips::BC1F;
329  case Mips::BC1F:   return Mips::BC1T;
330  }
331}
332
333static void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
334                          MachineBasicBlock *&BB,
335                          SmallVectorImpl<MachineOperand> &Cond) {
336  assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
337  int NumOp = Inst->getNumExplicitOperands();
338
339  // for both int and fp branches, the last explicit operand is the
340  // MBB.
341  BB = Inst->getOperand(NumOp-1).getMBB();
342  Cond.push_back(MachineOperand::CreateImm(Opc));
343
344  for (int i=0; i<NumOp-1; i++)
345    Cond.push_back(Inst->getOperand(i));
346}
347
348bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
349                                  MachineBasicBlock *&TBB,
350                                  MachineBasicBlock *&FBB,
351                                  SmallVectorImpl<MachineOperand> &Cond,
352                                  bool AllowModify) const
353{
354  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
355
356  // Skip all the debug instructions.
357  while (I != REnd && I->isDebugValue())
358    ++I;
359
360  if (I == REnd || !isUnpredicatedTerminator(&*I)) {
361    // If this block ends with no branches (it just falls through to its succ)
362    // just return false, leaving TBB/FBB null.
363    TBB = FBB = NULL;
364    return false;
365  }
366
367  MachineInstr *LastInst = &*I;
368  unsigned LastOpc = LastInst->getOpcode();
369
370  // Not an analyzable branch (must be an indirect jump).
371  if (!GetAnalyzableBrOpc(LastOpc))
372    return true;
373
374  // Get the second to last instruction in the block.
375  unsigned SecondLastOpc = 0;
376  MachineInstr *SecondLastInst = NULL;
377
378  if (++I != REnd) {
379    SecondLastInst = &*I;
380    SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
381
382    // Not an analyzable branch (must be an indirect jump).
383    if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
384      return true;
385  }
386
387  // If there is only one terminator instruction, process it.
388  if (!SecondLastOpc) {
389    // Unconditional branch
390    if (LastOpc == UncondBrOpc) {
391      TBB = LastInst->getOperand(0).getMBB();
392      return false;
393    }
394
395    // Conditional branch
396    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
397    return false;
398  }
399
400  // If we reached here, there are two branches.
401  // If there are three terminators, we don't know what sort of block this is.
402  if (++I != REnd && isUnpredicatedTerminator(&*I))
403    return true;
404
405  // If second to last instruction is an unconditional branch,
406  // analyze it and remove the last instruction.
407  if (SecondLastOpc == UncondBrOpc) {
408    // Return if the last instruction cannot be removed.
409    if (!AllowModify)
410      return true;
411
412    TBB = SecondLastInst->getOperand(0).getMBB();
413    LastInst->eraseFromParent();
414    return false;
415  }
416
417  // Conditional branch followed by an unconditional branch.
418  // The last one must be unconditional.
419  if (LastOpc != UncondBrOpc)
420    return true;
421
422  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
423  FBB = LastInst->getOperand(0).getMBB();
424
425  return false;
426}
427
428void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
429                                MachineBasicBlock *TBB, DebugLoc DL,
430                                const SmallVectorImpl<MachineOperand>& Cond)
431  const {
432  unsigned Opc = Cond[0].getImm();
433  const MCInstrDesc &MCID = get(Opc);
434  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
435
436  for (unsigned i = 1; i < Cond.size(); ++i)
437    MIB.addReg(Cond[i].getReg());
438
439  MIB.addMBB(TBB);
440}
441
442unsigned MipsInstrInfo::
443InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
444             MachineBasicBlock *FBB,
445             const SmallVectorImpl<MachineOperand> &Cond,
446             DebugLoc DL) const {
447  // Shouldn't be a fall through.
448  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
449
450  // # of condition operands:
451  //  Unconditional branches: 0
452  //  Floating point branches: 1 (opc)
453  //  Int BranchZero: 2 (opc, reg)
454  //  Int Branch: 3 (opc, reg0, reg1)
455  assert((Cond.size() <= 3) &&
456         "# of Mips branch conditions must be <= 3!");
457
458  // Two-way Conditional branch.
459  if (FBB) {
460    BuildCondBr(MBB, TBB, DL, Cond);
461    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
462    return 2;
463  }
464
465  // One way branch.
466  // Unconditional branch.
467  if (Cond.empty())
468    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
469  else // Conditional branch.
470    BuildCondBr(MBB, TBB, DL, Cond);
471  return 1;
472}
473
474unsigned MipsInstrInfo::
475RemoveBranch(MachineBasicBlock &MBB) const
476{
477  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
478  MachineBasicBlock::reverse_iterator FirstBr;
479  unsigned removed;
480
481  // Skip all the debug instructions.
482  while (I != REnd && I->isDebugValue())
483    ++I;
484
485  FirstBr = I;
486
487  // Up to 2 branches are removed.
488  // Note that indirect branches are not removed.
489  for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
490    if (!GetAnalyzableBrOpc(I->getOpcode()))
491      break;
492
493  MBB.erase(I.base(), FirstBr.base());
494
495  return removed;
496}
497
498/// ReverseBranchCondition - Return the inverse opcode of the
499/// specified Branch instruction.
500bool MipsInstrInfo::
501ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
502{
503  assert( (Cond.size() && Cond.size() <= 3) &&
504          "Invalid Mips branch condition!");
505  Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
506  return false;
507}
508
509/// Return the number of bytes of code the specified instruction may be.
510unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
511  switch (MI->getOpcode()) {
512  default:
513    return MI->getDesc().getSize();
514  case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
515    const MachineFunction *MF = MI->getParent()->getParent();
516    const char *AsmStr = MI->getOperand(0).getSymbolName();
517    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
518  }
519  }
520}
521
522unsigned
523llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
524                          MachineBasicBlock& MBB,
525                          MachineBasicBlock::iterator II, DebugLoc DL,
526                          bool LastInstrIsADDiu,
527                          MipsAnalyzeImmediate::Inst *LastInst) {
528  MipsAnalyzeImmediate AnalyzeImm;
529  unsigned Size = IsN64 ? 64 : 32;
530  unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
531  unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
532  unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
533
534  const MipsAnalyzeImmediate::InstSeq &Seq =
535    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
536  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
537
538  if (LastInst && (Seq.size() == 1)) {
539    *LastInst = *Inst;
540    return 0;
541  }
542
543  // The first instruction can be a LUi, which is different from other
544  // instructions (ADDiu, ORI and SLL) in that it does not have a register
545  // operand.
546  if (Inst->Opc == LUi)
547    BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
548      .addImm(SignExtend64<16>(Inst->ImmOpnd));
549  else
550    BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
551      .addImm(SignExtend64<16>(Inst->ImmOpnd));
552
553  // Build the remaining instructions in Seq. Skip the last instruction if
554  // LastInst is not 0.
555  for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
556    BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
557      .addImm(SignExtend64<16>(Inst->ImmOpnd));
558
559  if (LastInst)
560    *LastInst = *Inst;
561
562  return Seq.size() - !!LastInst;
563}
564