MipsInstrInfo.cpp revision d04a8d4b33ff316ca4cf961e06c9e312eff8e64f 
1//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsInstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/TargetRegistry.h"
24
25#define GET_INSTRINFO_CTOR
26#include "MipsGenInstrInfo.inc"
27
28using namespace llvm;
29
30MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
31  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32    TM(tm), UncondBrOpc(UncondBr) {}
33
34const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) {
35  if (TM.getSubtargetImpl()->inMips16Mode())
36    return llvm::createMips16InstrInfo(TM);
37
38  return llvm::createMipsSEInstrInfo(TM);
39}
40
41bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
42  return op.isImm() && op.getImm() == 0;
43}
44
45/// insertNoop - If data hazard condition is found insert the target nop
46/// instruction.
47void MipsInstrInfo::
48insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
49{
50  DebugLoc DL;
51  BuildMI(MBB, MI, DL, get(Mips::NOP));
52}
53
54MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
55                                                unsigned Flag) const {
56  MachineFunction &MF = *MBB.getParent();
57  MachineFrameInfo &MFI = *MF.getFrameInfo();
58  unsigned Align = MFI.getObjectAlignment(FI);
59
60  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
61                                 MFI.getObjectSize(FI), Align);
62}
63
64MachineInstr*
65MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
66                                        uint64_t Offset, const MDNode *MDPtr,
67                                        DebugLoc DL) const {
68  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
69    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
70  return &*MIB;
71}
72
73//===----------------------------------------------------------------------===//
74// Branch Analysis
75//===----------------------------------------------------------------------===//
76
77void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
78                                  MachineBasicBlock *&BB,
79                                  SmallVectorImpl<MachineOperand> &Cond) const {
80  assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
81  int NumOp = Inst->getNumExplicitOperands();
82
83  // for both int and fp branches, the last explicit operand is the
84  // MBB.
85  BB = Inst->getOperand(NumOp-1).getMBB();
86  Cond.push_back(MachineOperand::CreateImm(Opc));
87
88  for (int i=0; i<NumOp-1; i++)
89    Cond.push_back(Inst->getOperand(i));
90}
91
92bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
93                                  MachineBasicBlock *&TBB,
94                                  MachineBasicBlock *&FBB,
95                                  SmallVectorImpl<MachineOperand> &Cond,
96                                  bool AllowModify) const
97{
98
99  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
100
101  // Skip all the debug instructions.
102  while (I != REnd && I->isDebugValue())
103    ++I;
104
105  if (I == REnd || !isUnpredicatedTerminator(&*I)) {
106    // If this block ends with no branches (it just falls through to its succ)
107    // just return false, leaving TBB/FBB null.
108    TBB = FBB = NULL;
109    return false;
110  }
111
112  MachineInstr *LastInst = &*I;
113  unsigned LastOpc = LastInst->getOpcode();
114
115  // Not an analyzable branch (must be an indirect jump).
116  if (!GetAnalyzableBrOpc(LastOpc))
117    return true;
118
119  // Get the second to last instruction in the block.
120  unsigned SecondLastOpc = 0;
121  MachineInstr *SecondLastInst = NULL;
122
123  if (++I != REnd) {
124    SecondLastInst = &*I;
125    SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
126
127    // Not an analyzable branch (must be an indirect jump).
128    if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
129      return true;
130  }
131
132  // If there is only one terminator instruction, process it.
133  if (!SecondLastOpc) {
134    // Unconditional branch
135    if (LastOpc == UncondBrOpc) {
136      TBB = LastInst->getOperand(0).getMBB();
137      return false;
138    }
139
140    // Conditional branch
141    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
142    return false;
143  }
144
145  // If we reached here, there are two branches.
146  // If there are three terminators, we don't know what sort of block this is.
147  if (++I != REnd && isUnpredicatedTerminator(&*I))
148    return true;
149
150  // If second to last instruction is an unconditional branch,
151  // analyze it and remove the last instruction.
152  if (SecondLastOpc == UncondBrOpc) {
153    // Return if the last instruction cannot be removed.
154    if (!AllowModify)
155      return true;
156
157    TBB = SecondLastInst->getOperand(0).getMBB();
158    LastInst->eraseFromParent();
159    return false;
160  }
161
162  // Conditional branch followed by an unconditional branch.
163  // The last one must be unconditional.
164  if (LastOpc != UncondBrOpc)
165    return true;
166
167  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
168  FBB = LastInst->getOperand(0).getMBB();
169
170  return false;
171}
172
173void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
174                                MachineBasicBlock *TBB, DebugLoc DL,
175                                const SmallVectorImpl<MachineOperand>& Cond)
176  const {
177  unsigned Opc = Cond[0].getImm();
178  const MCInstrDesc &MCID = get(Opc);
179  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
180
181  for (unsigned i = 1; i < Cond.size(); ++i) {
182    if (Cond[i].isReg())
183      MIB.addReg(Cond[i].getReg());
184    else if (Cond[i].isImm())
185      MIB.addImm(Cond[i].getImm());
186    else
187       assert(true && "Cannot copy operand");
188  }
189  MIB.addMBB(TBB);
190}
191
192unsigned MipsInstrInfo::
193InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
194             MachineBasicBlock *FBB,
195             const SmallVectorImpl<MachineOperand> &Cond,
196             DebugLoc DL) const {
197  // Shouldn't be a fall through.
198  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
199
200  // # of condition operands:
201  //  Unconditional branches: 0
202  //  Floating point branches: 1 (opc)
203  //  Int BranchZero: 2 (opc, reg)
204  //  Int Branch: 3 (opc, reg0, reg1)
205  assert((Cond.size() <= 3) &&
206         "# of Mips branch conditions must be <= 3!");
207
208  // Two-way Conditional branch.
209  if (FBB) {
210    BuildCondBr(MBB, TBB, DL, Cond);
211    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
212    return 2;
213  }
214
215  // One way branch.
216  // Unconditional branch.
217  if (Cond.empty())
218    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
219  else // Conditional branch.
220    BuildCondBr(MBB, TBB, DL, Cond);
221  return 1;
222}
223
224unsigned MipsInstrInfo::
225RemoveBranch(MachineBasicBlock &MBB) const
226{
227  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
228  MachineBasicBlock::reverse_iterator FirstBr;
229  unsigned removed;
230
231  // Skip all the debug instructions.
232  while (I != REnd && I->isDebugValue())
233    ++I;
234
235  FirstBr = I;
236
237  // Up to 2 branches are removed.
238  // Note that indirect branches are not removed.
239  for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
240    if (!GetAnalyzableBrOpc(I->getOpcode()))
241      break;
242
243  MBB.erase(I.base(), FirstBr.base());
244
245  return removed;
246}
247
248/// ReverseBranchCondition - Return the inverse opcode of the
249/// specified Branch instruction.
250bool MipsInstrInfo::
251ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
252{
253  assert( (Cond.size() && Cond.size() <= 3) &&
254          "Invalid Mips branch condition!");
255  Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
256  return false;
257}
258
259/// Return the number of bytes of code the specified instruction may be.
260unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
261  switch (MI->getOpcode()) {
262  default:
263    return MI->getDesc().getSize();
264  case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
265    const MachineFunction *MF = MI->getParent()->getParent();
266    const char *AsmStr = MI->getOperand(0).getSymbolName();
267    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
268  }
269  }
270}
271