MipsInstrInfo.cpp revision d0a4b60df146b8c51555a752fed1530999ecbe64 
1//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsInstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/TargetRegistry.h"
24
25#define GET_INSTRINFO_CTOR
26#include "MipsGenInstrInfo.inc"
27
28using namespace llvm;
29
30MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
31  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32    TM(tm), UncondBrOpc(UncondBr) {}
33
34const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) {
35  if (TM.getSubtargetImpl()->inMips16Mode())
36    return llvm::createMips16InstrInfo(TM);
37
38  return llvm::createMipsSEInstrInfo(TM);
39}
40
41bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
42  return op.isImm() && op.getImm() == 0;
43}
44
45/// insertNoop - If data hazard condition is found insert the target nop
46/// instruction.
47void MipsInstrInfo::
48insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
49{
50  DebugLoc DL;
51  BuildMI(MBB, MI, DL, get(Mips::NOP));
52}
53
54MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
55                                                unsigned Flag) const {
56  MachineFunction &MF = *MBB.getParent();
57  MachineFrameInfo &MFI = *MF.getFrameInfo();
58  unsigned Align = MFI.getObjectAlignment(FI);
59
60  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
61                                 MFI.getObjectSize(FI), Align);
62}
63
64MachineInstr*
65MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
66                                        uint64_t Offset, const MDNode *MDPtr,
67                                        DebugLoc DL) const {
68  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
69    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
70  return &*MIB;
71}
72
73//===----------------------------------------------------------------------===//
74// Branch Analysis
75//===----------------------------------------------------------------------===//
76
77void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
78                                  MachineBasicBlock *&BB,
79                                  SmallVectorImpl<MachineOperand> &Cond) const {
80  assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
81  int NumOp = Inst->getNumExplicitOperands();
82
83  // for both int and fp branches, the last explicit operand is the
84  // MBB.
85  BB = Inst->getOperand(NumOp-1).getMBB();
86  Cond.push_back(MachineOperand::CreateImm(Opc));
87
88  for (int i=0; i<NumOp-1; i++)
89    Cond.push_back(Inst->getOperand(i));
90}
91
92bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
93                                  MachineBasicBlock *&TBB,
94                                  MachineBasicBlock *&FBB,
95                                  SmallVectorImpl<MachineOperand> &Cond,
96                                  bool AllowModify) const {
97  SmallVector<MachineInstr*, 2> BranchInstrs;
98  BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
99
100  return (BT == BT_None) || (BT == BT_Indirect);
101}
102
103void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
104                                MachineBasicBlock *TBB, DebugLoc DL,
105                                const SmallVectorImpl<MachineOperand>& Cond)
106  const {
107  unsigned Opc = Cond[0].getImm();
108  const MCInstrDesc &MCID = get(Opc);
109  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
110
111  for (unsigned i = 1; i < Cond.size(); ++i) {
112    if (Cond[i].isReg())
113      MIB.addReg(Cond[i].getReg());
114    else if (Cond[i].isImm())
115      MIB.addImm(Cond[i].getImm());
116    else
117       assert(true && "Cannot copy operand");
118  }
119  MIB.addMBB(TBB);
120}
121
122unsigned MipsInstrInfo::
123InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
124             MachineBasicBlock *FBB,
125             const SmallVectorImpl<MachineOperand> &Cond,
126             DebugLoc DL) const {
127  // Shouldn't be a fall through.
128  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
129
130  // # of condition operands:
131  //  Unconditional branches: 0
132  //  Floating point branches: 1 (opc)
133  //  Int BranchZero: 2 (opc, reg)
134  //  Int Branch: 3 (opc, reg0, reg1)
135  assert((Cond.size() <= 3) &&
136         "# of Mips branch conditions must be <= 3!");
137
138  // Two-way Conditional branch.
139  if (FBB) {
140    BuildCondBr(MBB, TBB, DL, Cond);
141    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
142    return 2;
143  }
144
145  // One way branch.
146  // Unconditional branch.
147  if (Cond.empty())
148    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
149  else // Conditional branch.
150    BuildCondBr(MBB, TBB, DL, Cond);
151  return 1;
152}
153
154unsigned MipsInstrInfo::
155RemoveBranch(MachineBasicBlock &MBB) const
156{
157  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
158  MachineBasicBlock::reverse_iterator FirstBr;
159  unsigned removed;
160
161  // Skip all the debug instructions.
162  while (I != REnd && I->isDebugValue())
163    ++I;
164
165  FirstBr = I;
166
167  // Up to 2 branches are removed.
168  // Note that indirect branches are not removed.
169  for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
170    if (!GetAnalyzableBrOpc(I->getOpcode()))
171      break;
172
173  MBB.erase(I.base(), FirstBr.base());
174
175  return removed;
176}
177
178/// ReverseBranchCondition - Return the inverse opcode of the
179/// specified Branch instruction.
180bool MipsInstrInfo::
181ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
182{
183  assert( (Cond.size() && Cond.size() <= 3) &&
184          "Invalid Mips branch condition!");
185  Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
186  return false;
187}
188
189MipsInstrInfo::BranchType MipsInstrInfo::
190AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
191              MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond,
192              bool AllowModify,
193              SmallVectorImpl<MachineInstr*> &BranchInstrs) const {
194
195  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
196
197  // Skip all the debug instructions.
198  while (I != REnd && I->isDebugValue())
199    ++I;
200
201  if (I == REnd || !isUnpredicatedTerminator(&*I)) {
202    // This block ends with no branches (it just falls through to its succ).
203    // Leave TBB/FBB null.
204    TBB = FBB = NULL;
205    return BT_NoBranch;
206  }
207
208  MachineInstr *LastInst = &*I;
209  unsigned LastOpc = LastInst->getOpcode();
210  BranchInstrs.push_back(LastInst);
211
212  // Not an analyzable branch (e.g., indirect jump).
213  if (!GetAnalyzableBrOpc(LastOpc))
214    return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
215
216  // Get the second to last instruction in the block.
217  unsigned SecondLastOpc = 0;
218  MachineInstr *SecondLastInst = NULL;
219
220  if (++I != REnd) {
221    SecondLastInst = &*I;
222    SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
223
224    // Not an analyzable branch (must be an indirect jump).
225    if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
226      return BT_None;
227  }
228
229  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
230
231  // If there is only one terminator instruction, process it.
232  if (!SecondLastOpc) {
233    // Unconditional branch
234    if (LastOpc == UncondBrOpc) {
235      TBB = LastInst->getOperand(0).getMBB();
236      return BT_Uncond;
237    }
238
239    // Conditional branch
240    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
241    return BT_Cond;
242  }
243
244  // If we reached here, there are two branches.
245  // If there are three terminators, we don't know what sort of block this is.
246  if (++I != REnd && isUnpredicatedTerminator(&*I))
247    return BT_None;
248
249  // If second to last instruction is an unconditional branch,
250  // analyze it and remove the last instruction.
251  if (SecondLastOpc == UncondBrOpc) {
252    // Return if the last instruction cannot be removed.
253    if (!AllowModify)
254      return BT_None;
255
256    TBB = SecondLastInst->getOperand(0).getMBB();
257    LastInst->eraseFromParent();
258    BranchInstrs.pop_back();
259    return BT_Uncond;
260  }
261
262  // Conditional branch followed by an unconditional branch.
263  // The last one must be unconditional.
264  if (LastOpc != UncondBrOpc)
265    return BT_None;
266
267  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
268  FBB = LastInst->getOperand(0).getMBB();
269
270  return BT_CondUncond;
271}
272
273/// Return the number of bytes of code the specified instruction may be.
274unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
275  switch (MI->getOpcode()) {
276  default:
277    return MI->getDesc().getSize();
278  case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
279    const MachineFunction *MF = MI->getParent()->getParent();
280    const char *AsmStr = MI->getOperand(0).getSymbolName();
281    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
282  }
283  }
284}
285