1bb481f882093fb738d2bb15610c79364bada5496Jia Liu//===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===// 2972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes// 3972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes// The LLVM Compiler Infrastructure 4972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes// 84552c9a3b34ad9b2085635266348d0d9b95514a6Akira Hatanaka//===----------------------------------------------------------------------===// 9972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes// 10972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes// This file contains the Mips implementation of the TargetInstrInfo class. 11972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes// 12dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in 13dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// order for MipsLongBranch pass to work correctly when the code has inline 14dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// assembly. The returned value doesn't have to be the asm instruction's exact 15dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// size in bytes; MipsLongBranch only expects it to be the correct upper bound. 164552c9a3b34ad9b2085635266348d0d9b95514a6Akira Hatanaka//===----------------------------------------------------------------------===// 17972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes 18972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes#ifndef MIPSINSTRUCTIONINFO_H 19972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes#define MIPSINSTRUCTIONINFO_H 20972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes 21972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes#include "Mips.h" 22d4b48b283c3939962f0cd3c17aedc40209d82b1aAkira Hatanaka#include "MipsAnalyzeImmediate.h" 2379aa3417eb6f58d668aadfedf075240a41d35a26Craig Topper#include "MipsRegisterInfo.h" 24151687cb8c4fc65fefcd8964a0c3d77680e90a5cAkira Hatanaka#include "llvm/CodeGen/MachineInstrBuilder.h" 25c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 26972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes#include "llvm/Target/TargetInstrInfo.h" 27972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes 284db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_HEADER 294db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#include "MipsGenInstrInfo.inc" 304db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng 31972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopesnamespace llvm { 32972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes 334db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Chengclass MipsInstrInfo : public MipsGenInstrInfo { 34354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka virtual void anchor(); 350bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakaprotected: 36972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes MipsTargetMachine &TM; 376e55ff56b88c3334d5847f2cb26f3001b92c489bAkira Hatanaka unsigned UncondBrOpc; 38972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes 390bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakapublic: 40d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka enum BranchType { 41d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka BT_None, // Couldn't analyze branch. 42d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka BT_NoBranch, // No branches found. 43d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka BT_Uncond, // One unconditional branch. 44d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka BT_Cond, // One conditional branch. 45d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka BT_CondUncond, // A conditional branch followed by an unconditional branch. 46d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka BT_Indirect // One indirct branch. 47d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka }; 48d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka 490bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc); 5081092dc20abe5253a5b4d48a75997baa84dde196Bruno Cardoso Lopes 51af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanaka static const MipsInstrInfo *create(MipsTargetMachine &TM); 52af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanaka 530b2cd89a397b54d318f53848b7b4f9292b09b752Bruno Cardoso Lopes /// Branch Analysis 54dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 55dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock *&FBB, 56dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines SmallVectorImpl<MachineOperand> &Cond, 57dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool AllowModify) const override; 5820ada98de82cb23c3f075acbb09436760ef0923cAkira Hatanaka 59dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 6020ada98de82cb23c3f075acbb09436760ef0923cAkira Hatanaka 61dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 62dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock *FBB, 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const SmallVectorImpl<MachineOperand> &Cond, 64dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DebugLoc DL) const override; 650bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 66dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool 67dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 68564f69072c4569e2d603c335a6ddc61adf94ebb2Akira Hatanaka 69d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 70d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka MachineBasicBlock *&FBB, 71d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka SmallVectorImpl<MachineOperand> &Cond, 72d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka bool AllowModify, 73d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka SmallVectorImpl<MachineInstr*> &BranchInstrs) const; 74d0a4b60df146b8c51555a752fed1530999ecbe64Akira Hatanaka 750b2cd89a397b54d318f53848b7b4f9292b09b752Bruno Cardoso Lopes /// Insert nop instruction when hazard condition is found 76dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines void insertNoop(MachineBasicBlock &MBB, 77dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator MI) const override; 78d4b48b283c3939962f0cd3c17aedc40209d82b1aAkira Hatanaka 790bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 800bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka /// such, whenever a client has an instance of instruction info, it should 810bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka /// always be able to get register info as well (through this method). 820bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka /// 838589010e3d1d5a902992a5039cffa9d4116982c5Akira Hatanaka virtual const MipsRegisterInfo &getRegisterInfo() const = 0; 840bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 856daba286836e6fb2351e7ebc248e18a5c80e8a31Akira Hatanaka virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; 860bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 87d4b48b283c3939962f0cd3c17aedc40209d82b1aAkira Hatanaka /// Return the number of bytes of code the specified instruction may be. 88d4b48b283c3939962f0cd3c17aedc40209d82b1aAkira Hatanaka unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 890bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 90dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines void storeRegToStackSlot(MachineBasicBlock &MBB, 91dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator MBBI, 92dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned SrcReg, bool isKill, int FrameIndex, 93dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *RC, 94dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterInfo *TRI) const override { 95c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); 96c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka } 97c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka 98dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines void loadRegFromStackSlot(MachineBasicBlock &MBB, 99dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator MBBI, 100dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned DestReg, int FrameIndex, 101dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *RC, 102dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterInfo *TRI) const override { 103c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); 104c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka } 105c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka 106c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka virtual void storeRegToStack(MachineBasicBlock &MBB, 107c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka MachineBasicBlock::iterator MI, 108c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka unsigned SrcReg, bool isKill, int FrameIndex, 109c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka const TargetRegisterClass *RC, 110c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka const TargetRegisterInfo *TRI, 111c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka int64_t Offset) const = 0; 112c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka 113c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka virtual void loadRegFromStack(MachineBasicBlock &MBB, 114c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka MachineBasicBlock::iterator MI, 115c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka unsigned DestReg, int FrameIndex, 116c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka const TargetRegisterClass *RC, 117c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka const TargetRegisterInfo *TRI, 118c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka int64_t Offset) const = 0; 119c713e996d305df99cc7fc58c9d8dc1f5fa00518dAkira Hatanaka 120151687cb8c4fc65fefcd8964a0c3d77680e90a5cAkira Hatanaka /// Create an instruction which has the same operands and memory operands 121151687cb8c4fc65fefcd8964a0c3d77680e90a5cAkira Hatanaka /// as MI but has a new opcode. 122151687cb8c4fc65fefcd8964a0c3d77680e90a5cAkira Hatanaka MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, 123151687cb8c4fc65fefcd8964a0c3d77680e90a5cAkira Hatanaka MachineBasicBlock::iterator I) const; 124151687cb8c4fc65fefcd8964a0c3d77680e90a5cAkira Hatanaka 1250bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakaprotected: 1260bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka bool isZeroImm(const MachineOperand &op) const; 1270bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1280bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, 1290bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka unsigned Flag) const; 1300bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1310bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakaprivate: 1326daba286836e6fb2351e7ebc248e18a5c80e8a31Akira Hatanaka virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; 1330bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1340bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 1350bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MachineBasicBlock *&BB, 1360bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka SmallVectorImpl<MachineOperand> &Cond) const; 1370bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1380bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL, 1390bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka const SmallVectorImpl<MachineOperand>& Cond) const; 140972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes}; 141972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes 142af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanaka/// Create MipsInstrInfo objects. 143af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanakaconst MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM); 144af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanakaconst MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM); 145af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanaka 146972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes} 147972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes 148972f5896e417d8e81cf400083fab15a37b6d4277Bruno Cardoso Lopes#endif 149