MipsInstrInfo.h revision 182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2
1//===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef MIPSINSTRUCTIONINFO_H 15#define MIPSINSTRUCTIONINFO_H 16 17#include "Mips.h" 18#include "MipsAnalyzeImmediate.h" 19#include "MipsRegisterInfo.h" 20#include "llvm/Support/ErrorHandling.h" 21#include "llvm/Target/TargetInstrInfo.h" 22 23#define GET_INSTRINFO_HEADER 24#include "MipsGenInstrInfo.inc" 25 26namespace llvm { 27 28class MipsInstrInfo : public MipsGenInstrInfo { 29 MipsTargetMachine &TM; 30 bool IsN64; 31 const MipsRegisterInfo RI; 32 unsigned UncondBrOpc; 33public: 34 explicit MipsInstrInfo(MipsTargetMachine &TM); 35 36 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 37 /// such, whenever a client has an instance of instruction info, it should 38 /// always be able to get register info as well (through this method). 39 /// 40 virtual const MipsRegisterInfo &getRegisterInfo() const; 41 42 /// isLoadFromStackSlot - If the specified machine instruction is a direct 43 /// load from a stack slot, return the virtual or physical register number of 44 /// the destination along with the FrameIndex of the loaded stack slot. If 45 /// not, return 0. This predicate must return 0 if the instruction has 46 /// any side effects other than loading from the stack slot. 47 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 48 int &FrameIndex) const; 49 50 /// isStoreToStackSlot - If the specified machine instruction is a direct 51 /// store to a stack slot, return the virtual or physical register number of 52 /// the source reg along with the FrameIndex of the loaded stack slot. If 53 /// not, return 0. This predicate must return 0 if the instruction has 54 /// any side effects other than storing to the stack slot. 55 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 56 int &FrameIndex) const; 57 58 /// Branch Analysis 59 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 60 MachineBasicBlock *&FBB, 61 SmallVectorImpl<MachineOperand> &Cond, 62 bool AllowModify) const; 63 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 64 65private: 66 void ExpandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 67 unsigned Opc) const; 68 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL, 69 const SmallVectorImpl<MachineOperand>& Cond) const; 70 void ExpandExtractElementF64(MachineBasicBlock &MBB, 71 MachineBasicBlock::iterator I) const; 72 void ExpandBuildPairF64(MachineBasicBlock &MBB, 73 MachineBasicBlock::iterator I) const; 74 75public: 76 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 77 MachineBasicBlock *FBB, 78 const SmallVectorImpl<MachineOperand> &Cond, 79 DebugLoc DL) const; 80 virtual void copyPhysReg(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator MI, DebugLoc DL, 82 unsigned DestReg, unsigned SrcReg, 83 bool KillSrc) const; 84 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 85 MachineBasicBlock::iterator MBBI, 86 unsigned SrcReg, bool isKill, int FrameIndex, 87 const TargetRegisterClass *RC, 88 const TargetRegisterInfo *TRI) const; 89 90 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 91 MachineBasicBlock::iterator MBBI, 92 unsigned DestReg, int FrameIndex, 93 const TargetRegisterClass *RC, 94 const TargetRegisterInfo *TRI) const; 95 96 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 97 98 virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF, 99 int FrameIx, uint64_t Offset, 100 const MDNode *MDPtr, 101 DebugLoc DL) const; 102 103 virtual 104 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 105 106 /// Insert nop instruction when hazard condition is found 107 virtual void insertNoop(MachineBasicBlock &MBB, 108 MachineBasicBlock::iterator MI) const; 109 110 /// Return the number of bytes of code the specified instruction may be. 111 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 112}; 113 114namespace Mips { 115 /// GetOppositeBranchOpc - Return the inverse of the specified 116 /// opcode, e.g. turning BEQ to BNE. 117 unsigned GetOppositeBranchOpc(unsigned Opc); 118 119 /// Emit a series of instructions to load an immediate. All instructions 120 /// except for the last one are emitted. The function returns the number of 121 /// MachineInstrs generated. The opcode-immediate pair of the last 122 /// instruction is returned in LastInst, if it is not 0. 123 unsigned 124 loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII, 125 MachineBasicBlock& MBB, MachineBasicBlock::iterator II, 126 DebugLoc DL, bool LastInstrIsADDiu, 127 MipsAnalyzeImmediate::Inst *LastInst); 128} 129 130} 131 132#endif 133