1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 27def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 29def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 34def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 35 36def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 37 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Tail call 56def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 58 59// Hi and Lo nodes are used to handle global addresses. Used on 60// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 61// static model. (nothing to do with Mips Registers Hi and Lo) 62def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 63def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 64def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 65 66// TlsGd node is used to handle General Dynamic TLS 67def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 68 69// TprelHi and TprelLo nodes are used to handle Local Exec TLS 70def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 71def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 72 73// Thread pointer 74def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 75 76// Return 77def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 79 80// These are target-independent nodes, but have target-specific formats. 81def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 83def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 84 [SDNPHasChain, SDNPSideEffect, 85 SDNPOptInGlue, SDNPOutGlue]>; 86 87// Nodes used to extract LO/HI registers. 88def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 89def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 90 91// Node used to insert 32-bit integers to LOHI register pair. 92def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 93 94// Mult nodes. 95def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 97 98// MAdd*/MSub* nodes 99def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 101def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 103 104// DivRem(u) nodes 105def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 106def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 107def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 108 [SDNPOutGlue]>; 109def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 110 [SDNPOutGlue]>; 111 112// Target constant nodes that are not part of any isel patterns and remain 113// unchanged can cause instructions with illegal operands to be emitted. 114// Wrapper node patterns give the instruction selector a chance to replace 115// target constant nodes that would otherwise remain unchanged with ADDiu 116// nodes. Without these wrapper node patterns, the following conditional move 117// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 118// compiled: 119// movn %got(d)($gp), %got(c)($gp), $4 120// This instruction is illegal since movn can take only register operands. 121 122def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 123 124def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 125 126def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 127def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 128 129def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 131def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 133def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 135def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 137def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 139def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 141def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 143def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 145 146//===----------------------------------------------------------------------===// 147// Mips Instruction Predicate Definitions. 148//===----------------------------------------------------------------------===// 149def HasMips2 : Predicate<"Subtarget->hasMips2()">, 150 AssemblerPredicate<"FeatureMips2">; 151def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">, 152 AssemblerPredicate<"FeatureMips3_32">; 153def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">, 154 AssemblerPredicate<"FeatureMips3_32r2">; 155def HasMips3 : Predicate<"Subtarget->hasMips3()">, 156 AssemblerPredicate<"FeatureMips3">; 157def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">, 158 AssemblerPredicate<"FeatureMips4_32">; 159def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">, 160 AssemblerPredicate<"FeatureMips4_32r2">; 161def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">, 162 AssemblerPredicate<"FeatureMips5_32r2">; 163def HasMips32 : Predicate<"Subtarget->hasMips32()">, 164 AssemblerPredicate<"FeatureMips32">; 165def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">, 166 AssemblerPredicate<"FeatureMips32r2">; 167def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">, 168 AssemblerPredicate<"FeatureMips32r6">; 169def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">, 170 AssemblerPredicate<"!FeatureMips32r6">; 171def IsGP64bit : Predicate<"Subtarget->isGP64bit()">, 172 AssemblerPredicate<"FeatureGP64Bit">; 173def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">, 174 AssemblerPredicate<"!FeatureGP64Bit">; 175def HasMips64 : Predicate<"Subtarget->hasMips64()">, 176 AssemblerPredicate<"FeatureMips64">; 177def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">, 178 AssemblerPredicate<"FeatureMips64r2">; 179def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">, 180 AssemblerPredicate<"FeatureMips64r6">; 181def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">, 182 AssemblerPredicate<"!FeatureMips64r6">; 183def IsN64 : Predicate<"Subtarget->isABI_N64()">, 184 AssemblerPredicate<"FeatureN64">; 185def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, 186 AssemblerPredicate<"FeatureMips16">; 187def HasCnMips : Predicate<"Subtarget->hasCnMips()">, 188 AssemblerPredicate<"FeatureCnMips">; 189def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 190 AssemblerPredicate<"FeatureMips32">; 191def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 192 AssemblerPredicate<"FeatureMips32">; 193def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 194def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">, 195 AssemblerPredicate<"!FeatureMips16">; 196def NotDSP : Predicate<"!Subtarget->hasDSP()">; 197def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">, 198 AssemblerPredicate<"FeatureMicroMips">; 199def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">, 200 AssemblerPredicate<"!FeatureMicroMips">; 201def IsLE : Predicate<"Subtarget->isLittle()">; 202def IsBE : Predicate<"!Subtarget->isLittle()">; 203def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 204 205//===----------------------------------------------------------------------===// 206// Mips GPR size adjectives. 207// They are mutually exclusive. 208//===----------------------------------------------------------------------===// 209 210class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; } 211class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; } 212 213//===----------------------------------------------------------------------===// 214// Mips ISA/ASE membership and instruction group membership adjectives. 215// They are mutually exclusive. 216//===----------------------------------------------------------------------===// 217 218// FIXME: I'd prefer to use additive predicates to build the instruction sets 219// but we are short on assembler feature bits at the moment. Using a 220// subtractive predicate will hopefully keep us under the 32 predicate 221// limit long enough to develop an alternative way to handle P1||P2 222// predicates. 223class ISA_MIPS1_NOT_32R6_64R6 { 224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6]; 225} 226class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; } 227class ISA_MIPS2_NOT_32R6_64R6 { 228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6]; 229} 230class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; } 231class ISA_MIPS3_NOT_32R6_64R6 { 232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6]; 233} 234class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; } 235class ISA_MIPS32_NOT_32R6_64R6 { 236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6]; 237} 238class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; } 239class ISA_MIPS32R2_NOT_32R6_64R6 { 240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6]; 241} 242class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; } 243class ISA_MIPS64_NOT_64R6 { 244 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6]; 245} 246class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; } 247class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; } 248class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; } 249 250// The portions of MIPS-III that were also added to MIPS32 251class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; } 252 253// The portions of MIPS-III that were also added to MIPS32 but were removed in 254// MIPS32r6 and MIPS64r6. 255class INSN_MIPS3_32_NOT_32R6_64R6 { 256 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6]; 257} 258 259// The portions of MIPS-III that were also added to MIPS32 260class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; } 261 262// The portions of MIPS-IV that were also added to MIPS32 but were removed in 263// MIPS32r6 and MIPS64r6. 264class INSN_MIPS4_32_NOT_32R6_64R6 { 265 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6]; 266} 267 268// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in 269// MIPS32r6 and MIPS64r6. 270class INSN_MIPS4_32R2_NOT_32R6_64R6 { 271 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6]; 272} 273 274// The portions of MIPS-V that were also added to MIPS32r2 but were removed in 275// MIPS32r6 and MIPS64r6. 276class INSN_MIPS5_32R2_NOT_32R6_64R6 { 277 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6]; 278} 279 280//===----------------------------------------------------------------------===// 281 282class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl { 283 let EncodingPredicates = [HasStdEnc]; 284} 285 286class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> : 287 InstAlias<Asm, Result, Emit>, PredicateControl; 288 289class IsCommutable { 290 bit isCommutable = 1; 291} 292 293class IsBranch { 294 bit isBranch = 1; 295} 296 297class IsReturn { 298 bit isReturn = 1; 299} 300 301class IsCall { 302 bit isCall = 1; 303} 304 305class IsTailCall { 306 bit isCall = 1; 307 bit isTerminator = 1; 308 bit isReturn = 1; 309 bit isBarrier = 1; 310 bit hasExtraSrcRegAllocReq = 1; 311 bit isCodeGenOnly = 1; 312} 313 314class IsAsCheapAsAMove { 315 bit isAsCheapAsAMove = 1; 316} 317 318class NeverHasSideEffects { 319 bit neverHasSideEffects = 1; 320} 321 322//===----------------------------------------------------------------------===// 323// Instruction format superclass 324//===----------------------------------------------------------------------===// 325 326include "MipsInstrFormats.td" 327 328//===----------------------------------------------------------------------===// 329// Mips Operand, Complex Patterns and Transformations Definitions. 330//===----------------------------------------------------------------------===// 331 332def MipsJumpTargetAsmOperand : AsmOperandClass { 333 let Name = "JumpTarget"; 334 let ParserMethod = "ParseJumpTarget"; 335 let PredicateMethod = "isImm"; 336 let RenderMethod = "addImmOperands"; 337} 338 339// Instruction operand types 340def jmptarget : Operand<OtherVT> { 341 let EncoderMethod = "getJumpTargetOpValue"; 342 let ParserMatchClass = MipsJumpTargetAsmOperand; 343} 344def brtarget : Operand<OtherVT> { 345 let EncoderMethod = "getBranchTargetOpValue"; 346 let OperandType = "OPERAND_PCREL"; 347 let DecoderMethod = "DecodeBranchTarget"; 348 let ParserMatchClass = MipsJumpTargetAsmOperand; 349} 350def calltarget : Operand<iPTR> { 351 let EncoderMethod = "getJumpTargetOpValue"; 352 let ParserMatchClass = MipsJumpTargetAsmOperand; 353} 354 355def simm9 : Operand<i32>; 356def simm10 : Operand<i32>; 357def simm11 : Operand<i32>; 358 359def simm16 : Operand<i32> { 360 let DecoderMethod= "DecodeSimm16"; 361} 362 363def simm19_lsl2 : Operand<i32> { 364 let EncoderMethod = "getSimm19Lsl2Encoding"; 365 let DecoderMethod = "DecodeSimm19Lsl2"; 366 let ParserMatchClass = MipsJumpTargetAsmOperand; 367} 368 369def simm18_lsl3 : Operand<i32> { 370 let EncoderMethod = "getSimm18Lsl3Encoding"; 371 let DecoderMethod = "DecodeSimm18Lsl3"; 372 let ParserMatchClass = MipsJumpTargetAsmOperand; 373} 374 375def simm20 : Operand<i32> { 376} 377 378def uimm20 : Operand<i32> { 379} 380 381def uimm10 : Operand<i32> { 382} 383 384def simm16_64 : Operand<i64> { 385 let DecoderMethod = "DecodeSimm16"; 386} 387 388// Zero 389def uimmz : Operand<i32> { 390 let PrintMethod = "printUnsignedImm"; 391} 392 393// Unsigned Operand 394def uimm2 : Operand<i32> { 395 let PrintMethod = "printUnsignedImm"; 396} 397 398def uimm3 : Operand<i32> { 399 let PrintMethod = "printUnsignedImm"; 400} 401 402def uimm5 : Operand<i32> { 403 let PrintMethod = "printUnsignedImm"; 404} 405 406def uimm6 : Operand<i32> { 407 let PrintMethod = "printUnsignedImm"; 408} 409 410def uimm16 : Operand<i32> { 411 let PrintMethod = "printUnsignedImm"; 412} 413 414def pcrel16 : Operand<i32> { 415} 416 417def MipsMemAsmOperand : AsmOperandClass { 418 let Name = "Mem"; 419 let ParserMethod = "parseMemOperand"; 420} 421 422def MipsMemSimm11AsmOperand : AsmOperandClass { 423 let Name = "MemOffsetSimm11"; 424 let SuperClasses = [MipsMemAsmOperand]; 425 let RenderMethod = "addMemOperands"; 426 let ParserMethod = "parseMemOperand"; 427 let PredicateMethod = "isMemWithSimmOffset<11>"; 428 //let DiagnosticType = "Simm11"; 429} 430 431def MipsInvertedImmoperand : AsmOperandClass { 432 let Name = "InvNum"; 433 let RenderMethod = "addImmOperands"; 434 let ParserMethod = "parseInvNum"; 435} 436 437def InvertedImOperand : Operand<i32> { 438 let ParserMatchClass = MipsInvertedImmoperand; 439} 440 441def InvertedImOperand64 : Operand<i64> { 442 let ParserMatchClass = MipsInvertedImmoperand; 443} 444 445class mem_generic : Operand<iPTR> { 446 let PrintMethod = "printMemOperand"; 447 let MIOperandInfo = (ops ptr_rc, simm16); 448 let EncoderMethod = "getMemEncoding"; 449 let ParserMatchClass = MipsMemAsmOperand; 450 let OperandType = "OPERAND_MEMORY"; 451} 452 453// Address operand 454def mem : mem_generic; 455 456// MSA specific address operand 457def mem_msa : mem_generic { 458 let MIOperandInfo = (ops ptr_rc, simm10); 459 let EncoderMethod = "getMSAMemEncoding"; 460} 461 462def mem_simm9 : mem_generic { 463 let MIOperandInfo = (ops ptr_rc, simm9); 464 let EncoderMethod = "getMemEncoding"; 465} 466 467def mem_simm11 : mem_generic { 468 let MIOperandInfo = (ops ptr_rc, simm11); 469 let EncoderMethod = "getMemEncoding"; 470 let ParserMatchClass = MipsMemSimm11AsmOperand; 471} 472 473def mem_ea : Operand<iPTR> { 474 let PrintMethod = "printMemOperandEA"; 475 let MIOperandInfo = (ops ptr_rc, simm16); 476 let EncoderMethod = "getMemEncoding"; 477 let OperandType = "OPERAND_MEMORY"; 478} 479 480def PtrRC : Operand<iPTR> { 481 let MIOperandInfo = (ops ptr_rc); 482 let DecoderMethod = "DecodePtrRegisterClass"; 483 let ParserMatchClass = GPR32AsmOperand; 484} 485 486// size operand of ext instruction 487def size_ext : Operand<i32> { 488 let EncoderMethod = "getSizeExtEncoding"; 489 let DecoderMethod = "DecodeExtSize"; 490} 491 492// size operand of ins instruction 493def size_ins : Operand<i32> { 494 let EncoderMethod = "getSizeInsEncoding"; 495 let DecoderMethod = "DecodeInsSize"; 496} 497 498// Transformation Function - get the lower 16 bits. 499def LO16 : SDNodeXForm<imm, [{ 500 return getImm(N, N->getZExtValue() & 0xFFFF); 501}]>; 502 503// Transformation Function - get the higher 16 bits. 504def HI16 : SDNodeXForm<imm, [{ 505 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 506}]>; 507 508// Plus 1. 509def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 510 511// Node immediate is zero (e.g. insve.d) 512def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>; 513 514// Node immediate fits as 16-bit sign extended on target immediate. 515// e.g. addi, andi 516def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 517 518// Node immediate fits as 16-bit sign extended on target immediate. 519// e.g. addi, andi 520def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 521 522// Node immediate fits as 15-bit sign extended on target immediate. 523// e.g. addi, andi 524def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 525 526// Node immediate fits as 16-bit zero extended on target immediate. 527// The LO16 param means that only the lower 16 bits of the node 528// immediate are caught. 529// e.g. addiu, sltiu 530def immZExt16 : PatLeaf<(imm), [{ 531 if (N->getValueType(0) == MVT::i32) 532 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 533 else 534 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 535}], LO16>; 536 537// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 538def immLow16Zero : PatLeaf<(imm), [{ 539 int64_t Val = N->getSExtValue(); 540 return isInt<32>(Val) && !(Val & 0xffff); 541}]>; 542 543// shamt field must fit in 5 bits. 544def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 545 546// True if (N + 1) fits in 16-bit field. 547def immSExt16Plus1 : PatLeaf<(imm), [{ 548 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 549}]>; 550 551// Mips Address Mode! SDNode frameindex could possibily be a match 552// since load and store instructions from stack used it. 553def addr : 554 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 555 556def addrRegImm : 557 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 558 559def addrRegReg : 560 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 561 562def addrDefault : 563 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 564 565def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>; 566 567//===----------------------------------------------------------------------===// 568// Instructions specific format 569//===----------------------------------------------------------------------===// 570 571// Arithmetic and logical instructions with 3 register operands. 572class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 573 InstrItinClass Itin = NoItinerary, 574 SDPatternOperator OpNode = null_frag>: 575 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 576 !strconcat(opstr, "\t$rd, $rs, $rt"), 577 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 578 let isCommutable = isComm; 579 let isReMaterializable = 1; 580 let TwoOperandAliasConstraint = "$rd = $rs"; 581} 582 583// Arithmetic and logical instructions with 2 register operands. 584class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 585 InstrItinClass Itin = NoItinerary, 586 SDPatternOperator imm_type = null_frag, 587 SDPatternOperator OpNode = null_frag> : 588 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 589 !strconcat(opstr, "\t$rt, $rs, $imm16"), 590 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 591 Itin, FrmI, opstr> { 592 let isReMaterializable = 1; 593 let TwoOperandAliasConstraint = "$rs = $rt"; 594} 595 596// Arithmetic Multiply ADD/SUB 597class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> : 598 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 599 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> { 600 let Defs = [HI0, LO0]; 601 let Uses = [HI0, LO0]; 602 let isCommutable = isComm; 603} 604 605// Logical 606class LogicNOR<string opstr, RegisterOperand RO>: 607 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 608 !strconcat(opstr, "\t$rd, $rs, $rt"), 609 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> { 610 let isCommutable = 1; 611} 612 613// Shifts 614class shift_rotate_imm<string opstr, Operand ImmOpnd, 615 RegisterOperand RO, InstrItinClass itin, 616 SDPatternOperator OpNode = null_frag, 617 SDPatternOperator PF = null_frag> : 618 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 619 !strconcat(opstr, "\t$rd, $rt, $shamt"), 620 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> { 621 let TwoOperandAliasConstraint = "$rt = $rd"; 622} 623 624class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin, 625 SDPatternOperator OpNode = null_frag>: 626 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 627 !strconcat(opstr, "\t$rd, $rt, $rs"), 628 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR, 629 opstr>; 630 631// Load Upper Imediate 632class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 633 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 634 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove { 635 let neverHasSideEffects = 1; 636 let isReMaterializable = 1; 637} 638 639// Memory Load/Store 640class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 641 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 642 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 643 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 644 let DecoderMethod = "DecodeMem"; 645 let canFoldAsLoad = 1; 646 let mayLoad = 1; 647} 648 649class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 650 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 651 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 652 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 653 let DecoderMethod = "DecodeMem"; 654 let mayStore = 1; 655} 656 657// Load/Store Left/Right 658let canFoldAsLoad = 1 in 659class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 660 InstrItinClass Itin> : 661 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 662 !strconcat(opstr, "\t$rt, $addr"), 663 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 664 let DecoderMethod = "DecodeMem"; 665 string Constraints = "$src = $rt"; 666} 667 668class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 669 InstrItinClass Itin> : 670 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 671 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 672 let DecoderMethod = "DecodeMem"; 673} 674 675// Conditional Branch 676class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, 677 RegisterOperand RO> : 678 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 679 !strconcat(opstr, "\t$rs, $rt, $offset"), 680 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 681 FrmI, opstr> { 682 let isBranch = 1; 683 let isTerminator = 1; 684 let hasDelaySlot = 1; 685 let Defs = [AT]; 686} 687 688class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, 689 RegisterOperand RO> : 690 InstSE<(outs), (ins RO:$rs, opnd:$offset), 691 !strconcat(opstr, "\t$rs, $offset"), 692 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, 693 FrmI, opstr> { 694 let isBranch = 1; 695 let isTerminator = 1; 696 let hasDelaySlot = 1; 697 let Defs = [AT]; 698} 699 700// SetCC 701class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 702 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 703 !strconcat(opstr, "\t$rd, $rs, $rt"), 704 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 705 II_SLT_SLTU, FrmR, opstr>; 706 707class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 708 RegisterOperand RO>: 709 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 710 !strconcat(opstr, "\t$rt, $rs, $imm16"), 711 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 712 II_SLTI_SLTIU, FrmI, opstr>; 713 714// Jump 715class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 716 SDPatternOperator targetoperator, string bopstr> : 717 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 718 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> { 719 let isTerminator=1; 720 let isBarrier=1; 721 let hasDelaySlot = 1; 722 let DecoderMethod = "DecodeJumpTarget"; 723 let Defs = [AT]; 724} 725 726// Unconditional branch 727class UncondBranch<Instruction BEQInst> : 728 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, 729 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 730 let isBranch = 1; 731 let isTerminator = 1; 732 let isBarrier = 1; 733 let hasDelaySlot = 1; 734 let AdditionalPredicates = [RelocPIC]; 735 let Defs = [AT]; 736} 737 738// Base class for indirect branch and return instruction classes. 739let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 740class JumpFR<string opstr, RegisterOperand RO, 741 SDPatternOperator operator = null_frag>: 742 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, 743 FrmR, opstr>; 744 745// Indirect branch 746class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> { 747 let isBranch = 1; 748 let isIndirectBranch = 1; 749} 750 751// Jump and Link (Call) 752let isCall=1, hasDelaySlot=1, Defs = [RA] in { 753 class JumpLink<string opstr, DAGOperand opnd> : 754 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 755 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> { 756 let DecoderMethod = "DecodeJumpTarget"; 757 } 758 759 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 760 Register RetReg, RegisterOperand ResRO = RO>: 761 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 762 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 763 764 class JumpLinkReg<string opstr, RegisterOperand RO>: 765 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 766 [], IIBranch, FrmR>; 767 768 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> : 769 InstSE<(outs), (ins RO:$rs, opnd:$offset), 770 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; 771 772} 773 774let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 775 hasExtraSrcRegAllocReq = 1, Defs = [AT] in { 776 class TailCall<Instruction JumpInst> : 777 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>, 778 PseudoInstExpansion<(JumpInst jmptarget:$target)>; 779 780 class TailCallReg<RegisterOperand RO, Instruction JRInst, 781 RegisterOperand ResRO = RO> : 782 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>, 783 PseudoInstExpansion<(JRInst ResRO:$rs)>; 784} 785 786class BAL_BR_Pseudo<Instruction RealInst> : 787 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 788 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 789 let isBranch = 1; 790 let isTerminator = 1; 791 let isBarrier = 1; 792 let hasDelaySlot = 1; 793 let Defs = [RA]; 794} 795 796// Syscall 797class SYS_FT<string opstr> : 798 InstSE<(outs), (ins uimm20:$code_), 799 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>; 800// Break 801class BRK_FT<string opstr> : 802 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 803 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, 804 FrmOther, opstr>; 805 806// (D)Eret 807class ER_FT<string opstr> : 808 InstSE<(outs), (ins), 809 opstr, [], NoItinerary, FrmOther, opstr>; 810 811// Interrupts 812class DEI_FT<string opstr, RegisterOperand RO> : 813 InstSE<(outs RO:$rt), (ins), 814 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>; 815 816// Wait 817class WAIT_FT<string opstr> : 818 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>; 819 820// Sync 821let hasSideEffects = 1 in 822class SYNC_FT<string opstr> : 823 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 824 NoItinerary, FrmOther, opstr>; 825 826let hasSideEffects = 1 in 827class TEQ_FT<string opstr, RegisterOperand RO> : 828 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 829 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, 830 FrmI, opstr>; 831 832class TEQI_FT<string opstr, RegisterOperand RO> : 833 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 834 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>; 835// Mul, Div 836class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 837 list<Register> DefRegs> : 838 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 839 itin, FrmR, opstr> { 840 let isCommutable = 1; 841 let Defs = DefRegs; 842 let neverHasSideEffects = 1; 843} 844 845// Pseudo multiply/divide instruction with explicit accumulator register 846// operands. 847class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 848 SDPatternOperator OpNode, InstrItinClass Itin, 849 bit IsComm = 1, bit HasSideEffects = 0, 850 bit UsesCustomInserter = 0> : 851 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 852 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 853 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 854 let isCommutable = IsComm; 855 let hasSideEffects = HasSideEffects; 856 let usesCustomInserter = UsesCustomInserter; 857} 858 859// Pseudo multiply add/sub instruction with explicit accumulator register 860// operands. 861class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode, 862 InstrItinClass itin> 863 : PseudoSE<(outs ACC64:$ac), 864 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 865 [(set ACC64:$ac, 866 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 867 itin>, 868 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 869 string Constraints = "$acin = $ac"; 870} 871 872class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 873 list<Register> DefRegs> : 874 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 875 [], itin, FrmR, opstr> { 876 let Defs = DefRegs; 877} 878 879// Move from Hi/Lo 880class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 881 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 882 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>; 883 884class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 885 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, 886 FrmR, opstr> { 887 let Uses = [UseReg]; 888 let neverHasSideEffects = 1; 889} 890 891class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> 892 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), 893 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], 894 II_MTHI_MTLO>; 895 896class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 897 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO, 898 FrmR, opstr> { 899 let Defs = DefRegs; 900 let neverHasSideEffects = 1; 901} 902 903class EffectiveAddress<string opstr, RegisterOperand RO> : 904 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 905 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI, 906 !strconcat(opstr, "_lea")> { 907 let isCodeGenOnly = 1; 908 let DecoderMethod = "DecodeMem"; 909} 910 911// Count Leading Ones/Zeros in Word 912class CountLeading0<string opstr, RegisterOperand RO>: 913 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 914 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>; 915 916class CountLeading1<string opstr, RegisterOperand RO>: 917 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 918 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>; 919 920// Sign Extend in Register. 921class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO, 922 InstrItinClass itin> : 923 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 924 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>; 925 926// Subword Swap 927class SubwordSwap<string opstr, RegisterOperand RO>: 928 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 929 NoItinerary, FrmR, opstr> { 930 let neverHasSideEffects = 1; 931} 932 933// Read Hardware 934class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 935 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 936 II_RDHWR, FrmR>; 937 938// Ext and Ins 939class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 940 SDPatternOperator Op = null_frag>: 941 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size), 942 !strconcat(opstr, " $rt, $rs, $pos, $size"), 943 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary, 944 FrmR, opstr>, ISA_MIPS32R2; 945 946class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 947 SDPatternOperator Op = null_frag>: 948 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), 949 !strconcat(opstr, " $rt, $rs, $pos, $size"), 950 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], 951 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 { 952 let Constraints = "$src = $rt"; 953} 954 955// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 956class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 957 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 958 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 959 960// Atomic Compare & Swap. 961class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 962 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 963 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 964 965class LLBase<string opstr, RegisterOperand RO> : 966 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 967 [], NoItinerary, FrmI> { 968 let DecoderMethod = "DecodeMem"; 969 let mayLoad = 1; 970} 971 972class SCBase<string opstr, RegisterOperand RO> : 973 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 974 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 975 let DecoderMethod = "DecodeMem"; 976 let mayStore = 1; 977 let Constraints = "$rt = $dst"; 978} 979 980class MFC3OP<string asmstr, RegisterOperand RO> : 981 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 982 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 983 984class TrapBase<Instruction RealInst> 985 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>, 986 PseudoInstExpansion<(RealInst 0, 0)> { 987 let isBarrier = 1; 988 let isTerminator = 1; 989 let isCodeGenOnly = 1; 990} 991 992//===----------------------------------------------------------------------===// 993// Pseudo instructions 994//===----------------------------------------------------------------------===// 995 996// Return RA. 997let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 998def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 999 1000let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1001def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 1002 [(callseq_start timm:$amt)]>; 1003def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1004 [(callseq_end timm:$amt1, timm:$amt2)]>; 1005} 1006 1007let usesCustomInserter = 1 in { 1008 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 1009 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 1010 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 1011 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 1012 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 1013 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 1014 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 1015 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 1016 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 1017 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 1018 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 1019 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 1020 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 1021 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 1022 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 1023 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 1024 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 1025 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 1026 1027 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 1028 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 1029 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 1030 1031 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 1032 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 1033 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 1034} 1035 1036/// Pseudo instructions for loading and storing accumulator registers. 1037let isPseudo = 1, isCodeGenOnly = 1 in { 1038 def LOAD_ACC64 : Load<"", ACC64>; 1039 def STORE_ACC64 : Store<"", ACC64>; 1040} 1041 1042// We need these two pseudo instructions to avoid offset calculation for long 1043// branches. See the comment in file MipsLongBranch.cpp for detailed 1044// explanation. 1045 1046// Expands to: lui $dst, %hi($tgt - $baltgt) 1047def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst), 1048 (ins brtarget:$tgt, brtarget:$baltgt), []>; 1049 1050// Expands to: addiu $dst, $src, %lo($tgt - $baltgt) 1051def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), 1052 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>; 1053 1054//===----------------------------------------------------------------------===// 1055// Instruction definition 1056//===----------------------------------------------------------------------===// 1057//===----------------------------------------------------------------------===// 1058// MipsI Instructions 1059//===----------------------------------------------------------------------===// 1060 1061/// Arithmetic Instructions (ALU Immediate) 1062def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, 1063 add>, 1064 ADDI_FM<0x9>, IsAsCheapAsAMove; 1065def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>, 1066 ISA_MIPS1_NOT_32R6_64R6; 1067def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 1068 SLTI_FM<0xa>; 1069def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 1070 SLTI_FM<0xb>; 1071def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, 1072 and>, 1073 ADDI_FM<0xc>; 1074def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, 1075 or>, 1076 ADDI_FM<0xd>; 1077def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, 1078 xor>, 1079 ADDI_FM<0xe>; 1080def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 1081 1082/// Arithmetic Instructions (3-Operand, R-Type) 1083def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, 1084 ADD_FM<0, 0x21>; 1085def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, 1086 ADD_FM<0, 0x23>; 1087let Defs = [HI0, LO0] in 1088def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, 1089 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; 1090def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 1091def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 1092def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 1093def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 1094def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, 1095 ADD_FM<0, 0x24>; 1096def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, 1097 ADD_FM<0, 0x25>; 1098def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, 1099 ADD_FM<0, 0x26>; 1100def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 1101 1102/// Shift Instructions 1103def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, 1104 immZExt5>, SRA_FM<0, 0>; 1105def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, 1106 immZExt5>, SRA_FM<2, 0>; 1107def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, 1108 immZExt5>, SRA_FM<3, 0>; 1109def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, 1110 SRLV_FM<4, 0>; 1111def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, 1112 SRLV_FM<6, 0>; 1113def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, 1114 SRLV_FM<7, 0>; 1115 1116// Rotate Instructions 1117def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, 1118 immZExt5>, 1119 SRA_FM<2, 1>, ISA_MIPS32R2; 1120def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, 1121 SRLV_FM<6, 1>, ISA_MIPS32R2; 1122 1123/// Load and Store Instructions 1124/// aligned 1125def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; 1126def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, 1127 LW_FM<0x24>; 1128def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, 1129 LW_FM<0x21>; 1130def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; 1131def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, 1132 LW_FM<0x23>; 1133def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>; 1134def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; 1135def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; 1136 1137/// load/store left/right 1138let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1139 AdditionalPredicates = [NotInMicroMips] in { 1140def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>, 1141 ISA_MIPS1_NOT_32R6_64R6; 1142def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>, 1143 ISA_MIPS1_NOT_32R6_64R6; 1144def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>, 1145 ISA_MIPS1_NOT_32R6_64R6; 1146def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>, 1147 ISA_MIPS1_NOT_32R6_64R6; 1148} 1149 1150def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32; 1151def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 1152def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; 1153def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; 1154def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; 1155def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; 1156def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; 1157 1158def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, 1159 ISA_MIPS2_NOT_32R6_64R6; 1160def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, 1161 ISA_MIPS2_NOT_32R6_64R6; 1162def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, 1163 ISA_MIPS2_NOT_32R6_64R6; 1164def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, 1165 ISA_MIPS2_NOT_32R6_64R6; 1166def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, 1167 ISA_MIPS2_NOT_32R6_64R6; 1168def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, 1169 ISA_MIPS2_NOT_32R6_64R6; 1170 1171def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>; 1172def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; 1173def TRAP : TrapBase<BREAK>; 1174def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; 1175 1176def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32; 1177def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32; 1178 1179def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; 1180def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; 1181 1182let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1183 AdditionalPredicates = [NotInMicroMips] in { 1184def WAIT : WAIT_FT<"wait">, WAIT_FM; 1185 1186/// Load-linked, Store-conditional 1187def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6; 1188def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6; 1189} 1190 1191/// Jump and Branch Instructions 1192def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>, 1193 AdditionalRequires<[RelocStatic]>, IsBranch; 1194def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>; 1195def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; 1196def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; 1197def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, 1198 BGEZ_FM<1, 1>; 1199def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, 1200 BGEZ_FM<7, 0>; 1201def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, 1202 BGEZ_FM<6, 0>; 1203def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, 1204 BGEZ_FM<1, 0>; 1205def B : UncondBranch<BEQ>; 1206 1207def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; 1208let AdditionalPredicates = [NotInMicroMips] in { 1209 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 1210 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 1211} 1212 1213// FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32. 1214def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6; 1215def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, 1216 ISA_MIPS1_NOT_32R6_64R6; 1217def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, 1218 ISA_MIPS1_NOT_32R6_64R6; 1219def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 1220def TAILCALL : TailCall<J>; 1221def TAILCALL_R : TailCallReg<GPR32Opnd, JR>; 1222 1223// Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64 1224// then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA. 1225class PseudoIndirectBranchBase<RegisterOperand RO> : 1226 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> { 1227 let isTerminator=1; 1228 let isBarrier=1; 1229 let hasDelaySlot = 1; 1230 let isBranch = 1; 1231 let isIndirectBranch = 1; 1232} 1233 1234def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>; 1235 1236// Return instructions are matched as a RetRA instruction, then ar expanded 1237// into PseudoReturn/PseudoReturn64 after register allocation. Finally, 1238// MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the 1239// ISA. 1240class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs), 1241 [], IIBranch> { 1242 let isTerminator = 1; 1243 let isBarrier = 1; 1244 let hasDelaySlot = 1; 1245 let isReturn = 1; 1246 let isCodeGenOnly = 1; 1247 let hasCtrlDep = 1; 1248 let hasExtraSrcRegAllocReq = 1; 1249} 1250 1251def PseudoReturn : PseudoReturnBase<GPR32Opnd>; 1252 1253// Exception handling related node and instructions. 1254// The conversion sequence is: 1255// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1256// MIPSeh_return -> (stack change + indirect branch) 1257// 1258// MIPSeh_return takes the place of regular return instruction 1259// but takes two arguments (V1, V0) which are used for storing 1260// the offset and return address respectively. 1261def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1262 1263def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1264 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1265 1266let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1267 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1268 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1269 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1270 GPR64:$dst), 1271 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1272} 1273 1274/// Multiply and Divide Instructions. 1275def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, 1276 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6; 1277def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, 1278 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6; 1279def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, 1280 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6; 1281def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, 1282 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6; 1283 1284def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, 1285 ISA_MIPS1_NOT_32R6_64R6; 1286def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, 1287 ISA_MIPS1_NOT_32R6_64R6; 1288let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1289 AdditionalPredicates = [NotInMicroMips] in { 1290def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, 1291 ISA_MIPS1_NOT_32R6_64R6; 1292def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, 1293 ISA_MIPS1_NOT_32R6_64R6; 1294} 1295 1296/// Sign Ext In Register Instructions. 1297def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, 1298 SEB_FM<0x10, 0x20>, ISA_MIPS32R2; 1299def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, 1300 SEB_FM<0x18, 0x20>, ISA_MIPS32R2; 1301 1302/// Count Leading 1303def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, 1304 ISA_MIPS32_NOT_32R6_64R6; 1305def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, 1306 ISA_MIPS32_NOT_32R6_64R6; 1307 1308/// Word Swap Bytes Within Halfwords 1309def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2; 1310 1311/// No operation. 1312def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1313 1314// FrameIndexes are legalized when they are operands from load/store 1315// instructions. The same not happens for stack address copies, so an 1316// add op with mem ComplexPattern is used and the stack address copy 1317// can be matched. It's similar to Sparc LEA_ADDRi 1318def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1319 1320// MADD*/MSUB* 1321def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, 1322 ISA_MIPS32_NOT_32R6_64R6; 1323def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, 1324 ISA_MIPS32_NOT_32R6_64R6; 1325def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, 1326 ISA_MIPS32_NOT_32R6_64R6; 1327def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, 1328 ISA_MIPS32_NOT_32R6_64R6; 1329 1330let AdditionalPredicates = [NotDSP] in { 1331def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>, 1332 ISA_MIPS1_NOT_32R6_64R6; 1333def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>, 1334 ISA_MIPS1_NOT_32R6_64R6; 1335def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6; 1336def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6; 1337def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6; 1338def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>, 1339 ISA_MIPS32_NOT_32R6_64R6; 1340def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>, 1341 ISA_MIPS32_NOT_32R6_64R6; 1342def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>, 1343 ISA_MIPS32_NOT_32R6_64R6; 1344def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>, 1345 ISA_MIPS32_NOT_32R6_64R6; 1346} 1347 1348def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV, 1349 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 1350def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, 1351 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 1352 1353def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1354 1355def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; 1356def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; 1357 1358/// Move Control Registers From/To CPU Registers 1359def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32; 1360def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32; 1361def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1362def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1363 1364class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1365 FrmOther>; 1366def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>; 1367def EHB : Barrier<"ehb">, BARRIER_FM<3>; 1368def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2; 1369 1370// JR_HB and JALR_HB are defined here using the new style naming 1371// scheme because some of this code is shared with Mips32r6InstrInfo.td 1372// and because of that it doesn't follow the naming convention of the 1373// rest of the file. To avoid a mixture of old vs new style, the new 1374// style was chosen. 1375class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 1376 dag OutOperandList = (outs); 1377 dag InOperandList = (ins GPROpnd:$rs); 1378 string AsmString = !strconcat(instr_asm, "\t$rs"); 1379 list<dag> Pattern = []; 1380} 1381 1382class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 1383 dag OutOperandList = (outs GPROpnd:$rd); 1384 dag InOperandList = (ins GPROpnd:$rs); 1385 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 1386 list<dag> Pattern = []; 1387} 1388 1389class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>, 1390 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> { 1391 let isBranch=1; 1392 let isIndirectBranch=1; 1393 let hasDelaySlot=1; 1394 let isTerminator=1; 1395 let isBarrier=1; 1396} 1397 1398class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>, 1399 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> { 1400 let isIndirectBranch=1; 1401 let hasDelaySlot=1; 1402} 1403 1404class JR_HB_ENC : JR_HB_FM<8>; 1405class JALR_HB_ENC : JALR_HB_FM<9>; 1406 1407def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6; 1408def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32; 1409 1410class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1411 FrmOther>; 1412def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>; 1413def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>; 1414def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>; 1415def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>; 1416 1417class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> : 1418 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), 1419 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>; 1420 1421def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>, 1422 INSN_MIPS3_32_NOT_32R6_64R6; 1423def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>, 1424 INSN_MIPS3_32_NOT_32R6_64R6; 1425 1426//===----------------------------------------------------------------------===// 1427// Instruction aliases 1428//===----------------------------------------------------------------------===// 1429def : MipsInstAlias<"move $dst, $src", 1430 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1431 GPR_32 { 1432 let AdditionalPredicates = [NotInMicroMips]; 1433} 1434def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>, 1435 ISA_MIPS1_NOT_32R6_64R6; 1436def : MipsInstAlias<"addu $rs, $rt, $imm", 1437 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1438def : MipsInstAlias<"add $rs, $rt, $imm", 1439 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1440def : MipsInstAlias<"and $rs, $rt, $imm", 1441 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1442def : MipsInstAlias<"and $rs, $imm", 1443 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; 1444def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1445let Predicates = [NotInMicroMips] in { 1446def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1447} 1448def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1449def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1450def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32; 1451def : MipsInstAlias<"not $rt, $rs", 1452 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1453def : MipsInstAlias<"neg $rt, $rs", 1454 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1455def : MipsInstAlias<"negu $rt", 1456 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; 1457def : MipsInstAlias<"negu $rt, $rs", 1458 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1459def : MipsInstAlias<"slt $rs, $rt, $imm", 1460 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1461def : MipsInstAlias<"sltu $rt, $rs, $imm", 1462 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>; 1463def : MipsInstAlias<"xor $rs, $rt, $imm", 1464 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1465def : MipsInstAlias<"or $rs, $rt, $imm", 1466 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1467def : MipsInstAlias<"or $rs, $imm", 1468 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; 1469def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1470def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1471def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1472def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1473def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1474def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1475def : MipsInstAlias<"bnez $rs,$offset", 1476 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1477def : MipsInstAlias<"beqz $rs,$offset", 1478 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1479def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; 1480 1481def : MipsInstAlias<"break", (BREAK 0, 0), 1>; 1482def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1483def : MipsInstAlias<"ei", (EI ZERO), 1>; 1484def : MipsInstAlias<"di", (DI ZERO), 1>; 1485 1486def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1487def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1488def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1489 1>; 1490def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1491def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1492 1>; 1493def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1494def : MipsInstAlias<"sll $rd, $rt, $rs", 1495 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1496def : MipsInstAlias<"sub, $rd, $rs, $imm", 1497 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, 1498 InvertedImOperand:$imm), 0>; 1499def : MipsInstAlias<"sub $rs, $imm", 1500 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), 1501 0>; 1502def : MipsInstAlias<"subu, $rd, $rs, $imm", 1503 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, 1504 InvertedImOperand:$imm), 0>; 1505def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, 1506 InvertedImOperand:$imm), 0>; 1507def : MipsInstAlias<"sra $rd, $rt, $rs", 1508 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1509def : MipsInstAlias<"srl $rd, $rt, $rs", 1510 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1511def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; 1512def : MipsInstAlias<"sync", 1513 (SYNC 0), 1>, ISA_MIPS2; 1514//===----------------------------------------------------------------------===// 1515// Assembler Pseudo Instructions 1516//===----------------------------------------------------------------------===// 1517 1518class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1519 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1520 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1521def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>; 1522 1523class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1524 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1525 !strconcat(instr_asm, "\t$rt, $addr")> ; 1526def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1527 1528class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1529 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1530 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1531def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; 1532 1533//===----------------------------------------------------------------------===// 1534// Arbitrary patterns that map to one or more instructions 1535//===----------------------------------------------------------------------===// 1536 1537// Load/store pattern templates. 1538class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1539 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1540 1541class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1542 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1543 1544// Small immediates 1545def : MipsPat<(i32 immSExt16:$in), 1546 (ADDiu ZERO, imm:$in)>; 1547def : MipsPat<(i32 immZExt16:$in), 1548 (ORi ZERO, imm:$in)>; 1549def : MipsPat<(i32 immLow16Zero:$in), 1550 (LUi (HI16 imm:$in))>; 1551 1552// Arbitrary immediates 1553def : MipsPat<(i32 imm:$imm), 1554 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1555 1556// Carry MipsPatterns 1557def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1558 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1559let AdditionalPredicates = [NotDSP] in { 1560 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1561 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1562 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1563 (ADDiu GPR32:$src, imm:$imm)>; 1564} 1565 1566// SYNC 1567def : MipsPat<(MipsSync (i32 immz)), 1568 (SYNC 0)>, ISA_MIPS2; 1569 1570// Call 1571def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1572 (JAL tglobaladdr:$dst)>; 1573def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1574 (JAL texternalsym:$dst)>; 1575//def : MipsPat<(MipsJmpLink GPR32:$dst), 1576// (JALR GPR32:$dst)>; 1577 1578// Tail call 1579def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1580 (TAILCALL tglobaladdr:$dst)>; 1581def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1582 (TAILCALL texternalsym:$dst)>; 1583// hi/lo relocs 1584def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1585def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1586def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1587def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1588def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1589def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1590 1591def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1592def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1593def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1594def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1595def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1596def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1597 1598def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1599 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1600def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1601 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1602def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1603 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1604def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1605 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1606def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1607 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1608 1609// gp_rel relocs 1610def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1611 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1612def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1613 (ADDiu GPR32:$gp, tconstpool:$in)>; 1614 1615// wrapper_pic 1616class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1617 MipsPat<(MipsWrapper RC:$gp, node:$in), 1618 (ADDiuOp RC:$gp, node:$in)>; 1619 1620def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1621def : WrapperPat<tconstpool, ADDiu, GPR32>; 1622def : WrapperPat<texternalsym, ADDiu, GPR32>; 1623def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1624def : WrapperPat<tjumptable, ADDiu, GPR32>; 1625def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1626 1627// Mips does not have "not", so we expand our way 1628def : MipsPat<(not GPR32:$in), 1629 (NOR GPR32Opnd:$in, ZERO)>; 1630 1631// extended loads 1632def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1633def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1634def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1635 1636// peepholes 1637def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1638 1639// brcond patterns 1640multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1641 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1642 Instruction SLTiuOp, Register ZEROReg> { 1643def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1644 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1645def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1646 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1647 1648def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1649 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1650def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1651 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1652def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1653 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1654def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1655 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1656def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1657 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1658def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1659 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1660 1661def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1662 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1663def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1664 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1665 1666def : MipsPat<(brcond RC:$cond, bb:$dst), 1667 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1668} 1669 1670defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1671 1672def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1673 (BLEZ i32:$lhs, bb:$dst)>; 1674def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1675 (BGEZ i32:$lhs, bb:$dst)>; 1676 1677// setcc patterns 1678multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1679 Instruction SLTuOp, Register ZEROReg> { 1680 def : MipsPat<(seteq RC:$lhs, 0), 1681 (SLTiuOp RC:$lhs, 1)>; 1682 def : MipsPat<(setne RC:$lhs, 0), 1683 (SLTuOp ZEROReg, RC:$lhs)>; 1684 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1685 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1686 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1687 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1688} 1689 1690multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1691 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1692 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1693 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1694 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1695} 1696 1697multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1698 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1699 (SLTOp RC:$rhs, RC:$lhs)>; 1700 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1701 (SLTuOp RC:$rhs, RC:$lhs)>; 1702} 1703 1704multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1705 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1706 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1707 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1708 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1709} 1710 1711multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1712 Instruction SLTiuOp> { 1713 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1714 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1715 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1716 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1717} 1718 1719defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1720defm : SetlePats<GPR32, SLT, SLTu>; 1721defm : SetgtPats<GPR32, SLT, SLTu>; 1722defm : SetgePats<GPR32, SLT, SLTu>; 1723defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1724 1725// bswap pattern 1726def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1727 1728// Load halfword/word patterns. 1729let AddedComplexity = 40 in { 1730 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1731 def : LoadRegImmPat<LH, i32, sextloadi16>; 1732 def : LoadRegImmPat<LW, i32, load>; 1733} 1734 1735//===----------------------------------------------------------------------===// 1736// Floating Point Support 1737//===----------------------------------------------------------------------===// 1738 1739include "MipsInstrFPU.td" 1740include "Mips64InstrInfo.td" 1741include "MipsCondMov.td" 1742 1743include "Mips32r6InstrInfo.td" 1744include "Mips64r6InstrInfo.td" 1745 1746// 1747// Mips16 1748 1749include "Mips16InstrFormats.td" 1750include "Mips16InstrInfo.td" 1751 1752// DSP 1753include "MipsDSPInstrFormats.td" 1754include "MipsDSPInstrInfo.td" 1755 1756// MSA 1757include "MipsMSAInstrFormats.td" 1758include "MipsMSAInstrInfo.td" 1759 1760// Micromips 1761include "MicroMipsInstrFormats.td" 1762include "MicroMipsInstrInfo.td" 1763include "MicroMipsInstrFPU.td" 1764