MipsInstrInfo.td revision 0c66403efdf88ff4f247b6a9f45339bb3a893235
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 76 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 77 78// These are target-independent nodes, but have target-specific formats. 79def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 80 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 81def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 82 [SDNPHasChain, SDNPSideEffect, 83 SDNPOptInGlue, SDNPOutGlue]>; 84 85// MAdd*/MSub* nodes 86def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 87 [SDNPOptInGlue, SDNPOutGlue]>; 88def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 89 [SDNPOptInGlue, SDNPOutGlue]>; 90def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 91 [SDNPOptInGlue, SDNPOutGlue]>; 92def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 93 [SDNPOptInGlue, SDNPOutGlue]>; 94 95// DivRem(u) nodes 96def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 97 [SDNPOutGlue]>; 98def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 99 [SDNPOutGlue]>; 100 101// Target constant nodes that are not part of any isel patterns and remain 102// unchanged can cause instructions with illegal operands to be emitted. 103// Wrapper node patterns give the instruction selector a chance to replace 104// target constant nodes that would otherwise remain unchanged with ADDiu 105// nodes. Without these wrapper node patterns, the following conditional move 106// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 107// compiled: 108// movn %got(d)($gp), %got(c)($gp), $4 109// This instruction is illegal since movn can take only register operands. 110 111def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 112 113def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 114 115def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 116def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 117 118def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 120def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 122def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 124def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 126def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 128def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 132def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134 135//===----------------------------------------------------------------------===// 136// Mips Instruction Predicate Definitions. 137//===----------------------------------------------------------------------===// 138def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 139 AssemblerPredicate<"FeatureSEInReg">; 140def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 141 AssemblerPredicate<"FeatureBitCount">; 142def HasSwap : Predicate<"Subtarget.hasSwap()">, 143 AssemblerPredicate<"FeatureSwap">; 144def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 145 AssemblerPredicate<"FeatureCondMov">; 146def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 147 AssemblerPredicate<"FeatureFPIdx">; 148def HasMips32 : Predicate<"Subtarget.hasMips32()">, 149 AssemblerPredicate<"FeatureMips32">; 150def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 151 AssemblerPredicate<"FeatureMips32r2">; 152def HasMips64 : Predicate<"Subtarget.hasMips64()">, 153 AssemblerPredicate<"FeatureMips64">; 154def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 155 AssemblerPredicate<"!FeatureMips64">; 156def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 157 AssemblerPredicate<"FeatureMips64r2">; 158def IsN64 : Predicate<"Subtarget.isABI_N64()">, 159 AssemblerPredicate<"FeatureN64">; 160def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 161 AssemblerPredicate<"!FeatureN64">; 162def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 163 AssemblerPredicate<"FeatureMips16">; 164def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 165 AssemblerPredicate<"FeatureMips32">; 166def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 167 AssemblerPredicate<"FeatureMips32">; 168def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 169 AssemblerPredicate<"FeatureMips32">; 170def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 171 AssemblerPredicate<"!FeatureMips16">; 172 173class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 174 let Predicates = [HasStdEnc]; 175} 176 177class IsCommutable { 178 bit isCommutable = 1; 179} 180 181class IsBranch { 182 bit isBranch = 1; 183} 184 185class IsReturn { 186 bit isReturn = 1; 187} 188 189class IsCall { 190 bit isCall = 1; 191} 192 193class IsTailCall { 194 bit isCall = 1; 195 bit isTerminator = 1; 196 bit isReturn = 1; 197 bit isBarrier = 1; 198 bit hasExtraSrcRegAllocReq = 1; 199 bit isCodeGenOnly = 1; 200} 201 202class IsAsCheapAsAMove { 203 bit isAsCheapAsAMove = 1; 204} 205 206class NeverHasSideEffects { 207 bit neverHasSideEffects = 1; 208} 209 210//===----------------------------------------------------------------------===// 211// Instruction format superclass 212//===----------------------------------------------------------------------===// 213 214include "MipsInstrFormats.td" 215 216//===----------------------------------------------------------------------===// 217// Mips Operand, Complex Patterns and Transformations Definitions. 218//===----------------------------------------------------------------------===// 219 220// Instruction operand types 221def jmptarget : Operand<OtherVT> { 222 let EncoderMethod = "getJumpTargetOpValue"; 223} 224def brtarget : Operand<OtherVT> { 225 let EncoderMethod = "getBranchTargetOpValue"; 226 let OperandType = "OPERAND_PCREL"; 227 let DecoderMethod = "DecodeBranchTarget"; 228} 229def calltarget : Operand<iPTR> { 230 let EncoderMethod = "getJumpTargetOpValue"; 231} 232def calltarget64: Operand<i64>; 233def simm16 : Operand<i32> { 234 let DecoderMethod= "DecodeSimm16"; 235} 236 237def simm20 : Operand<i32> { 238} 239 240def simm16_64 : Operand<i64>; 241def shamt : Operand<i32>; 242 243// Unsigned Operand 244def uimm16 : Operand<i32> { 245 let PrintMethod = "printUnsignedImm"; 246} 247 248def MipsMemAsmOperand : AsmOperandClass { 249 let Name = "Mem"; 250 let ParserMethod = "parseMemOperand"; 251} 252 253// Address operand 254def mem : Operand<i32> { 255 let PrintMethod = "printMemOperand"; 256 let MIOperandInfo = (ops CPURegs, simm16); 257 let EncoderMethod = "getMemEncoding"; 258 let ParserMatchClass = MipsMemAsmOperand; 259} 260 261def mem64 : Operand<i64> { 262 let PrintMethod = "printMemOperand"; 263 let MIOperandInfo = (ops CPU64Regs, simm16_64); 264 let EncoderMethod = "getMemEncoding"; 265 let ParserMatchClass = MipsMemAsmOperand; 266} 267 268def mem_ea : Operand<i32> { 269 let PrintMethod = "printMemOperandEA"; 270 let MIOperandInfo = (ops CPURegs, simm16); 271 let EncoderMethod = "getMemEncoding"; 272} 273 274def mem_ea_64 : Operand<i64> { 275 let PrintMethod = "printMemOperandEA"; 276 let MIOperandInfo = (ops CPU64Regs, simm16_64); 277 let EncoderMethod = "getMemEncoding"; 278} 279 280// size operand of ext instruction 281def size_ext : Operand<i32> { 282 let EncoderMethod = "getSizeExtEncoding"; 283 let DecoderMethod = "DecodeExtSize"; 284} 285 286// size operand of ins instruction 287def size_ins : Operand<i32> { 288 let EncoderMethod = "getSizeInsEncoding"; 289 let DecoderMethod = "DecodeInsSize"; 290} 291 292// Transformation Function - get the lower 16 bits. 293def LO16 : SDNodeXForm<imm, [{ 294 return getImm(N, N->getZExtValue() & 0xFFFF); 295}]>; 296 297// Transformation Function - get the higher 16 bits. 298def HI16 : SDNodeXForm<imm, [{ 299 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 300}]>; 301 302// Node immediate fits as 16-bit sign extended on target immediate. 303// e.g. addi, andi 304def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 305 306// Node immediate fits as 15-bit sign extended on target immediate. 307// e.g. addi, andi 308def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 309 310// Node immediate fits as 16-bit zero extended on target immediate. 311// The LO16 param means that only the lower 16 bits of the node 312// immediate are caught. 313// e.g. addiu, sltiu 314def immZExt16 : PatLeaf<(imm), [{ 315 if (N->getValueType(0) == MVT::i32) 316 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 317 else 318 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 319}], LO16>; 320 321// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 322def immLow16Zero : PatLeaf<(imm), [{ 323 int64_t Val = N->getSExtValue(); 324 return isInt<32>(Val) && !(Val & 0xffff); 325}]>; 326 327// shamt field must fit in 5 bits. 328def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 329 330// Mips Address Mode! SDNode frameindex could possibily be a match 331// since load and store instructions from stack used it. 332def addr : 333 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 334 335//===----------------------------------------------------------------------===// 336// Instructions specific format 337//===----------------------------------------------------------------------===// 338 339// Arithmetic and logical instructions with 3 register operands. 340class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 341 InstrItinClass Itin = NoItinerary, 342 SDPatternOperator OpNode = null_frag>: 343 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 344 !strconcat(opstr, "\t$rd, $rs, $rt"), 345 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { 346 let isCommutable = isComm; 347 let isReMaterializable = 1; 348 string BaseOpcode; 349 string Arch; 350} 351 352// Arithmetic and logical instructions with 2 register operands. 353class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 354 SDPatternOperator imm_type = null_frag, 355 SDPatternOperator OpNode = null_frag> : 356 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 357 !strconcat(opstr, "\t$rt, $rs, $imm16"), 358 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> { 359 let isReMaterializable = 1; 360} 361 362// Arithmetic Multiply ADD/SUB 363class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> : 364 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 365 !strconcat(opstr, "\t$rs, $rt"), 366 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> { 367 let Defs = [HI, LO]; 368 let Uses = [HI, LO]; 369 let isCommutable = isComm; 370} 371 372// Logical 373class LogicNOR<string opstr, RegisterOperand RC>: 374 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 375 !strconcat(opstr, "\t$rd, $rs, $rt"), 376 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 377 let isCommutable = 1; 378} 379 380// Shifts 381class shift_rotate_imm<string opstr, Operand ImmOpnd, 382 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 383 SDPatternOperator PF = null_frag> : 384 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 385 !strconcat(opstr, "\t$rd, $rt, $shamt"), 386 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 387 388class shift_rotate_reg<string opstr, RegisterOperand RC, 389 SDPatternOperator OpNode = null_frag>: 390 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 391 !strconcat(opstr, "\t$rd, $rt, $rs"), 392 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>; 393 394// Load Upper Imediate 395class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 396 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 397 [], IIAlu, FrmI>, IsAsCheapAsAMove { 398 let neverHasSideEffects = 1; 399 let isReMaterializable = 1; 400} 401 402class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 403 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 404 bits<21> addr; 405 let Inst{25-21} = addr{20-16}; 406 let Inst{15-0} = addr{15-0}; 407 let DecoderMethod = "DecodeMem"; 408} 409 410// Memory Load/Store 411class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 412 Operand MemOpnd> : 413 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 414 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 415 let DecoderMethod = "DecodeMem"; 416 let canFoldAsLoad = 1; 417} 418 419class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 420 Operand MemOpnd> : 421 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 422 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 423 let DecoderMethod = "DecodeMem"; 424} 425 426multiclass LoadM<string opstr, RegisterClass RC, 427 SDPatternOperator OpNode = null_frag> { 428 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 429 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 430 let DecoderNamespace = "Mips64"; 431 let isCodeGenOnly = 1; 432 } 433} 434 435multiclass StoreM<string opstr, RegisterClass RC, 436 SDPatternOperator OpNode = null_frag> { 437 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 438 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 439 let DecoderNamespace = "Mips64"; 440 let isCodeGenOnly = 1; 441 } 442} 443 444// Load/Store Left/Right 445let canFoldAsLoad = 1 in 446class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 447 Operand MemOpnd> : 448 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 449 !strconcat(opstr, "\t$rt, $addr"), 450 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 451 let DecoderMethod = "DecodeMem"; 452 string Constraints = "$src = $rt"; 453} 454 455class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 456 Operand MemOpnd>: 457 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 458 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 459 let DecoderMethod = "DecodeMem"; 460} 461 462multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 463 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 464 Requires<[NotN64, HasStdEnc]>; 465 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 466 Requires<[IsN64, HasStdEnc]> { 467 let DecoderNamespace = "Mips64"; 468 let isCodeGenOnly = 1; 469 } 470} 471 472multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 473 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 474 Requires<[NotN64, HasStdEnc]>; 475 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 476 Requires<[IsN64, HasStdEnc]> { 477 let DecoderNamespace = "Mips64"; 478 let isCodeGenOnly = 1; 479 } 480} 481 482// Conditional Branch 483class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 484 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 485 !strconcat(opstr, "\t$rs, $rt, $offset"), 486 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 487 FrmI> { 488 let isBranch = 1; 489 let isTerminator = 1; 490 let hasDelaySlot = 1; 491 let Defs = [AT]; 492} 493 494class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 495 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 496 !strconcat(opstr, "\t$rs, $offset"), 497 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 498 let isBranch = 1; 499 let isTerminator = 1; 500 let hasDelaySlot = 1; 501 let Defs = [AT]; 502} 503 504// SetCC 505class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 506 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 507 !strconcat(opstr, "\t$rd, $rs, $rt"), 508 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 509 510class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 511 RegisterClass RC>: 512 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 513 !strconcat(opstr, "\t$rt, $rs, $imm16"), 514 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 515 IIAlu, FrmI>; 516 517// Jump 518class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 519 SDPatternOperator targetoperator> : 520 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 521 [(operator targetoperator:$target)], IIBranch, FrmJ> { 522 let isTerminator=1; 523 let isBarrier=1; 524 let hasDelaySlot = 1; 525 let DecoderMethod = "DecodeJumpTarget"; 526 let Defs = [AT]; 527} 528 529// Unconditional branch 530class UncondBranch<string opstr> : 531 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 532 [(br bb:$offset)], IIBranch, FrmI> { 533 let isBranch = 1; 534 let isTerminator = 1; 535 let isBarrier = 1; 536 let hasDelaySlot = 1; 537 let Predicates = [RelocPIC, HasStdEnc]; 538 let Defs = [AT]; 539} 540 541// Base class for indirect branch and return instruction classes. 542let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 543class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 544 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 545 546// Indirect branch 547class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 548 let isBranch = 1; 549 let isIndirectBranch = 1; 550} 551 552// Return instruction 553class RetBase<RegisterClass RC>: JumpFR<RC> { 554 let isReturn = 1; 555 let isCodeGenOnly = 1; 556 let hasCtrlDep = 1; 557 let hasExtraSrcRegAllocReq = 1; 558} 559 560// Jump and Link (Call) 561let isCall=1, hasDelaySlot=1, Defs = [RA] in { 562 class JumpLink<string opstr> : 563 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 564 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 565 let DecoderMethod = "DecodeJumpTarget"; 566 } 567 568 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 569 Register RetReg>: 570 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 571 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 572 573 class JumpLinkReg<string opstr, RegisterClass RC>: 574 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 575 [], IIBranch, FrmR>; 576 577 class BGEZAL_FT<string opstr, RegisterOperand RO> : 578 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 579 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 580 581} 582 583class BAL_FT : 584 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 585 let isBranch = 1; 586 let isTerminator = 1; 587 let isBarrier = 1; 588 let hasDelaySlot = 1; 589 let Defs = [RA]; 590} 591 592// Sync 593let hasSideEffects = 1 in 594class SYNC_FT : 595 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 596 NoItinerary, FrmOther>; 597 598// Mul, Div 599class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 600 list<Register> DefRegs> : 601 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 602 itin, FrmR> { 603 let isCommutable = 1; 604 let Defs = DefRegs; 605 let neverHasSideEffects = 1; 606} 607 608class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO, 609 list<Register> DefRegs> : 610 InstSE<(outs), (ins RO:$rs, RO:$rt), 611 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin, 612 FrmR> { 613 let Defs = DefRegs; 614} 615 616// Move from Hi/Lo 617class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 618 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 619 let Uses = UseRegs; 620 let neverHasSideEffects = 1; 621} 622 623class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 624 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 625 let Defs = DefRegs; 626 let neverHasSideEffects = 1; 627} 628 629class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 630 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 631 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 632 let isCodeGenOnly = 1; 633 let DecoderMethod = "DecodeMem"; 634} 635 636// Count Leading Ones/Zeros in Word 637class CountLeading0<string opstr, RegisterOperand RO>: 638 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 639 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 640 Requires<[HasBitCount, HasStdEnc]>; 641 642class CountLeading1<string opstr, RegisterOperand RO>: 643 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 644 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 645 Requires<[HasBitCount, HasStdEnc]>; 646 647 648// Sign Extend in Register. 649class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 650 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 651 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 652 let Predicates = [HasSEInReg, HasStdEnc]; 653} 654 655// Subword Swap 656class SubwordSwap<string opstr, RegisterOperand RO>: 657 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 658 NoItinerary, FrmR> { 659 let Predicates = [HasSwap, HasStdEnc]; 660 let neverHasSideEffects = 1; 661} 662 663// Read Hardware 664class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 665 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 666 IIAlu, FrmR>; 667 668// Ext and Ins 669class ExtBase<string opstr, RegisterOperand RO>: 670 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 671 !strconcat(opstr, " $rt, $rs, $pos, $size"), 672 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 673 FrmR> { 674 let Predicates = [HasMips32r2, HasStdEnc]; 675} 676 677class InsBase<string opstr, RegisterOperand RO>: 678 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 679 !strconcat(opstr, " $rt, $rs, $pos, $size"), 680 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 681 NoItinerary, FrmR> { 682 let Predicates = [HasMips32r2, HasStdEnc]; 683 let Constraints = "$src = $rt"; 684} 685 686// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 687class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 688 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 689 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 690 691multiclass Atomic2Ops32<PatFrag Op> { 692 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 693 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 694 Requires<[IsN64, HasStdEnc]> { 695 let DecoderNamespace = "Mips64"; 696 } 697} 698 699// Atomic Compare & Swap. 700class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 701 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 702 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 703 704multiclass AtomicCmpSwap32<PatFrag Op> { 705 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 706 Requires<[NotN64, HasStdEnc]>; 707 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 708 Requires<[IsN64, HasStdEnc]> { 709 let DecoderNamespace = "Mips64"; 710 } 711} 712 713class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 714 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 715 [], NoItinerary, FrmI> { 716 let DecoderMethod = "DecodeMem"; 717 let mayLoad = 1; 718} 719 720class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 721 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 722 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 723 let DecoderMethod = "DecodeMem"; 724 let mayStore = 1; 725 let Constraints = "$rt = $dst"; 726} 727 728class MFC3OP<dag outs, dag ins, string asmstr> : 729 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 730 731//===----------------------------------------------------------------------===// 732// Pseudo instructions 733//===----------------------------------------------------------------------===// 734 735// Return RA. 736let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 737def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 738 739let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 740def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 741 [(callseq_start timm:$amt)]>; 742def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 743 [(callseq_end timm:$amt1, timm:$amt2)]>; 744} 745 746let usesCustomInserter = 1 in { 747 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 748 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 749 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 750 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 751 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 752 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 753 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 754 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 755 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 756 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 757 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 758 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 759 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 760 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 761 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 762 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 763 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 764 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 765 766 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 767 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 768 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 769 770 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 771 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 772 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 773} 774 775//===----------------------------------------------------------------------===// 776// Instruction definition 777//===----------------------------------------------------------------------===// 778//===----------------------------------------------------------------------===// 779// MipsI Instructions 780//===----------------------------------------------------------------------===// 781 782/// Arithmetic Instructions (ALU Immediate) 783def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 784 ADDI_FM<0x9>, IsAsCheapAsAMove; 785def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 786def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 787def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 788def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 789 ADDI_FM<0xc>; 790def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 791 ADDI_FM<0xd>; 792def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 793 ADDI_FM<0xe>; 794def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 795 796/// Arithmetic Instructions (3-Operand, R-Type) 797def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>; 798def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 799def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 800def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 801def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 802def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 803def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 804def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 805def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 806def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 807def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 808 809/// Shift Instructions 810def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 811 SRA_FM<0, 0>; 812def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 813 SRA_FM<2, 0>; 814def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 815 SRA_FM<3, 0>; 816def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 817def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 818def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 819 820// Rotate Instructions 821let Predicates = [HasMips32r2, HasStdEnc] in { 822 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>, 823 SRA_FM<2, 1>; 824 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>; 825} 826 827/// Load and Store Instructions 828/// aligned 829defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 830defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; 831defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; 832defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 833defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; 834defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 835defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 836defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 837 838/// load/store left/right 839defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 840defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 841defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 842defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 843 844def SYNC : SYNC_FT, SYNC_FM; 845 846/// Load-linked, Store-conditional 847let Predicates = [NotN64, HasStdEnc] in { 848 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 849 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 850} 851 852let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 853 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 854 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 855} 856 857/// Jump and Branch Instructions 858def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 859 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 860def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 861def B : UncondBranch<"b">, B_FM; 862def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 863def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 864def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 865def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 866def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 867def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 868 869def BAL_BR: BAL_FT, BAL_FM; 870 871def JAL : JumpLink<"jal">, FJ<3>; 872def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 873def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 874def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 875def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 876def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 877def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 878 879def RET : RetBase<CPURegs>, MTLO_FM<8>; 880 881// Exception handling related node and instructions. 882// The conversion sequence is: 883// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 884// MIPSeh_return -> (stack change + indirect branch) 885// 886// MIPSeh_return takes the place of regular return instruction 887// but takes two arguments (V1, V0) which are used for storing 888// the offset and return address respectively. 889def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 890 891def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 892 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 893 894let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 895 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 896 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 897 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 898 CPU64Regs:$dst), 899 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 900} 901 902/// Multiply and Divide Instructions. 903def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>; 904def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>; 905def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>, 906 MULT_FM<0, 0x1a>; 907def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>, 908 MULT_FM<0, 0x1b>; 909 910def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 911def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 912def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 913def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 914 915/// Sign Ext In Register Instructions. 916def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 917def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 918 919/// Count Leading 920def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 921def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 922 923/// Word Swap Bytes Within Halfwords 924def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 925 926/// No operation. 927def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 928 929// FrameIndexes are legalized when they are operands from load/store 930// instructions. The same not happens for stack address copies, so an 931// add op with mem ComplexPattern is used and the stack address copy 932// can be matched. It's similar to Sparc LEA_ADDRi 933def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 934 935// MADD*/MSUB* 936def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; 937def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; 938def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; 939def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; 940 941def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 942 943def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 944def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 945 946/// Move Control Registers From/To CPU Registers 947def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 948 (ins CPURegsOpnd:$rd, uimm16:$sel), 949 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 950 951def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 952 (ins CPURegsOpnd:$rt), 953 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 954 955def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 956 (ins CPURegsOpnd:$rd, uimm16:$sel), 957 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 958 959def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 960 (ins CPURegsOpnd:$rt), 961 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 962 963//===----------------------------------------------------------------------===// 964// Instruction aliases 965//===----------------------------------------------------------------------===// 966def : InstAlias<"move $dst, $src", 967 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 968 Requires<[NotMips64]>; 969def : InstAlias<"move $dst, $src", 970 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 0>, 971 Requires<[NotMips64]>; 972def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 973def : InstAlias<"addu $rs, $rt, $imm", 974 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 975def : InstAlias<"add $rs, $rt, $imm", 976 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 977def : InstAlias<"and $rs, $rt, $imm", 978 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 979def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 980 Requires<[NotMips64]>; 981def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 982def : InstAlias<"not $rt, $rs", 983 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 984def : InstAlias<"neg $rt, $rs", 985 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 986def : InstAlias<"negu $rt, $rs", 987 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 988def : InstAlias<"slt $rs, $rt, $imm", 989 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 990def : InstAlias<"xor $rs, $rt, $imm", 991 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 992 Requires<[NotMips64]>; 993def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 994def : InstAlias<"mfc0 $rt, $rd", 995 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 996def : InstAlias<"mtc0 $rt, $rd", 997 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 998def : InstAlias<"mfc2 $rt, $rd", 999 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1000def : InstAlias<"mtc2 $rt, $rd", 1001 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1002 1003//===----------------------------------------------------------------------===// 1004// Assembler Pseudo Instructions 1005//===----------------------------------------------------------------------===// 1006 1007class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1008 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1009 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1010def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1011 1012class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1013 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1014 !strconcat(instr_asm, "\t$rt, $addr")> ; 1015def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1016 1017class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1018 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1019 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1020def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1021 1022 1023 1024//===----------------------------------------------------------------------===// 1025// Arbitrary patterns that map to one or more instructions 1026//===----------------------------------------------------------------------===// 1027 1028// Small immediates 1029def : MipsPat<(i32 immSExt16:$in), 1030 (ADDiu ZERO, imm:$in)>; 1031def : MipsPat<(i32 immZExt16:$in), 1032 (ORi ZERO, imm:$in)>; 1033def : MipsPat<(i32 immLow16Zero:$in), 1034 (LUi (HI16 imm:$in))>; 1035 1036// Arbitrary immediates 1037def : MipsPat<(i32 imm:$imm), 1038 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1039 1040// Carry MipsPatterns 1041def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1042 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1043def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1044 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1045def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1046 (ADDiu CPURegs:$src, imm:$imm)>; 1047 1048// Call 1049def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1050 (JAL tglobaladdr:$dst)>; 1051def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1052 (JAL texternalsym:$dst)>; 1053//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1054// (JALR CPURegs:$dst)>; 1055 1056// Tail call 1057def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1058 (TAILCALL tglobaladdr:$dst)>; 1059def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1060 (TAILCALL texternalsym:$dst)>; 1061// hi/lo relocs 1062def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1063def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1064def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1065def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1066def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1067def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1068 1069def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1070def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1071def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1072def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1073def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1074def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1075 1076def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1077 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1078def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1079 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1080def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1081 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1082def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1083 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1084def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1085 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1086 1087// gp_rel relocs 1088def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1089 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1090def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1091 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1092 1093// wrapper_pic 1094class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1095 MipsPat<(MipsWrapper RC:$gp, node:$in), 1096 (ADDiuOp RC:$gp, node:$in)>; 1097 1098def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1099def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1100def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1101def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1102def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1103def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1104 1105// Mips does not have "not", so we expand our way 1106def : MipsPat<(not CPURegs:$in), 1107 (NOR CPURegsOpnd:$in, ZERO)>; 1108 1109// extended loads 1110let Predicates = [NotN64, HasStdEnc] in { 1111 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1112 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1113 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1114} 1115let Predicates = [IsN64, HasStdEnc] in { 1116 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1117 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1118 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1119} 1120 1121// peepholes 1122let Predicates = [NotN64, HasStdEnc] in { 1123 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1124} 1125let Predicates = [IsN64, HasStdEnc] in { 1126 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1127} 1128 1129// brcond patterns 1130multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1131 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1132 Instruction SLTiuOp, Register ZEROReg> { 1133def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1134 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1135def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1136 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1137 1138def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1139 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1140def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1141 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1142def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1143 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1144def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1145 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1146 1147def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1148 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1149def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1150 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1151 1152def : MipsPat<(brcond RC:$cond, bb:$dst), 1153 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1154} 1155 1156defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1157 1158// setcc patterns 1159multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1160 Instruction SLTuOp, Register ZEROReg> { 1161 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1162 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1163 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1164 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1165} 1166 1167multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1168 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1169 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1170 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1171 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1172} 1173 1174multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1175 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1176 (SLTOp RC:$rhs, RC:$lhs)>; 1177 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1178 (SLTuOp RC:$rhs, RC:$lhs)>; 1179} 1180 1181multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1182 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1183 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1184 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1185 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1186} 1187 1188multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1189 Instruction SLTiuOp> { 1190 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1191 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1192 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1193 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1194} 1195 1196defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1197defm : SetlePats<CPURegs, SLT, SLTu>; 1198defm : SetgtPats<CPURegs, SLT, SLTu>; 1199defm : SetgePats<CPURegs, SLT, SLTu>; 1200defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1201 1202// bswap pattern 1203def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1204 1205//===----------------------------------------------------------------------===// 1206// Floating Point Support 1207//===----------------------------------------------------------------------===// 1208 1209include "MipsInstrFPU.td" 1210include "Mips64InstrInfo.td" 1211include "MipsCondMov.td" 1212 1213// 1214// Mips16 1215 1216include "Mips16InstrFormats.td" 1217include "Mips16InstrInfo.td" 1218 1219// DSP 1220include "MipsDSPInstrFormats.td" 1221include "MipsDSPInstrInfo.td" 1222 1223