MipsInstrInfo.td revision 175f0fd99aaa66fd4268d0f3ff73d6b76332c99f
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 30def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 31 SDTCisSameAs<1, 2>]>; 32def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 33 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 34 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 35def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 36 37def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 38 39def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 40 41def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 43def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 45 SDTCisSameAs<0, 4>]>; 46 47def SDTMipsLoadLR : SDTypeProfile<1, 2, 48 [SDTCisInt<0>, SDTCisPtrTy<1>, 49 SDTCisSameAs<0, 2>]>; 50 51// Call 52def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 53 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 54 SDNPVariadic]>; 55 56// Tail call 57def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 58 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 59 60// Hi and Lo nodes are used to handle global addresses. Used on 61// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 62// static model. (nothing to do with Mips Registers Hi and Lo) 63def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 64def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 65def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 66 67// TlsGd node is used to handle General Dynamic TLS 68def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 69 70// TprelHi and TprelLo nodes are used to handle Local Exec TLS 71def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 72def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 73 74// Thread pointer 75def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 76 77// Return 78def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 79 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 80 81// These are target-independent nodes, but have target-specific formats. 82def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 83 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 84def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 85 [SDNPHasChain, SDNPSideEffect, 86 SDNPOptInGlue, SDNPOutGlue]>; 87 88// Node used to extract integer from LO/HI register. 89def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 90 91// Node used to insert 32-bit integers to LOHI register pair. 92def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 93 94// Mult nodes. 95def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 97 98// MAdd*/MSub* nodes 99def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 101def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 103 104// DivRem(u) nodes 105def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 106def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 107def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, [SDNPOutGlue]>; 108def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110 111// Target constant nodes that are not part of any isel patterns and remain 112// unchanged can cause instructions with illegal operands to be emitted. 113// Wrapper node patterns give the instruction selector a chance to replace 114// target constant nodes that would otherwise remain unchanged with ADDiu 115// nodes. Without these wrapper node patterns, the following conditional move 116// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 117// compiled: 118// movn %got(d)($gp), %got(c)($gp), $4 119// This instruction is illegal since movn can take only register operands. 120 121def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 122 123def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 124 125def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 126def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 127 128def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 137 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 138def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 141 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 142def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144 145//===----------------------------------------------------------------------===// 146// Mips Instruction Predicate Definitions. 147//===----------------------------------------------------------------------===// 148def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 149 AssemblerPredicate<"FeatureSEInReg">; 150def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 151 AssemblerPredicate<"FeatureBitCount">; 152def HasSwap : Predicate<"Subtarget.hasSwap()">, 153 AssemblerPredicate<"FeatureSwap">; 154def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 155 AssemblerPredicate<"FeatureCondMov">; 156def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 157 AssemblerPredicate<"FeatureFPIdx">; 158def HasMips32 : Predicate<"Subtarget.hasMips32()">, 159 AssemblerPredicate<"FeatureMips32">; 160def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 161 AssemblerPredicate<"FeatureMips32r2">; 162def HasMips64 : Predicate<"Subtarget.hasMips64()">, 163 AssemblerPredicate<"FeatureMips64">; 164def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 165 AssemblerPredicate<"!FeatureMips64">; 166def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 167 AssemblerPredicate<"FeatureMips64r2">; 168def IsN64 : Predicate<"Subtarget.isABI_N64()">, 169 AssemblerPredicate<"FeatureN64">; 170def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 171 AssemblerPredicate<"!FeatureN64">; 172def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 173 AssemblerPredicate<"FeatureMips16">; 174def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 175 AssemblerPredicate<"FeatureMips32">; 176def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 177 AssemblerPredicate<"FeatureMips32">; 178def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 179 AssemblerPredicate<"FeatureMips32">; 180def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 181 AssemblerPredicate<"!FeatureMips16">; 182 183class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 184 let Predicates = [HasStdEnc]; 185} 186 187class IsCommutable { 188 bit isCommutable = 1; 189} 190 191class IsBranch { 192 bit isBranch = 1; 193} 194 195class IsReturn { 196 bit isReturn = 1; 197} 198 199class IsCall { 200 bit isCall = 1; 201} 202 203class IsTailCall { 204 bit isCall = 1; 205 bit isTerminator = 1; 206 bit isReturn = 1; 207 bit isBarrier = 1; 208 bit hasExtraSrcRegAllocReq = 1; 209 bit isCodeGenOnly = 1; 210} 211 212class IsAsCheapAsAMove { 213 bit isAsCheapAsAMove = 1; 214} 215 216class NeverHasSideEffects { 217 bit neverHasSideEffects = 1; 218} 219 220//===----------------------------------------------------------------------===// 221// Instruction format superclass 222//===----------------------------------------------------------------------===// 223 224include "MipsInstrFormats.td" 225 226//===----------------------------------------------------------------------===// 227// Mips Operand, Complex Patterns and Transformations Definitions. 228//===----------------------------------------------------------------------===// 229 230// Instruction operand types 231def jmptarget : Operand<OtherVT> { 232 let EncoderMethod = "getJumpTargetOpValue"; 233} 234def brtarget : Operand<OtherVT> { 235 let EncoderMethod = "getBranchTargetOpValue"; 236 let OperandType = "OPERAND_PCREL"; 237 let DecoderMethod = "DecodeBranchTarget"; 238} 239def calltarget : Operand<iPTR> { 240 let EncoderMethod = "getJumpTargetOpValue"; 241} 242def calltarget64: Operand<i64>; 243def simm16 : Operand<i32> { 244 let DecoderMethod= "DecodeSimm16"; 245} 246 247def simm20 : Operand<i32> { 248} 249 250def simm16_64 : Operand<i64>; 251def shamt : Operand<i32>; 252 253// Unsigned Operand 254def uimm16 : Operand<i32> { 255 let PrintMethod = "printUnsignedImm"; 256} 257 258def MipsMemAsmOperand : AsmOperandClass { 259 let Name = "Mem"; 260 let ParserMethod = "parseMemOperand"; 261} 262 263// Address operand 264def mem : Operand<i32> { 265 let PrintMethod = "printMemOperand"; 266 let MIOperandInfo = (ops CPURegs, simm16); 267 let EncoderMethod = "getMemEncoding"; 268 let ParserMatchClass = MipsMemAsmOperand; 269 let OperandType = "OPERAND_MEMORY"; 270} 271 272def mem64 : Operand<i64> { 273 let PrintMethod = "printMemOperand"; 274 let MIOperandInfo = (ops CPU64Regs, simm16_64); 275 let EncoderMethod = "getMemEncoding"; 276 let ParserMatchClass = MipsMemAsmOperand; 277 let OperandType = "OPERAND_MEMORY"; 278} 279 280def mem_ea : Operand<i32> { 281 let PrintMethod = "printMemOperandEA"; 282 let MIOperandInfo = (ops CPURegs, simm16); 283 let EncoderMethod = "getMemEncoding"; 284 let OperandType = "OPERAND_MEMORY"; 285} 286 287def mem_ea_64 : Operand<i64> { 288 let PrintMethod = "printMemOperandEA"; 289 let MIOperandInfo = (ops CPU64Regs, simm16_64); 290 let EncoderMethod = "getMemEncoding"; 291 let OperandType = "OPERAND_MEMORY"; 292} 293 294// size operand of ext instruction 295def size_ext : Operand<i32> { 296 let EncoderMethod = "getSizeExtEncoding"; 297 let DecoderMethod = "DecodeExtSize"; 298} 299 300// size operand of ins instruction 301def size_ins : Operand<i32> { 302 let EncoderMethod = "getSizeInsEncoding"; 303 let DecoderMethod = "DecodeInsSize"; 304} 305 306// Transformation Function - get the lower 16 bits. 307def LO16 : SDNodeXForm<imm, [{ 308 return getImm(N, N->getZExtValue() & 0xFFFF); 309}]>; 310 311// Transformation Function - get the higher 16 bits. 312def HI16 : SDNodeXForm<imm, [{ 313 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 314}]>; 315 316// Plus 1. 317def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 318 319// Node immediate fits as 16-bit sign extended on target immediate. 320// e.g. addi, andi 321def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 322 323// Node immediate fits as 16-bit sign extended on target immediate. 324// e.g. addi, andi 325def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 326 327// Node immediate fits as 15-bit sign extended on target immediate. 328// e.g. addi, andi 329def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 330 331// Node immediate fits as 16-bit zero extended on target immediate. 332// The LO16 param means that only the lower 16 bits of the node 333// immediate are caught. 334// e.g. addiu, sltiu 335def immZExt16 : PatLeaf<(imm), [{ 336 if (N->getValueType(0) == MVT::i32) 337 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 338 else 339 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 340}], LO16>; 341 342// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 343def immLow16Zero : PatLeaf<(imm), [{ 344 int64_t Val = N->getSExtValue(); 345 return isInt<32>(Val) && !(Val & 0xffff); 346}]>; 347 348// shamt field must fit in 5 bits. 349def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 350 351// True if (N + 1) fits in 16-bit field. 352def immSExt16Plus1 : PatLeaf<(imm), [{ 353 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 354}]>; 355 356// Mips Address Mode! SDNode frameindex could possibily be a match 357// since load and store instructions from stack used it. 358def addr : 359 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 360 361def addrRegImm : 362 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 363 364def addrDefault : 365 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 366 367//===----------------------------------------------------------------------===// 368// Instructions specific format 369//===----------------------------------------------------------------------===// 370 371// Arithmetic and logical instructions with 3 register operands. 372class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 373 InstrItinClass Itin = NoItinerary, 374 SDPatternOperator OpNode = null_frag>: 375 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 376 !strconcat(opstr, "\t$rd, $rs, $rt"), 377 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { 378 let isCommutable = isComm; 379 let isReMaterializable = 1; 380 string BaseOpcode; 381 string Arch; 382} 383 384// Arithmetic and logical instructions with 2 register operands. 385class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 386 SDPatternOperator imm_type = null_frag, 387 SDPatternOperator OpNode = null_frag> : 388 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 389 !strconcat(opstr, "\t$rt, $rs, $imm16"), 390 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> { 391 let isReMaterializable = 1; 392} 393 394// Arithmetic Multiply ADD/SUB 395class MArithR<string opstr, bit isComm = 0> : 396 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 397 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> { 398 let Defs = [HI, LO]; 399 let Uses = [HI, LO]; 400 let isCommutable = isComm; 401} 402 403// Logical 404class LogicNOR<string opstr, RegisterOperand RC>: 405 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 406 !strconcat(opstr, "\t$rd, $rs, $rt"), 407 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 408 let isCommutable = 1; 409} 410 411// Shifts 412class shift_rotate_imm<string opstr, Operand ImmOpnd, 413 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 414 SDPatternOperator PF = null_frag> : 415 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 416 !strconcat(opstr, "\t$rd, $rt, $shamt"), 417 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 418 419class shift_rotate_reg<string opstr, RegisterOperand RC, 420 SDPatternOperator OpNode = null_frag>: 421 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 422 !strconcat(opstr, "\t$rd, $rt, $rs"), 423 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>; 424 425// Load Upper Imediate 426class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 427 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 428 [], IIAlu, FrmI>, IsAsCheapAsAMove { 429 let neverHasSideEffects = 1; 430 let isReMaterializable = 1; 431} 432 433class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 434 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 435 bits<21> addr; 436 let Inst{25-21} = addr{20-16}; 437 let Inst{15-0} = addr{15-0}; 438 let DecoderMethod = "DecodeMem"; 439} 440 441// Memory Load/Store 442class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 443 Operand MemOpnd> : 444 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 445 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 446 let DecoderMethod = "DecodeMem"; 447 let canFoldAsLoad = 1; 448 let mayLoad = 1; 449} 450 451class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 452 Operand MemOpnd> : 453 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 454 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 455 let DecoderMethod = "DecodeMem"; 456 let mayStore = 1; 457} 458 459multiclass LoadM<string opstr, RegisterClass RC, 460 SDPatternOperator OpNode = null_frag> { 461 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 462 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 463 let DecoderNamespace = "Mips64"; 464 let isCodeGenOnly = 1; 465 } 466} 467 468multiclass StoreM<string opstr, RegisterClass RC, 469 SDPatternOperator OpNode = null_frag> { 470 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 471 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 472 let DecoderNamespace = "Mips64"; 473 let isCodeGenOnly = 1; 474 } 475} 476 477// Load/Store Left/Right 478let canFoldAsLoad = 1 in 479class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 480 Operand MemOpnd> : 481 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 482 !strconcat(opstr, "\t$rt, $addr"), 483 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 484 let DecoderMethod = "DecodeMem"; 485 string Constraints = "$src = $rt"; 486} 487 488class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 489 Operand MemOpnd>: 490 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 491 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 492 let DecoderMethod = "DecodeMem"; 493} 494 495multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 496 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 497 Requires<[NotN64, HasStdEnc]>; 498 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 499 Requires<[IsN64, HasStdEnc]> { 500 let DecoderNamespace = "Mips64"; 501 let isCodeGenOnly = 1; 502 } 503} 504 505multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 506 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 507 Requires<[NotN64, HasStdEnc]>; 508 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 509 Requires<[IsN64, HasStdEnc]> { 510 let DecoderNamespace = "Mips64"; 511 let isCodeGenOnly = 1; 512 } 513} 514 515// Conditional Branch 516class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 517 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 518 !strconcat(opstr, "\t$rs, $rt, $offset"), 519 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 520 FrmI> { 521 let isBranch = 1; 522 let isTerminator = 1; 523 let hasDelaySlot = 1; 524 let Defs = [AT]; 525} 526 527class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 528 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 529 !strconcat(opstr, "\t$rs, $offset"), 530 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 531 let isBranch = 1; 532 let isTerminator = 1; 533 let hasDelaySlot = 1; 534 let Defs = [AT]; 535} 536 537// SetCC 538class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 539 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 540 !strconcat(opstr, "\t$rd, $rs, $rt"), 541 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 542 543class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 544 RegisterClass RC>: 545 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 546 !strconcat(opstr, "\t$rt, $rs, $imm16"), 547 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 548 IIAlu, FrmI>; 549 550// Jump 551class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 552 SDPatternOperator targetoperator> : 553 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 554 [(operator targetoperator:$target)], IIBranch, FrmJ> { 555 let isTerminator=1; 556 let isBarrier=1; 557 let hasDelaySlot = 1; 558 let DecoderMethod = "DecodeJumpTarget"; 559 let Defs = [AT]; 560} 561 562// Unconditional branch 563class UncondBranch<string opstr> : 564 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 565 [(br bb:$offset)], IIBranch, FrmI> { 566 let isBranch = 1; 567 let isTerminator = 1; 568 let isBarrier = 1; 569 let hasDelaySlot = 1; 570 let Predicates = [RelocPIC, HasStdEnc]; 571 let Defs = [AT]; 572} 573 574// Base class for indirect branch and return instruction classes. 575let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 576class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 577 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 578 579// Indirect branch 580class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 581 let isBranch = 1; 582 let isIndirectBranch = 1; 583} 584 585// Return instruction 586class RetBase<RegisterClass RC>: JumpFR<RC> { 587 let isReturn = 1; 588 let isCodeGenOnly = 1; 589 let hasCtrlDep = 1; 590 let hasExtraSrcRegAllocReq = 1; 591} 592 593// Jump and Link (Call) 594let isCall=1, hasDelaySlot=1, Defs = [RA] in { 595 class JumpLink<string opstr> : 596 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 597 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 598 let DecoderMethod = "DecodeJumpTarget"; 599 } 600 601 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 602 Register RetReg>: 603 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 604 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 605 606 class JumpLinkReg<string opstr, RegisterClass RC>: 607 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 608 [], IIBranch, FrmR>; 609 610 class BGEZAL_FT<string opstr, RegisterOperand RO> : 611 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 612 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 613 614} 615 616class BAL_FT : 617 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 618 let isBranch = 1; 619 let isTerminator = 1; 620 let isBarrier = 1; 621 let hasDelaySlot = 1; 622 let Defs = [RA]; 623} 624 625// Sync 626let hasSideEffects = 1 in 627class SYNC_FT : 628 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 629 NoItinerary, FrmOther>; 630 631// Mul, Div 632class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 633 list<Register> DefRegs> : 634 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 635 itin, FrmR> { 636 let isCommutable = 1; 637 let Defs = DefRegs; 638 let neverHasSideEffects = 1; 639} 640 641// Pseudo multiply/divide instruction with explicit accumulator register 642// operands. 643class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 644 SDPatternOperator OpNode, InstrItinClass Itin, 645 bit IsComm = 1, bit HasSideEffects = 0> : 646 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 647 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 648 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 649 let isCommutable = IsComm; 650 let hasSideEffects = HasSideEffects; 651} 652 653// Pseudo multiply add/sub instruction with explicit accumulator register 654// operands. 655class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 656 : PseudoSE<(outs ACRegs:$ac), 657 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin), 658 [(set ACRegs:$ac, 659 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))], 660 IIImul>, 661 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> { 662 string Constraints = "$acin = $ac"; 663} 664 665class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 666 list<Register> DefRegs> : 667 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 668 [], itin, FrmR> { 669 let Defs = DefRegs; 670} 671 672// Move from Hi/Lo 673class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 674 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 675 let Uses = UseRegs; 676 let neverHasSideEffects = 1; 677} 678 679class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 680 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 681 let Defs = DefRegs; 682 let neverHasSideEffects = 1; 683} 684 685class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 686 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 687 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 688 let isCodeGenOnly = 1; 689 let DecoderMethod = "DecodeMem"; 690} 691 692// Count Leading Ones/Zeros in Word 693class CountLeading0<string opstr, RegisterOperand RO>: 694 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 695 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 696 Requires<[HasBitCount, HasStdEnc]>; 697 698class CountLeading1<string opstr, RegisterOperand RO>: 699 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 700 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 701 Requires<[HasBitCount, HasStdEnc]>; 702 703 704// Sign Extend in Register. 705class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 706 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 707 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 708 let Predicates = [HasSEInReg, HasStdEnc]; 709} 710 711// Subword Swap 712class SubwordSwap<string opstr, RegisterOperand RO>: 713 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 714 NoItinerary, FrmR> { 715 let Predicates = [HasSwap, HasStdEnc]; 716 let neverHasSideEffects = 1; 717} 718 719// Read Hardware 720class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 721 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 722 IIAlu, FrmR>; 723 724// Ext and Ins 725class ExtBase<string opstr, RegisterOperand RO>: 726 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 727 !strconcat(opstr, " $rt, $rs, $pos, $size"), 728 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 729 FrmR> { 730 let Predicates = [HasMips32r2, HasStdEnc]; 731} 732 733class InsBase<string opstr, RegisterOperand RO>: 734 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 735 !strconcat(opstr, " $rt, $rs, $pos, $size"), 736 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 737 NoItinerary, FrmR> { 738 let Predicates = [HasMips32r2, HasStdEnc]; 739 let Constraints = "$src = $rt"; 740} 741 742// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 743class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 744 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 745 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 746 747multiclass Atomic2Ops32<PatFrag Op> { 748 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 749 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 750 Requires<[IsN64, HasStdEnc]> { 751 let DecoderNamespace = "Mips64"; 752 } 753} 754 755// Atomic Compare & Swap. 756class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 757 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 758 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 759 760multiclass AtomicCmpSwap32<PatFrag Op> { 761 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 762 Requires<[NotN64, HasStdEnc]>; 763 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 764 Requires<[IsN64, HasStdEnc]> { 765 let DecoderNamespace = "Mips64"; 766 } 767} 768 769class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 770 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 771 [], NoItinerary, FrmI> { 772 let DecoderMethod = "DecodeMem"; 773 let mayLoad = 1; 774} 775 776class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 777 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 778 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 779 let DecoderMethod = "DecodeMem"; 780 let mayStore = 1; 781 let Constraints = "$rt = $dst"; 782} 783 784class MFC3OP<dag outs, dag ins, string asmstr> : 785 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 786 787//===----------------------------------------------------------------------===// 788// Pseudo instructions 789//===----------------------------------------------------------------------===// 790 791// Return RA. 792let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 793def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 794 795let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 796def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 797 [(callseq_start timm:$amt)]>; 798def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 799 [(callseq_end timm:$amt1, timm:$amt2)]>; 800} 801 802let usesCustomInserter = 1 in { 803 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 804 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 805 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 806 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 807 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 808 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 809 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 810 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 811 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 812 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 813 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 814 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 815 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 816 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 817 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 818 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 819 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 820 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 821 822 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 823 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 824 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 825 826 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 827 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 828 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 829} 830 831/// Pseudo instructions for loading, storing and copying accumulator registers. 832let isPseudo = 1 in { 833 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>; 834 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>; 835} 836 837def COPY_AC64 : PseudoSE<(outs ACRegs:$dst), (ins ACRegs:$src), []>; 838 839//===----------------------------------------------------------------------===// 840// Instruction definition 841//===----------------------------------------------------------------------===// 842//===----------------------------------------------------------------------===// 843// MipsI Instructions 844//===----------------------------------------------------------------------===// 845 846/// Arithmetic Instructions (ALU Immediate) 847def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 848 ADDI_FM<0x9>, IsAsCheapAsAMove; 849def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 850def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 851def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 852def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 853 ADDI_FM<0xc>; 854def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 855 ADDI_FM<0xd>; 856def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 857 ADDI_FM<0xe>; 858def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 859 860/// Arithmetic Instructions (3-Operand, R-Type) 861def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>; 862def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 863def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 864def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 865def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 866def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 867def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 868def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 869def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 870def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 871def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 872 873/// Shift Instructions 874def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 875 SRA_FM<0, 0>; 876def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 877 SRA_FM<2, 0>; 878def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 879 SRA_FM<3, 0>; 880def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 881def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 882def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 883 884// Rotate Instructions 885let Predicates = [HasMips32r2, HasStdEnc] in { 886 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>, 887 SRA_FM<2, 1>; 888 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>; 889} 890 891/// Load and Store Instructions 892/// aligned 893defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 894defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; 895defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; 896defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 897defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; 898defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 899defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 900defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 901 902/// load/store left/right 903defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 904defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 905defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 906defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 907 908def SYNC : SYNC_FT, SYNC_FM; 909 910/// Load-linked, Store-conditional 911let Predicates = [NotN64, HasStdEnc] in { 912 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 913 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 914} 915 916let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 917 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 918 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 919} 920 921/// Jump and Branch Instructions 922def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 923 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 924def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 925def B : UncondBranch<"b">, B_FM; 926def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 927def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 928def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 929def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 930def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 931def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 932 933def BAL_BR: BAL_FT, BAL_FM; 934 935def JAL : JumpLink<"jal">, FJ<3>; 936def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 937def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 938def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 939def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 940def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 941def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 942 943def RET : RetBase<CPURegs>, MTLO_FM<8>; 944 945// Exception handling related node and instructions. 946// The conversion sequence is: 947// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 948// MIPSeh_return -> (stack change + indirect branch) 949// 950// MIPSeh_return takes the place of regular return instruction 951// but takes two arguments (V1, V0) which are used for storing 952// the offset and return address respectively. 953def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 954 955def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 956 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 957 958let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 959 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 960 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 961 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 962 CPU64Regs:$dst), 963 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 964} 965 966/// Multiply and Divide Instructions. 967def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>; 968def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>; 969def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>; 970def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>; 971def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>; 972def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>; 973def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 0>; 974def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv, 975 0>; 976 977def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 978def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 979def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 980def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 981 982/// Sign Ext In Register Instructions. 983def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 984def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 985 986/// Count Leading 987def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 988def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 989 990/// Word Swap Bytes Within Halfwords 991def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 992 993/// No operation. 994def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 995 996// FrameIndexes are legalized when they are operands from load/store 997// instructions. The same not happens for stack address copies, so an 998// add op with mem ComplexPattern is used and the stack address copy 999// can be matched. It's similar to Sparc LEA_ADDRi 1000def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 1001 1002// MADD*/MSUB* 1003def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1004def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1005def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1006def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1007def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1008def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1009def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1010def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1011 1012def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 1013 1014def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 1015def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 1016 1017/// Move Control Registers From/To CPU Registers 1018def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1019 (ins CPURegsOpnd:$rd, uimm16:$sel), 1020 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 1021 1022def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1023 (ins CPURegsOpnd:$rt), 1024 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 1025 1026def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1027 (ins CPURegsOpnd:$rd, uimm16:$sel), 1028 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 1029 1030def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1031 (ins CPURegsOpnd:$rt), 1032 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 1033 1034//===----------------------------------------------------------------------===// 1035// Instruction aliases 1036//===----------------------------------------------------------------------===// 1037def : InstAlias<"move $dst, $src", 1038 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1039 Requires<[NotMips64]>; 1040def : InstAlias<"move $dst, $src", 1041 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1042 Requires<[NotMips64]>; 1043def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 1044def : InstAlias<"addu $rs, $rt, $imm", 1045 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1046def : InstAlias<"add $rs, $rt, $imm", 1047 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1048def : InstAlias<"and $rs, $rt, $imm", 1049 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1050def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1051 Requires<[NotMips64]>; 1052def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1053def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1054def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1055 Requires<[NotMips64]>; 1056def : InstAlias<"not $rt, $rs", 1057 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1058def : InstAlias<"neg $rt, $rs", 1059 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1060def : InstAlias<"negu $rt, $rs", 1061 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1062def : InstAlias<"slt $rs, $rt, $imm", 1063 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1064def : InstAlias<"xor $rs, $rt, $imm", 1065 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 1066 Requires<[NotMips64]>; 1067def : InstAlias<"or $rs, $rt, $imm", 1068 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 1069 Requires<[NotMips64]>; 1070def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1071def : InstAlias<"mfc0 $rt, $rd", 1072 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1073def : InstAlias<"mtc0 $rt, $rd", 1074 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1075def : InstAlias<"mfc2 $rt, $rd", 1076 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1077def : InstAlias<"mtc2 $rt, $rd", 1078 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1079 1080//===----------------------------------------------------------------------===// 1081// Assembler Pseudo Instructions 1082//===----------------------------------------------------------------------===// 1083 1084class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1085 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1086 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1087def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1088 1089class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1090 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1091 !strconcat(instr_asm, "\t$rt, $addr")> ; 1092def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1093 1094class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1095 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1096 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1097def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1098 1099 1100 1101//===----------------------------------------------------------------------===// 1102// Arbitrary patterns that map to one or more instructions 1103//===----------------------------------------------------------------------===// 1104 1105// Load/store pattern templates. 1106class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1107 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1108 1109class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1110 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1111 1112// Small immediates 1113def : MipsPat<(i32 immSExt16:$in), 1114 (ADDiu ZERO, imm:$in)>; 1115def : MipsPat<(i32 immZExt16:$in), 1116 (ORi ZERO, imm:$in)>; 1117def : MipsPat<(i32 immLow16Zero:$in), 1118 (LUi (HI16 imm:$in))>; 1119 1120// Arbitrary immediates 1121def : MipsPat<(i32 imm:$imm), 1122 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1123 1124// Carry MipsPatterns 1125def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1126 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1127def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1128 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1129def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1130 (ADDiu CPURegs:$src, imm:$imm)>; 1131 1132// Call 1133def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1134 (JAL tglobaladdr:$dst)>; 1135def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1136 (JAL texternalsym:$dst)>; 1137//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1138// (JALR CPURegs:$dst)>; 1139 1140// Tail call 1141def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1142 (TAILCALL tglobaladdr:$dst)>; 1143def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1144 (TAILCALL texternalsym:$dst)>; 1145// hi/lo relocs 1146def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1147def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1148def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1149def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1150def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1151def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1152 1153def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1154def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1155def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1156def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1157def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1158def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1159 1160def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1161 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1162def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1163 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1164def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1165 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1166def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1167 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1168def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1169 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1170 1171// gp_rel relocs 1172def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1173 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1174def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1175 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1176 1177// wrapper_pic 1178class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1179 MipsPat<(MipsWrapper RC:$gp, node:$in), 1180 (ADDiuOp RC:$gp, node:$in)>; 1181 1182def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1183def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1184def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1185def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1186def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1187def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1188 1189// Mips does not have "not", so we expand our way 1190def : MipsPat<(not CPURegs:$in), 1191 (NOR CPURegsOpnd:$in, ZERO)>; 1192 1193// extended loads 1194let Predicates = [NotN64, HasStdEnc] in { 1195 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1196 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1197 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1198} 1199let Predicates = [IsN64, HasStdEnc] in { 1200 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1201 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1202 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1203} 1204 1205// peepholes 1206let Predicates = [NotN64, HasStdEnc] in { 1207 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1208} 1209let Predicates = [IsN64, HasStdEnc] in { 1210 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1211} 1212 1213// brcond patterns 1214multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1215 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1216 Instruction SLTiuOp, Register ZEROReg> { 1217def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1218 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1219def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1220 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1221 1222def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1223 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1224def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1225 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1226def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1227 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1228def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1229 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1230 1231def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1232 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1233def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1234 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1235 1236def : MipsPat<(brcond RC:$cond, bb:$dst), 1237 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1238} 1239 1240defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1241 1242// setcc patterns 1243multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1244 Instruction SLTuOp, Register ZEROReg> { 1245 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1246 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1247 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1248 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1249} 1250 1251multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1252 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1253 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1254 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1255 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1256} 1257 1258multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1259 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1260 (SLTOp RC:$rhs, RC:$lhs)>; 1261 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1262 (SLTuOp RC:$rhs, RC:$lhs)>; 1263} 1264 1265multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1266 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1267 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1268 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1269 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1270} 1271 1272multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1273 Instruction SLTiuOp> { 1274 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1275 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1276 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1277 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1278} 1279 1280defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1281defm : SetlePats<CPURegs, SLT, SLTu>; 1282defm : SetgtPats<CPURegs, SLT, SLTu>; 1283defm : SetgePats<CPURegs, SLT, SLTu>; 1284defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1285 1286// bswap pattern 1287def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1288 1289// mflo/hi patterns. 1290def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)), 1291 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>; 1292 1293//===----------------------------------------------------------------------===// 1294// Floating Point Support 1295//===----------------------------------------------------------------------===// 1296 1297include "MipsInstrFPU.td" 1298include "Mips64InstrInfo.td" 1299include "MipsCondMov.td" 1300 1301// 1302// Mips16 1303 1304include "Mips16InstrFormats.td" 1305include "Mips16InstrInfo.td" 1306 1307// DSP 1308include "MipsDSPInstrFormats.td" 1309include "MipsDSPInstrInfo.td" 1310 1311