MipsInstrInfo.td revision 2cd7d3f9ce034ecc4ef4d6fa8fc7dac06f0c708f
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 76 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 77 78// These are target-independent nodes, but have target-specific formats. 79def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 80 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 81def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 82 [SDNPHasChain, SDNPSideEffect, 83 SDNPOptInGlue, SDNPOutGlue]>; 84 85// MAdd*/MSub* nodes 86def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 87 [SDNPOptInGlue, SDNPOutGlue]>; 88def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 89 [SDNPOptInGlue, SDNPOutGlue]>; 90def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 91 [SDNPOptInGlue, SDNPOutGlue]>; 92def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 93 [SDNPOptInGlue, SDNPOutGlue]>; 94 95// DivRem(u) nodes 96def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 97 [SDNPOutGlue]>; 98def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 99 [SDNPOutGlue]>; 100 101// Target constant nodes that are not part of any isel patterns and remain 102// unchanged can cause instructions with illegal operands to be emitted. 103// Wrapper node patterns give the instruction selector a chance to replace 104// target constant nodes that would otherwise remain unchanged with ADDiu 105// nodes. Without these wrapper node patterns, the following conditional move 106// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 107// compiled: 108// movn %got(d)($gp), %got(c)($gp), $4 109// This instruction is illegal since movn can take only register operands. 110 111def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 112 113def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 114 115def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 116def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 117 118def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 120def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 122def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 124def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 126def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 128def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 132def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134 135//===----------------------------------------------------------------------===// 136// Mips Instruction Predicate Definitions. 137//===----------------------------------------------------------------------===// 138def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 139 AssemblerPredicate<"FeatureSEInReg">; 140def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 141 AssemblerPredicate<"FeatureBitCount">; 142def HasSwap : Predicate<"Subtarget.hasSwap()">, 143 AssemblerPredicate<"FeatureSwap">; 144def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 145 AssemblerPredicate<"FeatureCondMov">; 146def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 147 AssemblerPredicate<"FeatureFPIdx">; 148def HasMips32 : Predicate<"Subtarget.hasMips32()">, 149 AssemblerPredicate<"FeatureMips32">; 150def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 151 AssemblerPredicate<"FeatureMips32r2">; 152def HasMips64 : Predicate<"Subtarget.hasMips64()">, 153 AssemblerPredicate<"FeatureMips64">; 154def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 155 AssemblerPredicate<"!FeatureMips64">; 156def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 157 AssemblerPredicate<"FeatureMips64r2">; 158def IsN64 : Predicate<"Subtarget.isABI_N64()">, 159 AssemblerPredicate<"FeatureN64">; 160def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 161 AssemblerPredicate<"!FeatureN64">; 162def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 163 AssemblerPredicate<"FeatureMips16">; 164def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 165 AssemblerPredicate<"FeatureMips32">; 166def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 167 AssemblerPredicate<"FeatureMips32">; 168def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 169 AssemblerPredicate<"FeatureMips32">; 170def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 171 AssemblerPredicate<"!FeatureMips16">; 172 173class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 174 let Predicates = [HasStdEnc]; 175} 176 177class IsCommutable { 178 bit isCommutable = 1; 179} 180 181class IsBranch { 182 bit isBranch = 1; 183} 184 185class IsReturn { 186 bit isReturn = 1; 187} 188 189class IsCall { 190 bit isCall = 1; 191} 192 193class IsTailCall { 194 bit isCall = 1; 195 bit isTerminator = 1; 196 bit isReturn = 1; 197 bit isBarrier = 1; 198 bit hasExtraSrcRegAllocReq = 1; 199 bit isCodeGenOnly = 1; 200} 201 202class IsAsCheapAsAMove { 203 bit isAsCheapAsAMove = 1; 204} 205 206class NeverHasSideEffects { 207 bit neverHasSideEffects = 1; 208} 209 210//===----------------------------------------------------------------------===// 211// Instruction format superclass 212//===----------------------------------------------------------------------===// 213 214include "MipsInstrFormats.td" 215 216//===----------------------------------------------------------------------===// 217// Mips Operand, Complex Patterns and Transformations Definitions. 218//===----------------------------------------------------------------------===// 219 220// Instruction operand types 221def jmptarget : Operand<OtherVT> { 222 let EncoderMethod = "getJumpTargetOpValue"; 223} 224def brtarget : Operand<OtherVT> { 225 let EncoderMethod = "getBranchTargetOpValue"; 226 let OperandType = "OPERAND_PCREL"; 227 let DecoderMethod = "DecodeBranchTarget"; 228} 229def calltarget : Operand<iPTR> { 230 let EncoderMethod = "getJumpTargetOpValue"; 231} 232def calltarget64: Operand<i64>; 233def simm16 : Operand<i32> { 234 let DecoderMethod= "DecodeSimm16"; 235} 236 237def simm20 : Operand<i32> { 238} 239 240def simm16_64 : Operand<i64>; 241def shamt : Operand<i32>; 242 243// Unsigned Operand 244def uimm16 : Operand<i32> { 245 let PrintMethod = "printUnsignedImm"; 246} 247 248def MipsMemAsmOperand : AsmOperandClass { 249 let Name = "Mem"; 250 let ParserMethod = "parseMemOperand"; 251} 252 253// Address operand 254def mem : Operand<i32> { 255 let PrintMethod = "printMemOperand"; 256 let MIOperandInfo = (ops CPURegs, simm16); 257 let EncoderMethod = "getMemEncoding"; 258 let ParserMatchClass = MipsMemAsmOperand; 259 let OperandType = "OPERAND_MEMORY"; 260} 261 262def mem64 : Operand<i64> { 263 let PrintMethod = "printMemOperand"; 264 let MIOperandInfo = (ops CPU64Regs, simm16_64); 265 let EncoderMethod = "getMemEncoding"; 266 let ParserMatchClass = MipsMemAsmOperand; 267 let OperandType = "OPERAND_MEMORY"; 268} 269 270def mem_ea : Operand<i32> { 271 let PrintMethod = "printMemOperandEA"; 272 let MIOperandInfo = (ops CPURegs, simm16); 273 let EncoderMethod = "getMemEncoding"; 274 let OperandType = "OPERAND_MEMORY"; 275} 276 277def mem_ea_64 : Operand<i64> { 278 let PrintMethod = "printMemOperandEA"; 279 let MIOperandInfo = (ops CPU64Regs, simm16_64); 280 let EncoderMethod = "getMemEncoding"; 281 let OperandType = "OPERAND_MEMORY"; 282} 283 284// size operand of ext instruction 285def size_ext : Operand<i32> { 286 let EncoderMethod = "getSizeExtEncoding"; 287 let DecoderMethod = "DecodeExtSize"; 288} 289 290// size operand of ins instruction 291def size_ins : Operand<i32> { 292 let EncoderMethod = "getSizeInsEncoding"; 293 let DecoderMethod = "DecodeInsSize"; 294} 295 296// Transformation Function - get the lower 16 bits. 297def LO16 : SDNodeXForm<imm, [{ 298 return getImm(N, N->getZExtValue() & 0xFFFF); 299}]>; 300 301// Transformation Function - get the higher 16 bits. 302def HI16 : SDNodeXForm<imm, [{ 303 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 304}]>; 305 306// Plus 1. 307def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 308 309// Node immediate fits as 16-bit sign extended on target immediate. 310// e.g. addi, andi 311def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 312 313// Node immediate fits as 16-bit sign extended on target immediate. 314// e.g. addi, andi 315def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 316 317// Node immediate fits as 15-bit sign extended on target immediate. 318// e.g. addi, andi 319def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 320 321// Node immediate fits as 16-bit zero extended on target immediate. 322// The LO16 param means that only the lower 16 bits of the node 323// immediate are caught. 324// e.g. addiu, sltiu 325def immZExt16 : PatLeaf<(imm), [{ 326 if (N->getValueType(0) == MVT::i32) 327 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 328 else 329 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 330}], LO16>; 331 332// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 333def immLow16Zero : PatLeaf<(imm), [{ 334 int64_t Val = N->getSExtValue(); 335 return isInt<32>(Val) && !(Val & 0xffff); 336}]>; 337 338// shamt field must fit in 5 bits. 339def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 340 341// True if (N + 1) fits in 16-bit field. 342def immSExt16Plus1 : PatLeaf<(imm), [{ 343 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 344}]>; 345 346// Mips Address Mode! SDNode frameindex could possibily be a match 347// since load and store instructions from stack used it. 348def addr : 349 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 350 351def addrRegImm : 352 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 353 354def addrDefault : 355 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 356 357//===----------------------------------------------------------------------===// 358// Instructions specific format 359//===----------------------------------------------------------------------===// 360 361// Arithmetic and logical instructions with 3 register operands. 362class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 363 InstrItinClass Itin = NoItinerary, 364 SDPatternOperator OpNode = null_frag>: 365 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 366 !strconcat(opstr, "\t$rd, $rs, $rt"), 367 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { 368 let isCommutable = isComm; 369 let isReMaterializable = 1; 370 string BaseOpcode; 371 string Arch; 372} 373 374// Arithmetic and logical instructions with 2 register operands. 375class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 376 SDPatternOperator imm_type = null_frag, 377 SDPatternOperator OpNode = null_frag> : 378 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 379 !strconcat(opstr, "\t$rt, $rs, $imm16"), 380 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> { 381 let isReMaterializable = 1; 382} 383 384// Arithmetic Multiply ADD/SUB 385class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> : 386 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 387 !strconcat(opstr, "\t$rs, $rt"), 388 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> { 389 let Defs = [HI, LO]; 390 let Uses = [HI, LO]; 391 let isCommutable = isComm; 392} 393 394// Logical 395class LogicNOR<string opstr, RegisterOperand RC>: 396 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 397 !strconcat(opstr, "\t$rd, $rs, $rt"), 398 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 399 let isCommutable = 1; 400} 401 402// Shifts 403class shift_rotate_imm<string opstr, Operand ImmOpnd, 404 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 405 SDPatternOperator PF = null_frag> : 406 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 407 !strconcat(opstr, "\t$rd, $rt, $shamt"), 408 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 409 410class shift_rotate_reg<string opstr, RegisterOperand RC, 411 SDPatternOperator OpNode = null_frag>: 412 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 413 !strconcat(opstr, "\t$rd, $rt, $rs"), 414 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>; 415 416// Load Upper Imediate 417class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 418 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 419 [], IIAlu, FrmI>, IsAsCheapAsAMove { 420 let neverHasSideEffects = 1; 421 let isReMaterializable = 1; 422} 423 424class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 425 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 426 bits<21> addr; 427 let Inst{25-21} = addr{20-16}; 428 let Inst{15-0} = addr{15-0}; 429 let DecoderMethod = "DecodeMem"; 430} 431 432// Memory Load/Store 433class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 434 Operand MemOpnd> : 435 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 436 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 437 let DecoderMethod = "DecodeMem"; 438 let canFoldAsLoad = 1; 439 let mayLoad = 1; 440} 441 442class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 443 Operand MemOpnd> : 444 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 445 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 446 let DecoderMethod = "DecodeMem"; 447 let mayStore = 1; 448} 449 450multiclass LoadM<string opstr, RegisterClass RC, 451 SDPatternOperator OpNode = null_frag> { 452 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 453 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 454 let DecoderNamespace = "Mips64"; 455 let isCodeGenOnly = 1; 456 } 457} 458 459multiclass StoreM<string opstr, RegisterClass RC, 460 SDPatternOperator OpNode = null_frag> { 461 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 462 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 463 let DecoderNamespace = "Mips64"; 464 let isCodeGenOnly = 1; 465 } 466} 467 468// Load/Store Left/Right 469let canFoldAsLoad = 1 in 470class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 471 Operand MemOpnd> : 472 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 473 !strconcat(opstr, "\t$rt, $addr"), 474 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 475 let DecoderMethod = "DecodeMem"; 476 string Constraints = "$src = $rt"; 477} 478 479class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 480 Operand MemOpnd>: 481 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 482 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 483 let DecoderMethod = "DecodeMem"; 484} 485 486multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 487 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 488 Requires<[NotN64, HasStdEnc]>; 489 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 490 Requires<[IsN64, HasStdEnc]> { 491 let DecoderNamespace = "Mips64"; 492 let isCodeGenOnly = 1; 493 } 494} 495 496multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 497 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 498 Requires<[NotN64, HasStdEnc]>; 499 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 500 Requires<[IsN64, HasStdEnc]> { 501 let DecoderNamespace = "Mips64"; 502 let isCodeGenOnly = 1; 503 } 504} 505 506// Conditional Branch 507class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 508 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 509 !strconcat(opstr, "\t$rs, $rt, $offset"), 510 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 511 FrmI> { 512 let isBranch = 1; 513 let isTerminator = 1; 514 let hasDelaySlot = 1; 515 let Defs = [AT]; 516} 517 518class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 519 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 520 !strconcat(opstr, "\t$rs, $offset"), 521 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 522 let isBranch = 1; 523 let isTerminator = 1; 524 let hasDelaySlot = 1; 525 let Defs = [AT]; 526} 527 528// SetCC 529class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 530 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 531 !strconcat(opstr, "\t$rd, $rs, $rt"), 532 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 533 534class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 535 RegisterClass RC>: 536 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 537 !strconcat(opstr, "\t$rt, $rs, $imm16"), 538 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 539 IIAlu, FrmI>; 540 541// Jump 542class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 543 SDPatternOperator targetoperator> : 544 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 545 [(operator targetoperator:$target)], IIBranch, FrmJ> { 546 let isTerminator=1; 547 let isBarrier=1; 548 let hasDelaySlot = 1; 549 let DecoderMethod = "DecodeJumpTarget"; 550 let Defs = [AT]; 551} 552 553// Unconditional branch 554class UncondBranch<string opstr> : 555 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 556 [(br bb:$offset)], IIBranch, FrmI> { 557 let isBranch = 1; 558 let isTerminator = 1; 559 let isBarrier = 1; 560 let hasDelaySlot = 1; 561 let Predicates = [RelocPIC, HasStdEnc]; 562 let Defs = [AT]; 563} 564 565// Base class for indirect branch and return instruction classes. 566let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 567class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 568 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 569 570// Indirect branch 571class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 572 let isBranch = 1; 573 let isIndirectBranch = 1; 574} 575 576// Return instruction 577class RetBase<RegisterClass RC>: JumpFR<RC> { 578 let isReturn = 1; 579 let isCodeGenOnly = 1; 580 let hasCtrlDep = 1; 581 let hasExtraSrcRegAllocReq = 1; 582} 583 584// Jump and Link (Call) 585let isCall=1, hasDelaySlot=1, Defs = [RA] in { 586 class JumpLink<string opstr> : 587 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 588 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 589 let DecoderMethod = "DecodeJumpTarget"; 590 } 591 592 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 593 Register RetReg>: 594 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 595 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 596 597 class JumpLinkReg<string opstr, RegisterClass RC>: 598 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 599 [], IIBranch, FrmR>; 600 601 class BGEZAL_FT<string opstr, RegisterOperand RO> : 602 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 603 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 604 605} 606 607class BAL_FT : 608 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 609 let isBranch = 1; 610 let isTerminator = 1; 611 let isBarrier = 1; 612 let hasDelaySlot = 1; 613 let Defs = [RA]; 614} 615 616// Sync 617let hasSideEffects = 1 in 618class SYNC_FT : 619 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 620 NoItinerary, FrmOther>; 621 622// Mul, Div 623class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 624 list<Register> DefRegs> : 625 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 626 itin, FrmR> { 627 let isCommutable = 1; 628 let Defs = DefRegs; 629 let neverHasSideEffects = 1; 630} 631 632class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO, 633 list<Register> DefRegs> : 634 InstSE<(outs), (ins RO:$rs, RO:$rt), 635 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin, 636 FrmR> { 637 let Defs = DefRegs; 638} 639 640// Move from Hi/Lo 641class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 642 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 643 let Uses = UseRegs; 644 let neverHasSideEffects = 1; 645} 646 647class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 648 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 649 let Defs = DefRegs; 650 let neverHasSideEffects = 1; 651} 652 653class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 654 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 655 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 656 let isCodeGenOnly = 1; 657 let DecoderMethod = "DecodeMem"; 658} 659 660// Count Leading Ones/Zeros in Word 661class CountLeading0<string opstr, RegisterOperand RO>: 662 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 663 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 664 Requires<[HasBitCount, HasStdEnc]>; 665 666class CountLeading1<string opstr, RegisterOperand RO>: 667 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 668 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 669 Requires<[HasBitCount, HasStdEnc]>; 670 671 672// Sign Extend in Register. 673class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 674 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 675 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 676 let Predicates = [HasSEInReg, HasStdEnc]; 677} 678 679// Subword Swap 680class SubwordSwap<string opstr, RegisterOperand RO>: 681 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 682 NoItinerary, FrmR> { 683 let Predicates = [HasSwap, HasStdEnc]; 684 let neverHasSideEffects = 1; 685} 686 687// Read Hardware 688class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 689 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 690 IIAlu, FrmR>; 691 692// Ext and Ins 693class ExtBase<string opstr, RegisterOperand RO>: 694 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 695 !strconcat(opstr, " $rt, $rs, $pos, $size"), 696 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 697 FrmR> { 698 let Predicates = [HasMips32r2, HasStdEnc]; 699} 700 701class InsBase<string opstr, RegisterOperand RO>: 702 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 703 !strconcat(opstr, " $rt, $rs, $pos, $size"), 704 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 705 NoItinerary, FrmR> { 706 let Predicates = [HasMips32r2, HasStdEnc]; 707 let Constraints = "$src = $rt"; 708} 709 710// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 711class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 712 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 713 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 714 715multiclass Atomic2Ops32<PatFrag Op> { 716 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 717 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 718 Requires<[IsN64, HasStdEnc]> { 719 let DecoderNamespace = "Mips64"; 720 } 721} 722 723// Atomic Compare & Swap. 724class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 725 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 726 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 727 728multiclass AtomicCmpSwap32<PatFrag Op> { 729 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 730 Requires<[NotN64, HasStdEnc]>; 731 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 732 Requires<[IsN64, HasStdEnc]> { 733 let DecoderNamespace = "Mips64"; 734 } 735} 736 737class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 738 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 739 [], NoItinerary, FrmI> { 740 let DecoderMethod = "DecodeMem"; 741 let mayLoad = 1; 742} 743 744class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 745 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 746 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 747 let DecoderMethod = "DecodeMem"; 748 let mayStore = 1; 749 let Constraints = "$rt = $dst"; 750} 751 752class MFC3OP<dag outs, dag ins, string asmstr> : 753 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 754 755//===----------------------------------------------------------------------===// 756// Pseudo instructions 757//===----------------------------------------------------------------------===// 758 759// Return RA. 760let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 761def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 762 763let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 764def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 765 [(callseq_start timm:$amt)]>; 766def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 767 [(callseq_end timm:$amt1, timm:$amt2)]>; 768} 769 770let usesCustomInserter = 1 in { 771 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 772 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 773 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 774 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 775 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 776 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 777 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 778 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 779 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 780 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 781 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 782 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 783 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 784 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 785 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 786 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 787 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 788 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 789 790 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 791 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 792 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 793 794 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 795 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 796 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 797} 798 799/// Pseudo instructions for loading, storing and copying accumulator registers. 800let isPseudo = 1 in { 801 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>; 802 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>; 803} 804 805def COPY_AC64 : PseudoSE<(outs ACRegs:$dst), (ins ACRegs:$src), []>; 806 807//===----------------------------------------------------------------------===// 808// Instruction definition 809//===----------------------------------------------------------------------===// 810//===----------------------------------------------------------------------===// 811// MipsI Instructions 812//===----------------------------------------------------------------------===// 813 814/// Arithmetic Instructions (ALU Immediate) 815def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 816 ADDI_FM<0x9>, IsAsCheapAsAMove; 817def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 818def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 819def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 820def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 821 ADDI_FM<0xc>; 822def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 823 ADDI_FM<0xd>; 824def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 825 ADDI_FM<0xe>; 826def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 827 828/// Arithmetic Instructions (3-Operand, R-Type) 829def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>; 830def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 831def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 832def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 833def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 834def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 835def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 836def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 837def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 838def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 839def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 840 841/// Shift Instructions 842def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 843 SRA_FM<0, 0>; 844def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 845 SRA_FM<2, 0>; 846def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 847 SRA_FM<3, 0>; 848def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 849def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 850def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 851 852// Rotate Instructions 853let Predicates = [HasMips32r2, HasStdEnc] in { 854 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>, 855 SRA_FM<2, 1>; 856 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>; 857} 858 859/// Load and Store Instructions 860/// aligned 861defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 862defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; 863defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; 864defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 865defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; 866defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 867defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 868defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 869 870/// load/store left/right 871defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 872defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 873defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 874defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 875 876def SYNC : SYNC_FT, SYNC_FM; 877 878/// Load-linked, Store-conditional 879let Predicates = [NotN64, HasStdEnc] in { 880 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 881 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 882} 883 884let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 885 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 886 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 887} 888 889/// Jump and Branch Instructions 890def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 891 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 892def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 893def B : UncondBranch<"b">, B_FM; 894def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 895def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 896def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 897def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 898def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 899def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 900 901def BAL_BR: BAL_FT, BAL_FM; 902 903def JAL : JumpLink<"jal">, FJ<3>; 904def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 905def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 906def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 907def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 908def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 909def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 910 911def RET : RetBase<CPURegs>, MTLO_FM<8>; 912 913// Exception handling related node and instructions. 914// The conversion sequence is: 915// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 916// MIPSeh_return -> (stack change + indirect branch) 917// 918// MIPSeh_return takes the place of regular return instruction 919// but takes two arguments (V1, V0) which are used for storing 920// the offset and return address respectively. 921def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 922 923def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 924 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 925 926let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 927 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 928 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 929 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 930 CPU64Regs:$dst), 931 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 932} 933 934/// Multiply and Divide Instructions. 935def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>; 936def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>; 937def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>, 938 MULT_FM<0, 0x1a>; 939def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>, 940 MULT_FM<0, 0x1b>; 941 942def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 943def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 944def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 945def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 946 947/// Sign Ext In Register Instructions. 948def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 949def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 950 951/// Count Leading 952def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 953def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 954 955/// Word Swap Bytes Within Halfwords 956def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 957 958/// No operation. 959def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 960 961// FrameIndexes are legalized when they are operands from load/store 962// instructions. The same not happens for stack address copies, so an 963// add op with mem ComplexPattern is used and the stack address copy 964// can be matched. It's similar to Sparc LEA_ADDRi 965def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 966 967// MADD*/MSUB* 968def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; 969def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; 970def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; 971def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; 972 973def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 974 975def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 976def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 977 978/// Move Control Registers From/To CPU Registers 979def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 980 (ins CPURegsOpnd:$rd, uimm16:$sel), 981 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 982 983def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 984 (ins CPURegsOpnd:$rt), 985 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 986 987def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 988 (ins CPURegsOpnd:$rd, uimm16:$sel), 989 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 990 991def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 992 (ins CPURegsOpnd:$rt), 993 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 994 995//===----------------------------------------------------------------------===// 996// Instruction aliases 997//===----------------------------------------------------------------------===// 998def : InstAlias<"move $dst, $src", 999 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1000 Requires<[NotMips64]>; 1001def : InstAlias<"move $dst, $src", 1002 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1003 Requires<[NotMips64]>; 1004def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 1005def : InstAlias<"addu $rs, $rt, $imm", 1006 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1007def : InstAlias<"add $rs, $rt, $imm", 1008 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1009def : InstAlias<"and $rs, $rt, $imm", 1010 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1011def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1012 Requires<[NotMips64]>; 1013def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1014def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1015def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1016 Requires<[NotMips64]>; 1017def : InstAlias<"not $rt, $rs", 1018 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1019def : InstAlias<"neg $rt, $rs", 1020 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1021def : InstAlias<"negu $rt, $rs", 1022 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1023def : InstAlias<"slt $rs, $rt, $imm", 1024 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1025def : InstAlias<"xor $rs, $rt, $imm", 1026 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 1027 Requires<[NotMips64]>; 1028def : InstAlias<"or $rs, $rt, $imm", 1029 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 1030 Requires<[NotMips64]>; 1031def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1032def : InstAlias<"mfc0 $rt, $rd", 1033 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1034def : InstAlias<"mtc0 $rt, $rd", 1035 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1036def : InstAlias<"mfc2 $rt, $rd", 1037 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1038def : InstAlias<"mtc2 $rt, $rd", 1039 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1040 1041//===----------------------------------------------------------------------===// 1042// Assembler Pseudo Instructions 1043//===----------------------------------------------------------------------===// 1044 1045class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1046 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1047 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1048def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1049 1050class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1051 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1052 !strconcat(instr_asm, "\t$rt, $addr")> ; 1053def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1054 1055class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1056 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1057 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1058def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1059 1060 1061 1062//===----------------------------------------------------------------------===// 1063// Arbitrary patterns that map to one or more instructions 1064//===----------------------------------------------------------------------===// 1065 1066// Small immediates 1067def : MipsPat<(i32 immSExt16:$in), 1068 (ADDiu ZERO, imm:$in)>; 1069def : MipsPat<(i32 immZExt16:$in), 1070 (ORi ZERO, imm:$in)>; 1071def : MipsPat<(i32 immLow16Zero:$in), 1072 (LUi (HI16 imm:$in))>; 1073 1074// Arbitrary immediates 1075def : MipsPat<(i32 imm:$imm), 1076 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1077 1078// Carry MipsPatterns 1079def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1080 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1081def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1082 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1083def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1084 (ADDiu CPURegs:$src, imm:$imm)>; 1085 1086// Call 1087def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1088 (JAL tglobaladdr:$dst)>; 1089def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1090 (JAL texternalsym:$dst)>; 1091//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1092// (JALR CPURegs:$dst)>; 1093 1094// Tail call 1095def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1096 (TAILCALL tglobaladdr:$dst)>; 1097def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1098 (TAILCALL texternalsym:$dst)>; 1099// hi/lo relocs 1100def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1101def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1102def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1103def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1104def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1105def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1106 1107def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1108def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1109def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1110def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1111def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1112def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1113 1114def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1115 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1116def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1117 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1118def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1119 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1120def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1121 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1122def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1123 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1124 1125// gp_rel relocs 1126def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1127 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1128def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1129 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1130 1131// wrapper_pic 1132class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1133 MipsPat<(MipsWrapper RC:$gp, node:$in), 1134 (ADDiuOp RC:$gp, node:$in)>; 1135 1136def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1137def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1138def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1139def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1140def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1141def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1142 1143// Mips does not have "not", so we expand our way 1144def : MipsPat<(not CPURegs:$in), 1145 (NOR CPURegsOpnd:$in, ZERO)>; 1146 1147// extended loads 1148let Predicates = [NotN64, HasStdEnc] in { 1149 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1150 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1151 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1152} 1153let Predicates = [IsN64, HasStdEnc] in { 1154 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1155 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1156 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1157} 1158 1159// peepholes 1160let Predicates = [NotN64, HasStdEnc] in { 1161 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1162} 1163let Predicates = [IsN64, HasStdEnc] in { 1164 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1165} 1166 1167// brcond patterns 1168multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1169 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1170 Instruction SLTiuOp, Register ZEROReg> { 1171def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1172 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1173def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1174 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1175 1176def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1177 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1178def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1179 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1180def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1181 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1182def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1183 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1184 1185def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1186 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1187def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1188 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1189 1190def : MipsPat<(brcond RC:$cond, bb:$dst), 1191 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1192} 1193 1194defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1195 1196// setcc patterns 1197multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1198 Instruction SLTuOp, Register ZEROReg> { 1199 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1200 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1201 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1202 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1203} 1204 1205multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1206 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1207 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1208 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1209 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1210} 1211 1212multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1213 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1214 (SLTOp RC:$rhs, RC:$lhs)>; 1215 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1216 (SLTuOp RC:$rhs, RC:$lhs)>; 1217} 1218 1219multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1220 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1221 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1222 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1223 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1224} 1225 1226multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1227 Instruction SLTiuOp> { 1228 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1229 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1230 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1231 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1232} 1233 1234defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1235defm : SetlePats<CPURegs, SLT, SLTu>; 1236defm : SetgtPats<CPURegs, SLT, SLTu>; 1237defm : SetgePats<CPURegs, SLT, SLTu>; 1238defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1239 1240// bswap pattern 1241def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1242 1243//===----------------------------------------------------------------------===// 1244// Floating Point Support 1245//===----------------------------------------------------------------------===// 1246 1247include "MipsInstrFPU.td" 1248include "Mips64InstrInfo.td" 1249include "MipsCondMov.td" 1250 1251// 1252// Mips16 1253 1254include "Mips16InstrFormats.td" 1255include "Mips16InstrInfo.td" 1256 1257// DSP 1258include "MipsDSPInstrFormats.td" 1259include "MipsDSPInstrInfo.td" 1260 1261