MipsInstrInfo.td revision 2ef99c5dff1ab9612f2d65e38f725d809672d2fd
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 27def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 29def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 34def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 35 36def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 37 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Tail call 56def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 58 59// Hi and Lo nodes are used to handle global addresses. Used on 60// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 61// static model. (nothing to do with Mips Registers Hi and Lo) 62def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 63def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 64def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 65 66// TlsGd node is used to handle General Dynamic TLS 67def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 68 69// TprelHi and TprelLo nodes are used to handle Local Exec TLS 70def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 71def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 72 73// Thread pointer 74def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 75 76// Return 77def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 79 80// These are target-independent nodes, but have target-specific formats. 81def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 83def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 84 [SDNPHasChain, SDNPSideEffect, 85 SDNPOptInGlue, SDNPOutGlue]>; 86 87// Nodes used to extract LO/HI registers. 88def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 89def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 90 91// Node used to insert 32-bit integers to LOHI register pair. 92def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 93 94// Mult nodes. 95def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 97 98// MAdd*/MSub* nodes 99def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 101def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 103 104// DivRem(u) nodes 105def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 106def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 107def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 108 [SDNPOutGlue]>; 109def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 110 [SDNPOutGlue]>; 111 112// Target constant nodes that are not part of any isel patterns and remain 113// unchanged can cause instructions with illegal operands to be emitted. 114// Wrapper node patterns give the instruction selector a chance to replace 115// target constant nodes that would otherwise remain unchanged with ADDiu 116// nodes. Without these wrapper node patterns, the following conditional move 117// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 118// compiled: 119// movn %got(d)($gp), %got(c)($gp), $4 120// This instruction is illegal since movn can take only register operands. 121 122def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 123 124def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 125 126def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 127def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 128 129def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 131def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 133def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 135def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 137def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 139def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 141def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 143def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 145 146//===----------------------------------------------------------------------===// 147// Mips Instruction Predicate Definitions. 148//===----------------------------------------------------------------------===// 149def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 150 AssemblerPredicate<"FeatureSEInReg">; 151def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 152 AssemblerPredicate<"FeatureBitCount">; 153def HasSwap : Predicate<"Subtarget.hasSwap()">, 154 AssemblerPredicate<"FeatureSwap">; 155def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 156 AssemblerPredicate<"FeatureCondMov">; 157def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 158 AssemblerPredicate<"FeatureFPIdx">; 159def HasMips32 : Predicate<"Subtarget.hasMips32()">, 160 AssemblerPredicate<"FeatureMips32">; 161def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 162 AssemblerPredicate<"FeatureMips32r2">; 163def HasMips64 : Predicate<"Subtarget.hasMips64()">, 164 AssemblerPredicate<"FeatureMips64">; 165def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 166 AssemblerPredicate<"!FeatureMips64">; 167def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 168 AssemblerPredicate<"FeatureMips64r2">; 169def IsN64 : Predicate<"Subtarget.isABI_N64()">, 170 AssemblerPredicate<"FeatureN64">; 171def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 172 AssemblerPredicate<"!FeatureN64">; 173def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 174 AssemblerPredicate<"FeatureMips16">; 175def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 176 AssemblerPredicate<"FeatureMips32">; 177def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 178 AssemblerPredicate<"FeatureMips32">; 179def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 180 AssemblerPredicate<"FeatureMips32">; 181def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 182 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">; 183def NotDSP : Predicate<"!Subtarget.hasDSP()">; 184def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, 185 AssemblerPredicate<"FeatureMicroMips">; 186def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, 187 AssemblerPredicate<"!FeatureMicroMips">; 188def IsLE : Predicate<"Subtarget.isLittle()">; 189def IsBE : Predicate<"!Subtarget.isLittle()">; 190 191class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 192 let Predicates = [HasStdEnc]; 193} 194 195class IsCommutable { 196 bit isCommutable = 1; 197} 198 199class IsBranch { 200 bit isBranch = 1; 201} 202 203class IsReturn { 204 bit isReturn = 1; 205} 206 207class IsCall { 208 bit isCall = 1; 209} 210 211class IsTailCall { 212 bit isCall = 1; 213 bit isTerminator = 1; 214 bit isReturn = 1; 215 bit isBarrier = 1; 216 bit hasExtraSrcRegAllocReq = 1; 217 bit isCodeGenOnly = 1; 218} 219 220class IsAsCheapAsAMove { 221 bit isAsCheapAsAMove = 1; 222} 223 224class NeverHasSideEffects { 225 bit neverHasSideEffects = 1; 226} 227 228//===----------------------------------------------------------------------===// 229// Instruction format superclass 230//===----------------------------------------------------------------------===// 231 232include "MipsInstrFormats.td" 233 234//===----------------------------------------------------------------------===// 235// Mips Operand, Complex Patterns and Transformations Definitions. 236//===----------------------------------------------------------------------===// 237 238// Instruction operand types 239def jmptarget : Operand<OtherVT> { 240 let EncoderMethod = "getJumpTargetOpValue"; 241} 242def brtarget : Operand<OtherVT> { 243 let EncoderMethod = "getBranchTargetOpValue"; 244 let OperandType = "OPERAND_PCREL"; 245 let DecoderMethod = "DecodeBranchTarget"; 246} 247def calltarget : Operand<iPTR> { 248 let EncoderMethod = "getJumpTargetOpValue"; 249} 250 251def simm16 : Operand<i32> { 252 let DecoderMethod= "DecodeSimm16"; 253} 254 255def simm20 : Operand<i32> { 256} 257 258def uimm20 : Operand<i32> { 259} 260 261def uimm10 : Operand<i32> { 262} 263 264def simm16_64 : Operand<i64> { 265 let DecoderMethod = "DecodeSimm16"; 266} 267 268// Unsigned Operand 269def uimm5 : Operand<i32> { 270 let PrintMethod = "printUnsignedImm"; 271} 272 273def uimm6 : Operand<i32> { 274 let PrintMethod = "printUnsignedImm"; 275} 276 277def uimm16 : Operand<i32> { 278 let PrintMethod = "printUnsignedImm"; 279} 280 281def MipsMemAsmOperand : AsmOperandClass { 282 let Name = "Mem"; 283 let ParserMethod = "parseMemOperand"; 284} 285 286def MipsInvertedImmoperand : AsmOperandClass { 287 let Name = "InvNum"; 288 let RenderMethod = "addImmOperands"; 289 let ParserMethod = "parseInvNum"; 290} 291 292def PtrRegAsmOperand : AsmOperandClass { 293 let Name = "PtrReg"; 294 let ParserMethod = "parsePtrReg"; 295} 296 297 298def InvertedImOperand : Operand<i32> { 299 let ParserMatchClass = MipsInvertedImmoperand; 300} 301 302// Address operand 303def mem : Operand<iPTR> { 304 let PrintMethod = "printMemOperand"; 305 let MIOperandInfo = (ops ptr_rc, simm16); 306 let EncoderMethod = "getMemEncoding"; 307 let ParserMatchClass = MipsMemAsmOperand; 308 let OperandType = "OPERAND_MEMORY"; 309} 310 311def mem_ea : Operand<iPTR> { 312 let PrintMethod = "printMemOperandEA"; 313 let MIOperandInfo = (ops ptr_rc, simm16); 314 let EncoderMethod = "getMemEncoding"; 315 let OperandType = "OPERAND_MEMORY"; 316} 317 318def PtrRC : Operand<iPTR> { 319 let MIOperandInfo = (ops ptr_rc); 320 let DecoderMethod = "DecodePtrRegisterClass"; 321 let ParserMatchClass = PtrRegAsmOperand; 322} 323 324// size operand of ext instruction 325def size_ext : Operand<i32> { 326 let EncoderMethod = "getSizeExtEncoding"; 327 let DecoderMethod = "DecodeExtSize"; 328} 329 330// size operand of ins instruction 331def size_ins : Operand<i32> { 332 let EncoderMethod = "getSizeInsEncoding"; 333 let DecoderMethod = "DecodeInsSize"; 334} 335 336// Transformation Function - get the lower 16 bits. 337def LO16 : SDNodeXForm<imm, [{ 338 return getImm(N, N->getZExtValue() & 0xFFFF); 339}]>; 340 341// Transformation Function - get the higher 16 bits. 342def HI16 : SDNodeXForm<imm, [{ 343 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 344}]>; 345 346// Plus 1. 347def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 348 349// Node immediate fits as 16-bit sign extended on target immediate. 350// e.g. addi, andi 351def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 352 353// Node immediate fits as 16-bit sign extended on target immediate. 354// e.g. addi, andi 355def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 356 357// Node immediate fits as 15-bit sign extended on target immediate. 358// e.g. addi, andi 359def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 360 361// Node immediate fits as 16-bit zero extended on target immediate. 362// The LO16 param means that only the lower 16 bits of the node 363// immediate are caught. 364// e.g. addiu, sltiu 365def immZExt16 : PatLeaf<(imm), [{ 366 if (N->getValueType(0) == MVT::i32) 367 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 368 else 369 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 370}], LO16>; 371 372// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 373def immLow16Zero : PatLeaf<(imm), [{ 374 int64_t Val = N->getSExtValue(); 375 return isInt<32>(Val) && !(Val & 0xffff); 376}]>; 377 378// shamt field must fit in 5 bits. 379def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 380 381// True if (N + 1) fits in 16-bit field. 382def immSExt16Plus1 : PatLeaf<(imm), [{ 383 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 384}]>; 385 386// Mips Address Mode! SDNode frameindex could possibily be a match 387// since load and store instructions from stack used it. 388def addr : 389 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 390 391def addrRegImm : 392 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 393 394def addrRegReg : 395 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 396 397def addrDefault : 398 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 399 400//===----------------------------------------------------------------------===// 401// Instructions specific format 402//===----------------------------------------------------------------------===// 403 404// Arithmetic and logical instructions with 3 register operands. 405class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 406 InstrItinClass Itin = NoItinerary, 407 SDPatternOperator OpNode = null_frag>: 408 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 409 !strconcat(opstr, "\t$rd, $rs, $rt"), 410 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 411 let isCommutable = isComm; 412 let isReMaterializable = 1; 413} 414 415// Arithmetic and logical instructions with 2 register operands. 416class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 417 InstrItinClass Itin = NoItinerary, 418 SDPatternOperator imm_type = null_frag, 419 SDPatternOperator OpNode = null_frag> : 420 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 421 !strconcat(opstr, "\t$rt, $rs, $imm16"), 422 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 423 Itin, FrmI, opstr> { 424 let isReMaterializable = 1; 425 let TwoOperandAliasConstraint = "$rs = $rt"; 426} 427 428// Arithmetic Multiply ADD/SUB 429class MArithR<string opstr, bit isComm = 0> : 430 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 431 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> { 432 let Defs = [HI0, LO0]; 433 let Uses = [HI0, LO0]; 434 let isCommutable = isComm; 435} 436 437// Logical 438class LogicNOR<string opstr, RegisterOperand RO>: 439 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 440 !strconcat(opstr, "\t$rd, $rs, $rt"), 441 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> { 442 let isCommutable = 1; 443} 444 445// Shifts 446class shift_rotate_imm<string opstr, Operand ImmOpnd, 447 RegisterOperand RO, SDPatternOperator OpNode = null_frag, 448 SDPatternOperator PF = null_frag> : 449 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 450 !strconcat(opstr, "\t$rd, $rt, $shamt"), 451 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>; 452 453class shift_rotate_reg<string opstr, RegisterOperand RO, 454 SDPatternOperator OpNode = null_frag>: 455 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 456 !strconcat(opstr, "\t$rd, $rt, $rs"), 457 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>; 458 459// Load Upper Imediate 460class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 461 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 462 [], IIArith, FrmI, opstr>, IsAsCheapAsAMove { 463 let neverHasSideEffects = 1; 464 let isReMaterializable = 1; 465} 466 467// Memory Load/Store 468class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 469 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 470 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 471 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 472 let DecoderMethod = "DecodeMem"; 473 let canFoldAsLoad = 1; 474 let mayLoad = 1; 475} 476 477class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 478 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 479 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 480 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 481 let DecoderMethod = "DecodeMem"; 482 let mayStore = 1; 483} 484 485// Load/Store Left/Right 486let canFoldAsLoad = 1 in 487class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 488 InstrItinClass Itin> : 489 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 490 !strconcat(opstr, "\t$rt, $addr"), 491 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 492 let DecoderMethod = "DecodeMem"; 493 string Constraints = "$src = $rt"; 494} 495 496class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 497 InstrItinClass Itin> : 498 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 499 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 500 let DecoderMethod = "DecodeMem"; 501} 502 503// Conditional Branch 504class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> : 505 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset), 506 !strconcat(opstr, "\t$rs, $rt, $offset"), 507 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 508 FrmI> { 509 let isBranch = 1; 510 let isTerminator = 1; 511 let hasDelaySlot = 1; 512 let Defs = [AT]; 513} 514 515class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> : 516 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 517 !strconcat(opstr, "\t$rs, $offset"), 518 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 519 let isBranch = 1; 520 let isTerminator = 1; 521 let hasDelaySlot = 1; 522 let Defs = [AT]; 523} 524 525// SetCC 526class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 527 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 528 !strconcat(opstr, "\t$rd, $rs, $rt"), 529 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 530 IIslt, FrmR, opstr>; 531 532class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 533 RegisterOperand RO>: 534 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 535 !strconcat(opstr, "\t$rt, $rs, $imm16"), 536 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 537 IIslt, FrmI, opstr>; 538 539// Jump 540class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 541 SDPatternOperator targetoperator> : 542 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 543 [(operator targetoperator:$target)], IIBranch, FrmJ> { 544 let isTerminator=1; 545 let isBarrier=1; 546 let hasDelaySlot = 1; 547 let DecoderMethod = "DecodeJumpTarget"; 548 let Defs = [AT]; 549} 550 551// Unconditional branch 552class UncondBranch<Instruction BEQInst> : 553 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, 554 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 555 let isBranch = 1; 556 let isTerminator = 1; 557 let isBarrier = 1; 558 let hasDelaySlot = 1; 559 let Predicates = [RelocPIC, HasStdEnc]; 560 let Defs = [AT]; 561} 562 563// Base class for indirect branch and return instruction classes. 564let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 565class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>: 566 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>; 567 568// Indirect branch 569class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> { 570 let isBranch = 1; 571 let isIndirectBranch = 1; 572} 573 574// Return instruction 575class RetBase<RegisterOperand RO>: JumpFR<RO> { 576 let isReturn = 1; 577 let isCodeGenOnly = 1; 578 let hasCtrlDep = 1; 579 let hasExtraSrcRegAllocReq = 1; 580} 581 582// Jump and Link (Call) 583let isCall=1, hasDelaySlot=1, Defs = [RA] in { 584 class JumpLink<string opstr> : 585 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 586 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 587 let DecoderMethod = "DecodeJumpTarget"; 588 } 589 590 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 591 Register RetReg, RegisterOperand ResRO = RO>: 592 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 593 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 594 595 class JumpLinkReg<string opstr, RegisterOperand RO>: 596 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 597 [], IIBranch, FrmR>; 598 599 class BGEZAL_FT<string opstr, RegisterOperand RO> : 600 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 601 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 602 603} 604 605class BAL_BR_Pseudo<Instruction RealInst> : 606 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 607 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 608 let isBranch = 1; 609 let isTerminator = 1; 610 let isBarrier = 1; 611 let hasDelaySlot = 1; 612 let Defs = [RA]; 613} 614 615// Syscall 616class SYS_FT<string opstr> : 617 InstSE<(outs), (ins uimm20:$code_), 618 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; 619// Break 620class BRK_FT<string opstr> : 621 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 622 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; 623 624// (D)Eret 625class ER_FT<string opstr> : 626 InstSE<(outs), (ins), 627 opstr, [], NoItinerary, FrmOther>; 628 629// Interrupts 630class DEI_FT<string opstr, RegisterOperand RO> : 631 InstSE<(outs RO:$rt), (ins), 632 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>; 633 634// Wait 635class WAIT_FT<string opstr> : 636 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> { 637 let Inst{31-26} = 0x10; 638 let Inst{25} = 1; 639 let Inst{24-6} = 0; 640 let Inst{5-0} = 0x20; 641} 642 643// Sync 644let hasSideEffects = 1 in 645class SYNC_FT : 646 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 647 NoItinerary, FrmOther>; 648 649let hasSideEffects = 1 in 650class TEQ_FT<string opstr, RegisterOperand RO> : 651 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 652 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; 653 654class TEQI_FT<string opstr, RegisterOperand RO> : 655 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 656 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>; 657// Mul, Div 658class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 659 list<Register> DefRegs> : 660 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 661 itin, FrmR, opstr> { 662 let isCommutable = 1; 663 let Defs = DefRegs; 664 let neverHasSideEffects = 1; 665} 666 667// Pseudo multiply/divide instruction with explicit accumulator register 668// operands. 669class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 670 SDPatternOperator OpNode, InstrItinClass Itin, 671 bit IsComm = 1, bit HasSideEffects = 0, 672 bit UsesCustomInserter = 0> : 673 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 674 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 675 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 676 let isCommutable = IsComm; 677 let hasSideEffects = HasSideEffects; 678 let usesCustomInserter = UsesCustomInserter; 679} 680 681// Pseudo multiply add/sub instruction with explicit accumulator register 682// operands. 683class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 684 : PseudoSE<(outs ACC64:$ac), 685 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 686 [(set ACC64:$ac, 687 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 688 IIImult>, 689 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 690 string Constraints = "$acin = $ac"; 691} 692 693class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 694 list<Register> DefRegs> : 695 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 696 [], itin, FrmR, opstr> { 697 let Defs = DefRegs; 698} 699 700// Move from Hi/Lo 701class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 702 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 703 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>; 704 705class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 706 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR, 707 opstr> { 708 let Uses = [UseReg]; 709 let neverHasSideEffects = 1; 710} 711 712class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> 713 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), 714 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], IIHiLo>; 715 716class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 717 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, 718 FrmR, opstr> { 719 let Defs = DefRegs; 720 let neverHasSideEffects = 1; 721} 722 723class EffectiveAddress<string opstr, RegisterOperand RO> : 724 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 725 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> { 726 let isCodeGenOnly = 1; 727 let DecoderMethod = "DecodeMem"; 728} 729 730// Count Leading Ones/Zeros in Word 731class CountLeading0<string opstr, RegisterOperand RO>: 732 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 733 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>, 734 Requires<[HasBitCount, HasStdEnc]>; 735 736class CountLeading1<string opstr, RegisterOperand RO>: 737 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 738 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>, 739 Requires<[HasBitCount, HasStdEnc]>; 740 741 742// Sign Extend in Register. 743class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> : 744 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 745 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> { 746 let Predicates = [HasSEInReg, HasStdEnc]; 747} 748 749// Subword Swap 750class SubwordSwap<string opstr, RegisterOperand RO>: 751 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 752 NoItinerary, FrmR, opstr> { 753 let Predicates = [HasSwap, HasStdEnc]; 754 let neverHasSideEffects = 1; 755} 756 757// Read Hardware 758class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 759 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 760 IIArith, FrmR>; 761 762// Ext and Ins 763class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 764 SDPatternOperator Op = null_frag>: 765 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size), 766 !strconcat(opstr, " $rt, $rs, $pos, $size"), 767 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary, 768 FrmR, opstr> { 769 let Predicates = [HasMips32r2, HasStdEnc]; 770} 771 772class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 773 SDPatternOperator Op = null_frag>: 774 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), 775 !strconcat(opstr, " $rt, $rs, $pos, $size"), 776 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], 777 NoItinerary, FrmR, opstr> { 778 let Predicates = [HasMips32r2, HasStdEnc]; 779 let Constraints = "$src = $rt"; 780} 781 782// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 783class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 784 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 785 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 786 787// Atomic Compare & Swap. 788class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 789 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 790 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 791 792class LLBase<string opstr, RegisterOperand RO> : 793 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 794 [], NoItinerary, FrmI> { 795 let DecoderMethod = "DecodeMem"; 796 let mayLoad = 1; 797} 798 799class SCBase<string opstr, RegisterOperand RO> : 800 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 801 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 802 let DecoderMethod = "DecodeMem"; 803 let mayStore = 1; 804 let Constraints = "$rt = $dst"; 805} 806 807class MFC3OP<string asmstr, RegisterOperand RO> : 808 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 809 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 810 811class TrapBase<Instruction RealInst> 812 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>, 813 PseudoInstExpansion<(RealInst 0, 0)> { 814 let isBarrier = 1; 815 let isTerminator = 1; 816 let isCodeGenOnly = 1; 817} 818 819//===----------------------------------------------------------------------===// 820// Pseudo instructions 821//===----------------------------------------------------------------------===// 822 823// Return RA. 824let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 825def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 826 827let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 828def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 829 [(callseq_start timm:$amt)]>; 830def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 831 [(callseq_end timm:$amt1, timm:$amt2)]>; 832} 833 834let usesCustomInserter = 1 in { 835 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 836 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 837 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 838 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 839 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 840 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 841 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 842 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 843 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 844 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 845 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 846 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 847 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 848 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 849 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 850 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 851 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 852 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 853 854 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 855 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 856 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 857 858 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 859 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 860 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 861} 862 863/// Pseudo instructions for loading and storing accumulator registers. 864let isPseudo = 1, isCodeGenOnly = 1 in { 865 def LOAD_ACC64 : Load<"", ACC64>; 866 def STORE_ACC64 : Store<"", ACC64>; 867} 868 869//===----------------------------------------------------------------------===// 870// Instruction definition 871//===----------------------------------------------------------------------===// 872//===----------------------------------------------------------------------===// 873// MipsI Instructions 874//===----------------------------------------------------------------------===// 875 876/// Arithmetic Instructions (ALU Immediate) 877def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16, 878 add>, 879 ADDI_FM<0x9>, IsAsCheapAsAMove; 880def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>; 881def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 882 SLTI_FM<0xa>; 883def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 884 SLTI_FM<0xb>; 885def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16, 886 and>, 887 ADDI_FM<0xc>; 888def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16, 889 or>, 890 ADDI_FM<0xd>; 891def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16, 892 xor>, 893 ADDI_FM<0xe>; 894def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 895 896/// Arithmetic Instructions (3-Operand, R-Type) 897def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>, 898 ADD_FM<0, 0x21>; 899def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>, 900 ADD_FM<0, 0x23>; 901let Defs = [HI0, LO0] in 902def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>, 903 ADD_FM<0x1c, 2>; 904def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 905def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 906def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 907def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 908def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>, 909 ADD_FM<0, 0x24>; 910def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>, 911 ADD_FM<0, 0x25>; 912def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>, 913 ADD_FM<0, 0x26>; 914def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 915 916/// Shift Instructions 917def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>, 918 SRA_FM<0, 0>; 919def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>, 920 SRA_FM<2, 0>; 921def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>, 922 SRA_FM<3, 0>; 923def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>; 924def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>; 925def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>; 926 927// Rotate Instructions 928let Predicates = [HasMips32r2, HasStdEnc] in { 929 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr, 930 immZExt5>, 931 SRA_FM<2, 1>; 932 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>, 933 SRLV_FM<6, 1>; 934} 935 936/// Load and Store Instructions 937/// aligned 938def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>; 939def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel, 940 LW_FM<0x24>; 941def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel, 942 LW_FM<0x21>; 943def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; 944def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, 945 LW_FM<0x23>; 946def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; 947def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; 948def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; 949 950/// load/store left/right 951def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>; 952def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>; 953def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>; 954def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>; 955 956def SYNC : SYNC_FT, SYNC_FM; 957def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 958def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; 959def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; 960def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; 961def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; 962def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; 963 964def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>; 965def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>; 966def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>; 967def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>; 968def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>; 969def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>; 970 971def BREAK : BRK_FT<"break">, BRK_FM<0xd>; 972def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; 973def TRAP : TrapBase<BREAK>; 974 975def ERET : ER_FT<"eret">, ER_FM<0x18>; 976def DERET : ER_FT<"deret">, ER_FM<0x1f>; 977 978def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; 979def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>; 980 981def WAIT : WAIT_FT<"wait">; 982 983/// Load-linked, Store-conditional 984def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>; 985def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>; 986 987/// Jump and Branch Instructions 988def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 989 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 990def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>; 991def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>; 992def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>; 993def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>; 994def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>; 995def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>; 996def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>; 997def B : UncondBranch<BEQ>; 998 999def JAL : JumpLink<"jal">, FJ<3>; 1000def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 1001def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 1002def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>; 1003def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>; 1004def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 1005def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 1006def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall; 1007 1008def RET : RetBase<GPR32Opnd>, MTLO_FM<8>; 1009 1010// Exception handling related node and instructions. 1011// The conversion sequence is: 1012// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1013// MIPSeh_return -> (stack change + indirect branch) 1014// 1015// MIPSeh_return takes the place of regular return instruction 1016// but takes two arguments (V1, V0) which are used for storing 1017// the offset and return address respectively. 1018def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1019 1020def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1021 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1022 1023let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1024 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1025 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1026 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1027 GPR64:$dst), 1028 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1029} 1030 1031/// Multiply and Divide Instructions. 1032def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>, 1033 MULT_FM<0, 0x18>; 1034def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>, 1035 MULT_FM<0, 0x19>; 1036def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>; 1037def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>; 1038 1039def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; 1040def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; 1041def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>; 1042def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>; 1043 1044/// Sign Ext In Register Instructions. 1045def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; 1046def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; 1047 1048/// Count Leading 1049def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; 1050def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; 1051 1052/// Word Swap Bytes Within Halfwords 1053def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; 1054 1055/// No operation. 1056def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1057 1058// FrameIndexes are legalized when they are operands from load/store 1059// instructions. The same not happens for stack address copies, so an 1060// add op with mem ComplexPattern is used and the stack address copy 1061// can be matched. It's similar to Sparc LEA_ADDRi 1062def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1063 1064// MADD*/MSUB* 1065def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1066def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1067def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>; 1068def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>; 1069 1070let Predicates = [HasStdEnc, NotDSP] in { 1071def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; 1072def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; 1073def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>; 1074def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>; 1075def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>; 1076def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1077def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1078def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1079def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1080} 1081 1082def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, 1083 0, 1, 1>; 1084def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, 1085 0, 1, 1>; 1086 1087def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1088 1089def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; 1090def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; 1091 1092/// Move Control Registers From/To CPU Registers 1093def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>; 1094def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>; 1095def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1096def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1097 1098//===----------------------------------------------------------------------===// 1099// Instruction aliases 1100//===----------------------------------------------------------------------===// 1101def : InstAlias<"move $dst, $src", 1102 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1103 Requires<[NotMips64]>; 1104def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; 1105def : InstAlias<"addu $rs, $rt, $imm", 1106 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1107def : InstAlias<"add $rs, $rt, $imm", 1108 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1109def : InstAlias<"and $rs, $rt, $imm", 1110 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1111def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1112def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1113def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1114def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1115def : InstAlias<"not $rt, $rs", 1116 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1117def : InstAlias<"neg $rt, $rs", 1118 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1119def : InstAlias<"negu $rt, $rs", 1120 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1121def : InstAlias<"slt $rs, $rt, $imm", 1122 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1123def : InstAlias<"xor $rs, $rt, $imm", 1124 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1125def : InstAlias<"or $rs, $rt, $imm", 1126 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1127def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1128def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1129def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1130def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1131def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1132def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1133def : InstAlias<"bnez $rs,$offset", 1134 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1135def : InstAlias<"beqz $rs,$offset", 1136 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1137def : InstAlias<"syscall", (SYSCALL 0), 1>; 1138 1139def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1140def : InstAlias<"break", (BREAK 0, 0), 1>; 1141def : InstAlias<"ei", (EI ZERO), 1>; 1142def : InstAlias<"di", (DI ZERO), 1>; 1143 1144def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1145def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1146def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1147def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1148def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1149def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1150def : InstAlias<"sub, $rd, $rs, $imm", 1151 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; 1152def : InstAlias<"subu, $rd, $rs, $imm", 1153 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; 1154 1155//===----------------------------------------------------------------------===// 1156// Assembler Pseudo Instructions 1157//===----------------------------------------------------------------------===// 1158 1159class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1160 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1161 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1162def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>; 1163 1164class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1165 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1166 !strconcat(instr_asm, "\t$rt, $addr")> ; 1167def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1168 1169class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1170 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1171 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1172def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; 1173 1174//===----------------------------------------------------------------------===// 1175// Arbitrary patterns that map to one or more instructions 1176//===----------------------------------------------------------------------===// 1177 1178// Load/store pattern templates. 1179class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1180 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1181 1182class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1183 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1184 1185// Small immediates 1186def : MipsPat<(i32 immSExt16:$in), 1187 (ADDiu ZERO, imm:$in)>; 1188def : MipsPat<(i32 immZExt16:$in), 1189 (ORi ZERO, imm:$in)>; 1190def : MipsPat<(i32 immLow16Zero:$in), 1191 (LUi (HI16 imm:$in))>; 1192 1193// Arbitrary immediates 1194def : MipsPat<(i32 imm:$imm), 1195 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1196 1197// Carry MipsPatterns 1198def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1199 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1200let Predicates = [HasStdEnc, NotDSP] in { 1201 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1202 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1203 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1204 (ADDiu GPR32:$src, imm:$imm)>; 1205} 1206 1207// Call 1208def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1209 (JAL tglobaladdr:$dst)>; 1210def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1211 (JAL texternalsym:$dst)>; 1212//def : MipsPat<(MipsJmpLink GPR32:$dst), 1213// (JALR GPR32:$dst)>; 1214 1215// Tail call 1216def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1217 (TAILCALL tglobaladdr:$dst)>; 1218def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1219 (TAILCALL texternalsym:$dst)>; 1220// hi/lo relocs 1221def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1222def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1223def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1224def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1225def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1226def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1227 1228def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1229def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1230def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1231def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1232def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1233def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1234 1235def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1236 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1237def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1238 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1239def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1240 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1241def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1242 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1243def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1244 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1245 1246// gp_rel relocs 1247def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1248 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1249def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1250 (ADDiu GPR32:$gp, tconstpool:$in)>; 1251 1252// wrapper_pic 1253class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1254 MipsPat<(MipsWrapper RC:$gp, node:$in), 1255 (ADDiuOp RC:$gp, node:$in)>; 1256 1257def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1258def : WrapperPat<tconstpool, ADDiu, GPR32>; 1259def : WrapperPat<texternalsym, ADDiu, GPR32>; 1260def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1261def : WrapperPat<tjumptable, ADDiu, GPR32>; 1262def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1263 1264// Mips does not have "not", so we expand our way 1265def : MipsPat<(not GPR32:$in), 1266 (NOR GPR32Opnd:$in, ZERO)>; 1267 1268// extended loads 1269let Predicates = [HasStdEnc] in { 1270 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1271 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1272 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1273} 1274 1275// peepholes 1276let Predicates = [HasStdEnc] in 1277def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1278 1279// brcond patterns 1280multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1281 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1282 Instruction SLTiuOp, Register ZEROReg> { 1283def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1284 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1285def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1286 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1287 1288def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1289 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1290def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1291 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1292def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1293 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1294def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1295 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1296def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1297 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1298def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1299 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1300 1301def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1302 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1303def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1304 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1305 1306def : MipsPat<(brcond RC:$cond, bb:$dst), 1307 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1308} 1309 1310defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1311 1312def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1313 (BLEZ i32:$lhs, bb:$dst)>; 1314def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1315 (BGEZ i32:$lhs, bb:$dst)>; 1316 1317// setcc patterns 1318multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1319 Instruction SLTuOp, Register ZEROReg> { 1320 def : MipsPat<(seteq RC:$lhs, 0), 1321 (SLTiuOp RC:$lhs, 1)>; 1322 def : MipsPat<(setne RC:$lhs, 0), 1323 (SLTuOp ZEROReg, RC:$lhs)>; 1324 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1325 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1326 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1327 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1328} 1329 1330multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1331 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1332 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1333 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1334 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1335} 1336 1337multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1338 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1339 (SLTOp RC:$rhs, RC:$lhs)>; 1340 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1341 (SLTuOp RC:$rhs, RC:$lhs)>; 1342} 1343 1344multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1345 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1346 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1347 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1348 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1349} 1350 1351multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1352 Instruction SLTiuOp> { 1353 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1354 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1355 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1356 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1357} 1358 1359defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1360defm : SetlePats<GPR32, SLT, SLTu>; 1361defm : SetgtPats<GPR32, SLT, SLTu>; 1362defm : SetgePats<GPR32, SLT, SLTu>; 1363defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1364 1365// bswap pattern 1366def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1367 1368// Load halfword/word patterns. 1369let AddedComplexity = 40 in { 1370 let Predicates = [HasStdEnc] in { 1371 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1372 def : LoadRegImmPat<LH, i32, sextloadi16>; 1373 def : LoadRegImmPat<LW, i32, load>; 1374 } 1375} 1376 1377//===----------------------------------------------------------------------===// 1378// Floating Point Support 1379//===----------------------------------------------------------------------===// 1380 1381include "MipsInstrFPU.td" 1382include "Mips64InstrInfo.td" 1383include "MipsCondMov.td" 1384 1385// 1386// Mips16 1387 1388include "Mips16InstrFormats.td" 1389include "Mips16InstrInfo.td" 1390 1391// DSP 1392include "MipsDSPInstrFormats.td" 1393include "MipsDSPInstrInfo.td" 1394 1395// MSA 1396include "MipsMSAInstrFormats.td" 1397include "MipsMSAInstrInfo.td" 1398 1399// Micromips 1400include "MicroMipsInstrFormats.td" 1401include "MicroMipsInstrInfo.td" 1402