MipsInstrInfo.td revision 35242e27c578da3915451079b5bdd7b9a89ed77c
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 15-bit sign extended on target immediate. 302// e.g. addi, andi 303def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 304 305// Node immediate fits as 16-bit zero extended on target immediate. 306// The LO16 param means that only the lower 16 bits of the node 307// immediate are caught. 308// e.g. addiu, sltiu 309def immZExt16 : PatLeaf<(imm), [{ 310 if (N->getValueType(0) == MVT::i32) 311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 312 else 313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 314}], LO16>; 315 316// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 317def immLow16Zero : PatLeaf<(imm), [{ 318 int64_t Val = N->getSExtValue(); 319 return isInt<32>(Val) && !(Val & 0xffff); 320}]>; 321 322// shamt field must fit in 5 bits. 323def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 324 325// Mips Address Mode! SDNode frameindex could possibily be a match 326// since load and store instructions from stack used it. 327def addr : 328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 329 330//===----------------------------------------------------------------------===// 331// Instructions specific format 332//===----------------------------------------------------------------------===// 333 334// Arithmetic and logical instructions with 3 register operands. 335class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0, 336 InstrItinClass Itin = NoItinerary, 337 SDPatternOperator OpNode = null_frag>: 338 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 339 !strconcat(opstr, "\t$rd, $rs, $rt"), 340 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 341 let isCommutable = isComm; 342 let isReMaterializable = 1; 343} 344 345// Arithmetic and logical instructions with 2 register operands. 346class ArithLogicI<string opstr, Operand Od, RegisterClass RC, 347 SDPatternOperator imm_type = null_frag, 348 SDPatternOperator OpNode = null_frag> : 349 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 350 !strconcat(opstr, "\t$rt, $rs, $imm16"), 351 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 352 let isReMaterializable = 1; 353} 354 355// Arithmetic Multiply ADD/SUB 356let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 357class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 358 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 359 !strconcat(instr_asm, "\t$rs, $rt"), 360 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 361 let rd = 0; 362 let shamt = 0; 363 let isCommutable = isComm; 364} 365 366// Logical 367class LogicNOR<string opstr, RegisterClass RC>: 368 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 369 !strconcat(opstr, "\t$rd, $rs, $rt"), 370 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 371 let isCommutable = 1; 372} 373 374// Shifts 375class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd, 376 RegisterClass RC, SDPatternOperator OpNode> : 377 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 378 !strconcat(opstr, "\t$rd, $rt, $shamt"), 379 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 380 381// 32-bit shift instructions. 382class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> : 383 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>; 384 385class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>: 386 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 387 !strconcat(opstr, "\t$rd, $rt, $rs"), 388 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; 389 390// Load Upper Imediate 391class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 392 FI<op, (outs RC:$rt), (ins Imm:$imm16), 393 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { 394 let rs = 0; 395 let neverHasSideEffects = 1; 396 let isReMaterializable = 1; 397} 398 399class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 400 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 401 bits<21> addr; 402 let Inst{25-21} = addr{20-16}; 403 let Inst{15-0} = addr{15-0}; 404 let DecoderMethod = "DecodeMem"; 405} 406 407// Memory Load/Store 408let canFoldAsLoad = 1 in 409class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 410 Operand MemOpnd, bit Pseudo>: 411 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 412 !strconcat(instr_asm, "\t$rt, $addr"), 413 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 414 let isPseudo = Pseudo; 415} 416 417class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 418 Operand MemOpnd, bit Pseudo>: 419 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 420 !strconcat(instr_asm, "\t$rt, $addr"), 421 [(OpNode RC:$rt, addr:$addr)], IIStore> { 422 let isPseudo = Pseudo; 423} 424 425// 32-bit load. 426multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 427 bit Pseudo = 0> { 428 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 429 Requires<[NotN64, HasStdEnc]>; 430 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 431 Requires<[IsN64, HasStdEnc]> { 432 let DecoderNamespace = "Mips64"; 433 let isCodeGenOnly = 1; 434 } 435} 436 437// 64-bit load. 438multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 439 bit Pseudo = 0> { 440 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 441 Requires<[NotN64, HasStdEnc]>; 442 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 443 Requires<[IsN64, HasStdEnc]> { 444 let DecoderNamespace = "Mips64"; 445 let isCodeGenOnly = 1; 446 } 447} 448 449// 32-bit store. 450multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 451 bit Pseudo = 0> { 452 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 453 Requires<[NotN64, HasStdEnc]>; 454 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 455 Requires<[IsN64, HasStdEnc]> { 456 let DecoderNamespace = "Mips64"; 457 let isCodeGenOnly = 1; 458 } 459} 460 461// 64-bit store. 462multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 463 bit Pseudo = 0> { 464 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 465 Requires<[NotN64, HasStdEnc]>; 466 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 467 Requires<[IsN64, HasStdEnc]> { 468 let DecoderNamespace = "Mips64"; 469 let isCodeGenOnly = 1; 470 } 471} 472 473// Load/Store Left/Right 474let canFoldAsLoad = 1 in 475class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 476 RegisterClass RC, Operand MemOpnd> : 477 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 478 !strconcat(instr_asm, "\t$rt, $addr"), 479 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 480 string Constraints = "$src = $rt"; 481} 482 483class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 484 RegisterClass RC, Operand MemOpnd>: 485 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 486 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 487 IIStore>; 488 489// 32-bit load left/right. 490multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 491 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 492 Requires<[NotN64, HasStdEnc]>; 493 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 494 Requires<[IsN64, HasStdEnc]> { 495 let DecoderNamespace = "Mips64"; 496 let isCodeGenOnly = 1; 497 } 498} 499 500// 64-bit load left/right. 501multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 502 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 503 Requires<[NotN64, HasStdEnc]>; 504 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 505 Requires<[IsN64, HasStdEnc]> { 506 let DecoderNamespace = "Mips64"; 507 let isCodeGenOnly = 1; 508 } 509} 510 511// 32-bit store left/right. 512multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 513 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 514 Requires<[NotN64, HasStdEnc]>; 515 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 516 Requires<[IsN64, HasStdEnc]> { 517 let DecoderNamespace = "Mips64"; 518 let isCodeGenOnly = 1; 519 } 520} 521 522// 64-bit store left/right. 523multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 524 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 525 Requires<[NotN64, HasStdEnc]>; 526 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 527 Requires<[IsN64, HasStdEnc]> { 528 let DecoderNamespace = "Mips64"; 529 let isCodeGenOnly = 1; 530 } 531} 532 533// Conditional Branch 534class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 535 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 536 !strconcat(opstr, "\t$rs, $rt, $offset"), 537 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 538 FrmI> { 539 let isBranch = 1; 540 let isTerminator = 1; 541 let hasDelaySlot = 1; 542 let Defs = [AT]; 543} 544 545class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 546 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 547 !strconcat(opstr, "\t$rs, $offset"), 548 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 549 let isBranch = 1; 550 let isTerminator = 1; 551 let hasDelaySlot = 1; 552 let Defs = [AT]; 553} 554 555// SetCC 556class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 557 InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 558 !strconcat(opstr, "\t$rd, $rs, $rt"), 559 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 560 561class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 562 RegisterClass RC>: 563 InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 564 !strconcat(opstr, "\t$rt, $rs, $imm16"), 565 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>; 566 567// Jump 568class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 569 SDPatternOperator operator, SDPatternOperator targetoperator>: 570 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 571 [(operator targetoperator:$target)], IIBranch> { 572 let isTerminator=1; 573 let isBarrier=1; 574 let hasDelaySlot = 1; 575 let DecoderMethod = "DecodeJumpTarget"; 576 let Defs = [AT]; 577} 578 579// Unconditional branch 580class UncondBranch<string opstr> : 581 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 582 [(br bb:$offset)], IIBranch, FrmI> { 583 let isBranch = 1; 584 let isTerminator = 1; 585 let isBarrier = 1; 586 let hasDelaySlot = 1; 587 let Predicates = [RelocPIC, HasStdEnc]; 588 let Defs = [AT]; 589} 590 591// Base class for indirect branch and return instruction classes. 592let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 593class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 594 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 595 let rt = 0; 596 let rd = 0; 597 let shamt = 0; 598} 599 600// Indirect branch 601class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 602 let isBranch = 1; 603 let isIndirectBranch = 1; 604} 605 606// Return instruction 607class RetBase<RegisterClass RC>: JumpFR<RC> { 608 let isReturn = 1; 609 let isCodeGenOnly = 1; 610 let hasCtrlDep = 1; 611 let hasExtraSrcRegAllocReq = 1; 612} 613 614// Jump and Link (Call) 615let isCall=1, hasDelaySlot=1, Defs = [RA] in { 616 class JumpLink<bits<6> op, string instr_asm>: 617 FJ<op, (outs), (ins calltarget:$target), 618 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 619 IIBranch> { 620 let DecoderMethod = "DecodeJumpTarget"; 621 } 622 623 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 624 RegisterClass RC>: 625 FR<op, func, (outs), (ins RC:$rs), 626 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 627 let rt = 0; 628 let rd = 31; 629 let shamt = 0; 630 } 631 632 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 633 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 634 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 635 let rt = _rt; 636 } 637} 638 639// Mul, Div 640class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 641 RegisterClass RC, list<Register> DefRegs>: 642 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 643 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 644 let rd = 0; 645 let shamt = 0; 646 let isCommutable = 1; 647 let Defs = DefRegs; 648 let neverHasSideEffects = 1; 649} 650 651class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 652 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 653 654class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 655 RegisterClass RC, list<Register> DefRegs>: 656 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 657 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 658 [(op RC:$rs, RC:$rt)], itin> { 659 let rd = 0; 660 let shamt = 0; 661 let Defs = DefRegs; 662} 663 664class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 665 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 666 667// Move from Hi/Lo 668class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 669 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 670 let Uses = UseRegs; 671 let neverHasSideEffects = 1; 672} 673 674class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 675 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 676 let Defs = DefRegs; 677 let neverHasSideEffects = 1; 678} 679 680class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 681 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 682 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 683 let isCodeGenOnly = 1; 684} 685 686// Count Leading Ones/Zeros in Word 687class CountLeading0<string opstr, RegisterClass RC>: 688 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 689 [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>, 690 Requires<[HasBitCount, HasStdEnc]>; 691 692class CountLeading1<string opstr, RegisterClass RC>: 693 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 694 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>, 695 Requires<[HasBitCount, HasStdEnc]>; 696 697 698// Sign Extend in Register. 699class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 700 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 701 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 702 let Predicates = [HasSEInReg, HasStdEnc]; 703} 704 705// Subword Swap 706class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 707 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 708 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 709 let rs = 0; 710 let shamt = sa; 711 let Predicates = [HasSwap, HasStdEnc]; 712 let neverHasSideEffects = 1; 713} 714 715// Read Hardware 716class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 717 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 718 "rdhwr\t$rt, $rd", [], IIAlu> { 719 let rs = 0; 720 let shamt = 0; 721} 722 723// Ext and Ins 724class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 725 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 726 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 727 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 728 bits<5> pos; 729 bits<5> sz; 730 let rd = sz; 731 let shamt = pos; 732 let Predicates = [HasMips32r2, HasStdEnc]; 733} 734 735class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 736 FR<0x1f, _funct, (outs RC:$rt), 737 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 738 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 739 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 740 NoItinerary> { 741 bits<5> pos; 742 bits<5> sz; 743 let rd = sz; 744 let shamt = pos; 745 let Predicates = [HasMips32r2, HasStdEnc]; 746 let Constraints = "$src = $rt"; 747} 748 749// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 750class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 751 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 752 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 753 754multiclass Atomic2Ops32<PatFrag Op> { 755 def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 756 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 757 Requires<[IsN64, HasStdEnc]> { 758 let DecoderNamespace = "Mips64"; 759 } 760} 761 762// Atomic Compare & Swap. 763class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 764 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 765 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 766 767multiclass AtomicCmpSwap32<PatFrag Op> { 768 def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>, 769 Requires<[NotN64, HasStdEnc]>; 770 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 771 Requires<[IsN64, HasStdEnc]> { 772 let DecoderNamespace = "Mips64"; 773 } 774} 775 776class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 777 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 778 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 779 let mayLoad = 1; 780} 781 782class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 783 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 784 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 785 let mayStore = 1; 786 let Constraints = "$rt = $dst"; 787} 788 789//===----------------------------------------------------------------------===// 790// Pseudo instructions 791//===----------------------------------------------------------------------===// 792 793// Return RA. 794let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 795def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 796 797let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 798def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 799 [(callseq_start timm:$amt)]>; 800def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 801 [(callseq_end timm:$amt1, timm:$amt2)]>; 802} 803 804let usesCustomInserter = 1 in { 805 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 806 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 807 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 808 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 809 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 810 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 811 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 812 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 813 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 814 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 815 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 816 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 817 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 818 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 819 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 820 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 821 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 822 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 823 824 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 825 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 826 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 827 828 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 829 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 830 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 831} 832 833//===----------------------------------------------------------------------===// 834// Instruction definition 835//===----------------------------------------------------------------------===// 836//===----------------------------------------------------------------------===// 837// MipsI Instructions 838//===----------------------------------------------------------------------===// 839 840/// Arithmetic Instructions (ALU Immediate) 841def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, 842 ADDI_FM<0x9>, IsAsCheapAsAMove; 843def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; 844def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 845def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 846def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; 847def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; 848def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; 849def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 850 851/// Arithmetic Instructions (3-Operand, R-Type) 852def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; 853def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 854def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 855def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; 856def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; 857def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 858def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 859def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 860def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 861def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 862def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>; 863 864/// Shift Instructions 865def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>; 866def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>; 867def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>; 868def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>; 869def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>; 870def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>; 871 872// Rotate Instructions 873let Predicates = [HasMips32r2, HasStdEnc] in { 874 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>; 875 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>; 876} 877 878/// Load and Store Instructions 879/// aligned 880defm LB : LoadM32<0x20, "lb", sextloadi8>; 881defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 882defm LH : LoadM32<0x21, "lh", sextloadi16>; 883defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 884defm LW : LoadM32<0x23, "lw", load>; 885defm SB : StoreM32<0x28, "sb", truncstorei8>; 886defm SH : StoreM32<0x29, "sh", truncstorei16>; 887defm SW : StoreM32<0x2b, "sw", store>; 888 889/// load/store left/right 890defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 891defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 892defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 893defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 894 895let hasSideEffects = 1 in 896def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 897 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 898{ 899 bits<5> stype; 900 let Opcode = 0; 901 let Inst{25-11} = 0; 902 let Inst{10-6} = stype; 903 let Inst{5-0} = 15; 904} 905 906/// Load-linked, Store-conditional 907def LL : LLBase<0x30, "ll", CPURegs, mem>, 908 Requires<[NotN64, HasStdEnc]>; 909def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 910 Requires<[IsN64, HasStdEnc]> { 911 let DecoderNamespace = "Mips64"; 912} 913 914def SC : SCBase<0x38, "sc", CPURegs, mem>, 915 Requires<[NotN64, HasStdEnc]>; 916def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 917 Requires<[IsN64, HasStdEnc]> { 918 let DecoderNamespace = "Mips64"; 919} 920 921/// Jump and Branch Instructions 922def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 923 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 924def JR : IndirectBranch<CPURegs>; 925def B : UncondBranch<"b">, B_FM; 926def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 927def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 928def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 929def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 930def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 931def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 932 933let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 934 hasDelaySlot = 1, Defs = [RA] in 935def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 936 937def JAL : JumpLink<0x03, "jal">; 938def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 939def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 940def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 941def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 942def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 943 944def RET : RetBase<CPURegs>; 945 946/// Multiply and Divide Instructions. 947def MULT : Mult32<0x18, "mult", IIImul>; 948def MULTu : Mult32<0x19, "multu", IIImul>; 949def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 950def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 951 952def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 953def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 954def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 955def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 956 957/// Sign Ext In Register Instructions. 958def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10>; 959def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18>; 960 961/// Count Leading 962def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>; 963def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>; 964 965/// Word Swap Bytes Within Halfwords 966def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 967 968/// No operation 969let addr=0 in 970 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 971 972// FrameIndexes are legalized when they are operands from load/store 973// instructions. The same not happens for stack address copies, so an 974// add op with mem ComplexPattern is used and the stack address copy 975// can be matched. It's similar to Sparc LEA_ADDRi 976def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 977 978// MADD*/MSUB* 979def MADD : MArithR<0, "madd", MipsMAdd, 1>; 980def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 981def MSUB : MArithR<4, "msub", MipsMSub>; 982def MSUBU : MArithR<5, "msubu", MipsMSubu>; 983 984def RDHWR : ReadHardware<CPURegs, HWRegs>; 985 986def EXT : ExtBase<0, "ext", CPURegs>; 987def INS : InsBase<4, "ins", CPURegs>; 988 989/// Move Control Registers From/To CPU Registers 990def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 991 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 992def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 993 994def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 995 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 996def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 997 998def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 999 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 1000def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 1001 1002def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 1003 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 1004def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 1005 1006//===----------------------------------------------------------------------===// 1007// Instruction aliases 1008//===----------------------------------------------------------------------===// 1009def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1010def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1011def : InstAlias<"addu $rs,$rt,$imm", 1012 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1013def : InstAlias<"add $rs,$rt,$imm", 1014 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1015def : InstAlias<"and $rs,$rt,$imm", 1016 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1017def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1018def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1019def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1020def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1021def : InstAlias<"slt $rs,$rt,$imm", 1022 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1023def : InstAlias<"xor $rs,$rt,$imm", 1024 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1025 1026//===----------------------------------------------------------------------===// 1027// Assembler Pseudo Instructions 1028//===----------------------------------------------------------------------===// 1029 1030class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 1031 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 1032 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1033def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 1034 1035class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 1036 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 1037 !strconcat(instr_asm, "\t$rt, $addr")> ; 1038def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 1039 1040class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 1041 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 1042 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1043def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 1044 1045 1046 1047//===----------------------------------------------------------------------===// 1048// Arbitrary patterns that map to one or more instructions 1049//===----------------------------------------------------------------------===// 1050 1051// Small immediates 1052def : MipsPat<(i32 immSExt16:$in), 1053 (ADDiu ZERO, imm:$in)>; 1054def : MipsPat<(i32 immZExt16:$in), 1055 (ORi ZERO, imm:$in)>; 1056def : MipsPat<(i32 immLow16Zero:$in), 1057 (LUi (HI16 imm:$in))>; 1058 1059// Arbitrary immediates 1060def : MipsPat<(i32 imm:$imm), 1061 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1062 1063// Carry MipsPatterns 1064def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1065 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1066def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1067 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1068def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1069 (ADDiu CPURegs:$src, imm:$imm)>; 1070 1071// Call 1072def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1073 (JAL tglobaladdr:$dst)>; 1074def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1075 (JAL texternalsym:$dst)>; 1076//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1077// (JALR CPURegs:$dst)>; 1078 1079// Tail call 1080def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1081 (TAILCALL tglobaladdr:$dst)>; 1082def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1083 (TAILCALL texternalsym:$dst)>; 1084// hi/lo relocs 1085def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1086def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1087def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1088def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1089def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1090def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1091 1092def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1093def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1094def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1095def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1096def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1097def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1098 1099def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1100 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1101def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1102 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1103def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1104 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1105def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1106 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1107def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1108 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1109 1110// gp_rel relocs 1111def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1112 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1113def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1114 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1115 1116// wrapper_pic 1117class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1118 MipsPat<(MipsWrapper RC:$gp, node:$in), 1119 (ADDiuOp RC:$gp, node:$in)>; 1120 1121def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1122def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1123def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1124def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1125def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1126def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1127 1128// Mips does not have "not", so we expand our way 1129def : MipsPat<(not CPURegs:$in), 1130 (NOR CPURegs:$in, ZERO)>; 1131 1132// extended loads 1133let Predicates = [NotN64, HasStdEnc] in { 1134 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1135 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1136 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1137} 1138let Predicates = [IsN64, HasStdEnc] in { 1139 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1140 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1141 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1142} 1143 1144// peepholes 1145let Predicates = [NotN64, HasStdEnc] in { 1146 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1147} 1148let Predicates = [IsN64, HasStdEnc] in { 1149 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1150} 1151 1152// brcond patterns 1153multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1154 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1155 Instruction SLTiuOp, Register ZEROReg> { 1156def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1157 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1158def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1159 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1160 1161def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1162 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1163def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1164 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1165def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1166 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1167def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1168 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1169 1170def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1171 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1172def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1173 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1174 1175def : MipsPat<(brcond RC:$cond, bb:$dst), 1176 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1177} 1178 1179defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1180 1181// setcc patterns 1182multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1183 Instruction SLTuOp, Register ZEROReg> { 1184 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1185 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1186 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1187 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1188} 1189 1190multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1191 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1192 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1193 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1194 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1195} 1196 1197multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1198 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1199 (SLTOp RC:$rhs, RC:$lhs)>; 1200 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1201 (SLTuOp RC:$rhs, RC:$lhs)>; 1202} 1203 1204multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1205 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1206 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1207 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1208 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1209} 1210 1211multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1212 Instruction SLTiuOp> { 1213 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1214 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1215 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1216 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1217} 1218 1219defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1220defm : SetlePats<CPURegs, SLT, SLTu>; 1221defm : SetgtPats<CPURegs, SLT, SLTu>; 1222defm : SetgePats<CPURegs, SLT, SLTu>; 1223defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1224 1225// bswap pattern 1226def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1227 1228//===----------------------------------------------------------------------===// 1229// Floating Point Support 1230//===----------------------------------------------------------------------===// 1231 1232include "MipsInstrFPU.td" 1233include "Mips64InstrInfo.td" 1234include "MipsCondMov.td" 1235 1236// 1237// Mips16 1238 1239include "Mips16InstrFormats.td" 1240include "Mips16InstrInfo.td" 1241 1242// DSP 1243include "MipsDSPInstrFormats.td" 1244include "MipsDSPInstrInfo.td" 1245 1246