MipsInstrInfo.td revision 397f6da28cc889597e8c267e15154f1f70a0922a
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 27def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 28 SDTCisVT<1, i32>, 29 SDTCisSameAs<1, 2>]>; 30def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 31 SDTCisSameAs<1, 2>]>; 32def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 33 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 34 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 35def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 36 37def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 38 39def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 40 41def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 43def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 45 SDTCisSameAs<0, 4>]>; 46 47def SDTMipsLoadLR : SDTypeProfile<1, 2, 48 [SDTCisInt<0>, SDTCisPtrTy<1>, 49 SDTCisSameAs<0, 2>]>; 50 51// Call 52def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 53 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 54 SDNPVariadic]>; 55 56// Tail call 57def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 58 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 59 60// Hi and Lo nodes are used to handle global addresses. Used on 61// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 62// static model. (nothing to do with Mips Registers Hi and Lo) 63def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 64def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 65def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 66 67// TlsGd node is used to handle General Dynamic TLS 68def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 69 70// TprelHi and TprelLo nodes are used to handle Local Exec TLS 71def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 72def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 73 74// Thread pointer 75def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 76 77// Return 78def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 79 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 80 81// These are target-independent nodes, but have target-specific formats. 82def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 83 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 84def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 85 [SDNPHasChain, SDNPSideEffect, 86 SDNPOptInGlue, SDNPOutGlue]>; 87 88// Nodes used to extract LO/HI registers. 89def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 90def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, 186 AssemblerPredicate<"FeatureMicroMips">; 187def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, 188 AssemblerPredicate<"!FeatureMicroMips">; 189def IsLE : Predicate<"Subtarget.isLittle()">; 190def IsBE : Predicate<"!Subtarget.isLittle()">; 191 192class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 193 let Predicates = [HasStdEnc]; 194} 195 196class IsCommutable { 197 bit isCommutable = 1; 198} 199 200class IsBranch { 201 bit isBranch = 1; 202} 203 204class IsReturn { 205 bit isReturn = 1; 206} 207 208class IsCall { 209 bit isCall = 1; 210} 211 212class IsTailCall { 213 bit isCall = 1; 214 bit isTerminator = 1; 215 bit isReturn = 1; 216 bit isBarrier = 1; 217 bit hasExtraSrcRegAllocReq = 1; 218 bit isCodeGenOnly = 1; 219} 220 221class IsAsCheapAsAMove { 222 bit isAsCheapAsAMove = 1; 223} 224 225class NeverHasSideEffects { 226 bit neverHasSideEffects = 1; 227} 228 229//===----------------------------------------------------------------------===// 230// Instruction format superclass 231//===----------------------------------------------------------------------===// 232 233include "MipsInstrFormats.td" 234 235//===----------------------------------------------------------------------===// 236// Mips Operand, Complex Patterns and Transformations Definitions. 237//===----------------------------------------------------------------------===// 238 239// Instruction operand types 240def jmptarget : Operand<OtherVT> { 241 let EncoderMethod = "getJumpTargetOpValue"; 242} 243def brtarget : Operand<OtherVT> { 244 let EncoderMethod = "getBranchTargetOpValue"; 245 let OperandType = "OPERAND_PCREL"; 246 let DecoderMethod = "DecodeBranchTarget"; 247} 248def calltarget : Operand<iPTR> { 249 let EncoderMethod = "getJumpTargetOpValue"; 250} 251 252def simm16 : Operand<i32> { 253 let DecoderMethod= "DecodeSimm16"; 254} 255 256def simm20 : Operand<i32> { 257} 258 259def uimm20 : Operand<i32> { 260} 261 262def uimm10 : Operand<i32> { 263} 264 265def simm16_64 : Operand<i64> { 266 let DecoderMethod = "DecodeSimm16"; 267} 268 269// Unsigned Operand 270def uimm5 : Operand<i32> { 271 let PrintMethod = "printUnsignedImm"; 272} 273 274def uimm6 : Operand<i32> { 275 let PrintMethod = "printUnsignedImm"; 276} 277 278def uimm16 : Operand<i32> { 279 let PrintMethod = "printUnsignedImm"; 280} 281 282def MipsMemAsmOperand : AsmOperandClass { 283 let Name = "Mem"; 284 let ParserMethod = "parseMemOperand"; 285} 286 287def MipsInvertedImmoperand : AsmOperandClass { 288 let Name = "InvNum"; 289 let RenderMethod = "addImmOperands"; 290 let ParserMethod = "parseInvNum"; 291} 292 293def PtrRegAsmOperand : AsmOperandClass { 294 let Name = "PtrReg"; 295 let ParserMethod = "parsePtrReg"; 296} 297 298 299def InvertedImOperand : Operand<i32> { 300 let ParserMatchClass = MipsInvertedImmoperand; 301} 302 303// Address operand 304def mem : Operand<iPTR> { 305 let PrintMethod = "printMemOperand"; 306 let MIOperandInfo = (ops ptr_rc, simm16); 307 let EncoderMethod = "getMemEncoding"; 308 let ParserMatchClass = MipsMemAsmOperand; 309 let OperandType = "OPERAND_MEMORY"; 310} 311 312def mem_ea : Operand<iPTR> { 313 let PrintMethod = "printMemOperandEA"; 314 let MIOperandInfo = (ops ptr_rc, simm16); 315 let EncoderMethod = "getMemEncoding"; 316 let OperandType = "OPERAND_MEMORY"; 317} 318 319def PtrRC : Operand<iPTR> { 320 let MIOperandInfo = (ops ptr_rc); 321 let DecoderMethod = "DecodePtrRegisterClass"; 322 let ParserMatchClass = PtrRegAsmOperand; 323} 324 325// size operand of ext instruction 326def size_ext : Operand<i32> { 327 let EncoderMethod = "getSizeExtEncoding"; 328 let DecoderMethod = "DecodeExtSize"; 329} 330 331// size operand of ins instruction 332def size_ins : Operand<i32> { 333 let EncoderMethod = "getSizeInsEncoding"; 334 let DecoderMethod = "DecodeInsSize"; 335} 336 337// Transformation Function - get the lower 16 bits. 338def LO16 : SDNodeXForm<imm, [{ 339 return getImm(N, N->getZExtValue() & 0xFFFF); 340}]>; 341 342// Transformation Function - get the higher 16 bits. 343def HI16 : SDNodeXForm<imm, [{ 344 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 345}]>; 346 347// Plus 1. 348def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 349 350// Node immediate fits as 16-bit sign extended on target immediate. 351// e.g. addi, andi 352def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 353 354// Node immediate fits as 16-bit sign extended on target immediate. 355// e.g. addi, andi 356def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 357 358// Node immediate fits as 15-bit sign extended on target immediate. 359// e.g. addi, andi 360def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 361 362// Node immediate fits as 16-bit zero extended on target immediate. 363// The LO16 param means that only the lower 16 bits of the node 364// immediate are caught. 365// e.g. addiu, sltiu 366def immZExt16 : PatLeaf<(imm), [{ 367 if (N->getValueType(0) == MVT::i32) 368 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 369 else 370 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 371}], LO16>; 372 373// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 374def immLow16Zero : PatLeaf<(imm), [{ 375 int64_t Val = N->getSExtValue(); 376 return isInt<32>(Val) && !(Val & 0xffff); 377}]>; 378 379// shamt field must fit in 5 bits. 380def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 381 382// True if (N + 1) fits in 16-bit field. 383def immSExt16Plus1 : PatLeaf<(imm), [{ 384 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 385}]>; 386 387// Mips Address Mode! SDNode frameindex could possibily be a match 388// since load and store instructions from stack used it. 389def addr : 390 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 391 392def addrRegImm : 393 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 394 395def addrRegReg : 396 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 397 398def addrDefault : 399 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 400 401//===----------------------------------------------------------------------===// 402// Instructions specific format 403//===----------------------------------------------------------------------===// 404 405// Arithmetic and logical instructions with 3 register operands. 406class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 407 InstrItinClass Itin = NoItinerary, 408 SDPatternOperator OpNode = null_frag>: 409 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 410 !strconcat(opstr, "\t$rd, $rs, $rt"), 411 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 412 let isCommutable = isComm; 413 let isReMaterializable = 1; 414} 415 416// Arithmetic and logical instructions with 2 register operands. 417class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 418 InstrItinClass Itin = NoItinerary, 419 SDPatternOperator imm_type = null_frag, 420 SDPatternOperator OpNode = null_frag> : 421 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 422 !strconcat(opstr, "\t$rt, $rs, $imm16"), 423 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 424 Itin, FrmI, opstr> { 425 let isReMaterializable = 1; 426 let TwoOperandAliasConstraint = "$rs = $rt"; 427} 428 429// Arithmetic Multiply ADD/SUB 430class MArithR<string opstr, bit isComm = 0> : 431 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 432 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> { 433 let Defs = [HI0, LO0]; 434 let Uses = [HI0, LO0]; 435 let isCommutable = isComm; 436} 437 438// Logical 439class LogicNOR<string opstr, RegisterOperand RO>: 440 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 441 !strconcat(opstr, "\t$rd, $rs, $rt"), 442 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> { 443 let isCommutable = 1; 444} 445 446// Shifts 447class shift_rotate_imm<string opstr, Operand ImmOpnd, 448 RegisterOperand RO, SDPatternOperator OpNode = null_frag, 449 SDPatternOperator PF = null_frag> : 450 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 451 !strconcat(opstr, "\t$rd, $rt, $shamt"), 452 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>; 453 454class shift_rotate_reg<string opstr, RegisterOperand RO, 455 SDPatternOperator OpNode = null_frag>: 456 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 457 !strconcat(opstr, "\t$rd, $rt, $rs"), 458 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>; 459 460// Load Upper Imediate 461class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 462 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 463 [], IIArith, FrmI, opstr>, IsAsCheapAsAMove { 464 let neverHasSideEffects = 1; 465 let isReMaterializable = 1; 466} 467 468// Memory Load/Store 469class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 470 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 471 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 472 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 473 let DecoderMethod = "DecodeMem"; 474 let canFoldAsLoad = 1; 475 let mayLoad = 1; 476} 477 478class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 479 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 480 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 481 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 482 let DecoderMethod = "DecodeMem"; 483 let mayStore = 1; 484} 485 486// Load/Store Left/Right 487let canFoldAsLoad = 1 in 488class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 489 InstrItinClass Itin> : 490 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 491 !strconcat(opstr, "\t$rt, $addr"), 492 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 493 let DecoderMethod = "DecodeMem"; 494 string Constraints = "$src = $rt"; 495} 496 497class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 498 InstrItinClass Itin> : 499 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 500 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 501 let DecoderMethod = "DecodeMem"; 502} 503 504// Conditional Branch 505class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> : 506 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset), 507 !strconcat(opstr, "\t$rs, $rt, $offset"), 508 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 509 FrmI> { 510 let isBranch = 1; 511 let isTerminator = 1; 512 let hasDelaySlot = 1; 513 let Defs = [AT]; 514} 515 516class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> : 517 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 518 !strconcat(opstr, "\t$rs, $offset"), 519 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 520 let isBranch = 1; 521 let isTerminator = 1; 522 let hasDelaySlot = 1; 523 let Defs = [AT]; 524} 525 526// SetCC 527class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 528 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 529 !strconcat(opstr, "\t$rd, $rs, $rt"), 530 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 531 IIslt, FrmR, opstr>; 532 533class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 534 RegisterOperand RO>: 535 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 536 !strconcat(opstr, "\t$rt, $rs, $imm16"), 537 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 538 IIslt, FrmI, opstr>; 539 540// Jump 541class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 542 SDPatternOperator targetoperator> : 543 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 544 [(operator targetoperator:$target)], IIBranch, FrmJ> { 545 let isTerminator=1; 546 let isBarrier=1; 547 let hasDelaySlot = 1; 548 let DecoderMethod = "DecodeJumpTarget"; 549 let Defs = [AT]; 550} 551 552// Unconditional branch 553class UncondBranch<Instruction BEQInst> : 554 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, 555 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 556 let isBranch = 1; 557 let isTerminator = 1; 558 let isBarrier = 1; 559 let hasDelaySlot = 1; 560 let Predicates = [RelocPIC, HasStdEnc]; 561 let Defs = [AT]; 562} 563 564// Base class for indirect branch and return instruction classes. 565let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 566class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>: 567 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>; 568 569// Indirect branch 570class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> { 571 let isBranch = 1; 572 let isIndirectBranch = 1; 573} 574 575// Return instruction 576class RetBase<RegisterOperand RO>: JumpFR<RO> { 577 let isReturn = 1; 578 let isCodeGenOnly = 1; 579 let hasCtrlDep = 1; 580 let hasExtraSrcRegAllocReq = 1; 581} 582 583// Jump and Link (Call) 584let isCall=1, hasDelaySlot=1, Defs = [RA] in { 585 class JumpLink<string opstr> : 586 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 587 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 588 let DecoderMethod = "DecodeJumpTarget"; 589 } 590 591 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 592 Register RetReg, RegisterOperand ResRO = RO>: 593 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 594 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 595 596 class JumpLinkReg<string opstr, RegisterOperand RO>: 597 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 598 [], IIBranch, FrmR>; 599 600 class BGEZAL_FT<string opstr, RegisterOperand RO> : 601 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 602 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 603 604} 605 606class BAL_BR_Pseudo<Instruction RealInst> : 607 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 608 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 609 let isBranch = 1; 610 let isTerminator = 1; 611 let isBarrier = 1; 612 let hasDelaySlot = 1; 613 let Defs = [RA]; 614} 615 616// Syscall 617class SYS_FT<string opstr> : 618 InstSE<(outs), (ins uimm20:$code_), 619 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; 620// Break 621class BRK_FT<string opstr> : 622 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 623 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; 624 625// (D)Eret 626class ER_FT<string opstr> : 627 InstSE<(outs), (ins), 628 opstr, [], NoItinerary, FrmOther>; 629 630// Interrupts 631class DEI_FT<string opstr, RegisterOperand RO> : 632 InstSE<(outs RO:$rt), (ins), 633 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>; 634 635// Wait 636class WAIT_FT<string opstr> : 637 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> { 638 let Inst{31-26} = 0x10; 639 let Inst{25} = 1; 640 let Inst{24-6} = 0; 641 let Inst{5-0} = 0x20; 642} 643 644// Sync 645let hasSideEffects = 1 in 646class SYNC_FT : 647 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 648 NoItinerary, FrmOther>; 649 650let hasSideEffects = 1 in 651class TEQ_FT<string opstr, RegisterOperand RO> : 652 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 653 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; 654 655class TEQI_FT<string opstr, RegisterOperand RO> : 656 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 657 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>; 658// Mul, Div 659class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 660 list<Register> DefRegs> : 661 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 662 itin, FrmR, opstr> { 663 let isCommutable = 1; 664 let Defs = DefRegs; 665 let neverHasSideEffects = 1; 666} 667 668// Pseudo multiply/divide instruction with explicit accumulator register 669// operands. 670class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 671 SDPatternOperator OpNode, InstrItinClass Itin, 672 bit IsComm = 1, bit HasSideEffects = 0, 673 bit UsesCustomInserter = 0> : 674 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 675 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 676 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 677 let isCommutable = IsComm; 678 let hasSideEffects = HasSideEffects; 679 let usesCustomInserter = UsesCustomInserter; 680} 681 682// Pseudo multiply add/sub instruction with explicit accumulator register 683// operands. 684class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 685 : PseudoSE<(outs ACC64:$ac), 686 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 687 [(set ACC64:$ac, 688 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 689 IIImult>, 690 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 691 string Constraints = "$acin = $ac"; 692} 693 694class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 695 list<Register> DefRegs> : 696 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 697 [], itin, FrmR, opstr> { 698 let Defs = DefRegs; 699} 700 701// Move from Hi/Lo 702class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 703 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 704 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>; 705 706class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 707 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR, 708 opstr> { 709 let Uses = [UseReg]; 710 let neverHasSideEffects = 1; 711} 712 713class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 714 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, 715 FrmR, opstr> { 716 let Defs = DefRegs; 717 let neverHasSideEffects = 1; 718} 719 720class EffectiveAddress<string opstr, RegisterOperand RO> : 721 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 722 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> { 723 let isCodeGenOnly = 1; 724 let DecoderMethod = "DecodeMem"; 725} 726 727// Count Leading Ones/Zeros in Word 728class CountLeading0<string opstr, RegisterOperand RO>: 729 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 730 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>, 731 Requires<[HasBitCount, HasStdEnc]>; 732 733class CountLeading1<string opstr, RegisterOperand RO>: 734 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 735 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>, 736 Requires<[HasBitCount, HasStdEnc]>; 737 738 739// Sign Extend in Register. 740class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> : 741 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 742 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> { 743 let Predicates = [HasSEInReg, HasStdEnc]; 744} 745 746// Subword Swap 747class SubwordSwap<string opstr, RegisterOperand RO>: 748 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 749 NoItinerary, FrmR, opstr> { 750 let Predicates = [HasSwap, HasStdEnc]; 751 let neverHasSideEffects = 1; 752} 753 754// Read Hardware 755class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 756 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 757 IIArith, FrmR>; 758 759// Ext and Ins 760class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 761 SDPatternOperator Op = null_frag>: 762 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size), 763 !strconcat(opstr, " $rt, $rs, $pos, $size"), 764 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary, 765 FrmR, opstr> { 766 let Predicates = [HasMips32r2, HasStdEnc]; 767} 768 769class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 770 SDPatternOperator Op = null_frag>: 771 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), 772 !strconcat(opstr, " $rt, $rs, $pos, $size"), 773 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], 774 NoItinerary, FrmR, opstr> { 775 let Predicates = [HasMips32r2, HasStdEnc]; 776 let Constraints = "$src = $rt"; 777} 778 779// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 780class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 781 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 782 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 783 784// Atomic Compare & Swap. 785class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 786 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 787 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 788 789class LLBase<string opstr, RegisterOperand RO> : 790 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 791 [], NoItinerary, FrmI> { 792 let DecoderMethod = "DecodeMem"; 793 let mayLoad = 1; 794} 795 796class SCBase<string opstr, RegisterOperand RO> : 797 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 798 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 799 let DecoderMethod = "DecodeMem"; 800 let mayStore = 1; 801 let Constraints = "$rt = $dst"; 802} 803 804class MFC3OP<string asmstr, RegisterOperand RO> : 805 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 806 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 807 808class TrapBase<Instruction RealInst> 809 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>, 810 PseudoInstExpansion<(RealInst 0, 0)> { 811 let isBarrier = 1; 812 let isTerminator = 1; 813 let isCodeGenOnly = 1; 814} 815 816//===----------------------------------------------------------------------===// 817// Pseudo instructions 818//===----------------------------------------------------------------------===// 819 820// Return RA. 821let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 822def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 823 824let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 825def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 826 [(callseq_start timm:$amt)]>; 827def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 828 [(callseq_end timm:$amt1, timm:$amt2)]>; 829} 830 831let usesCustomInserter = 1 in { 832 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 833 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 834 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 835 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 836 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 837 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 838 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 839 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 840 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 841 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 842 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 843 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 844 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 845 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 846 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 847 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 848 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 849 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 850 851 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 852 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 853 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 854 855 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 856 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 857 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 858} 859 860/// Pseudo instructions for loading and storing accumulator registers. 861let isPseudo = 1, isCodeGenOnly = 1 in { 862 def LOAD_ACC64 : Load<"", ACC64>; 863 def STORE_ACC64 : Store<"", ACC64>; 864} 865 866//===----------------------------------------------------------------------===// 867// Instruction definition 868//===----------------------------------------------------------------------===// 869//===----------------------------------------------------------------------===// 870// MipsI Instructions 871//===----------------------------------------------------------------------===// 872 873/// Arithmetic Instructions (ALU Immediate) 874def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16, 875 add>, 876 ADDI_FM<0x9>, IsAsCheapAsAMove; 877def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>; 878def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 879 SLTI_FM<0xa>; 880def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 881 SLTI_FM<0xb>; 882def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16, 883 and>, 884 ADDI_FM<0xc>; 885def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16, 886 or>, 887 ADDI_FM<0xd>; 888def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16, 889 xor>, 890 ADDI_FM<0xe>; 891def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 892 893/// Arithmetic Instructions (3-Operand, R-Type) 894def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>, 895 ADD_FM<0, 0x21>; 896def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>, 897 ADD_FM<0, 0x23>; 898let Defs = [HI0, LO0] in 899def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>, 900 ADD_FM<0x1c, 2>; 901def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 902def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 903def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 904def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 905def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>, 906 ADD_FM<0, 0x24>; 907def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>, 908 ADD_FM<0, 0x25>; 909def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>, 910 ADD_FM<0, 0x26>; 911def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 912 913/// Shift Instructions 914def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>, 915 SRA_FM<0, 0>; 916def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>, 917 SRA_FM<2, 0>; 918def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>, 919 SRA_FM<3, 0>; 920def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>; 921def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>; 922def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>; 923 924// Rotate Instructions 925let Predicates = [HasMips32r2, HasStdEnc] in { 926 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr, 927 immZExt5>, 928 SRA_FM<2, 1>; 929 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>, 930 SRLV_FM<6, 1>; 931} 932 933/// Load and Store Instructions 934/// aligned 935def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>; 936def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel, 937 LW_FM<0x24>; 938def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel, 939 LW_FM<0x21>; 940def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; 941def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, 942 LW_FM<0x23>; 943def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; 944def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; 945def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; 946 947/// load/store left/right 948def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>; 949def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>; 950def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>; 951def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>; 952 953def SYNC : SYNC_FT, SYNC_FM; 954def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 955def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; 956def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; 957def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; 958def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; 959def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; 960 961def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>; 962def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>; 963def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>; 964def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>; 965def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>; 966def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>; 967 968def BREAK : BRK_FT<"break">, BRK_FM<0xd>; 969def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; 970def TRAP : TrapBase<BREAK>; 971 972def ERET : ER_FT<"eret">, ER_FM<0x18>; 973def DERET : ER_FT<"deret">, ER_FM<0x1f>; 974 975def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; 976def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>; 977 978def WAIT : WAIT_FT<"wait">; 979 980/// Load-linked, Store-conditional 981def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>; 982def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>; 983 984/// Jump and Branch Instructions 985def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 986 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 987def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>; 988def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>; 989def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>; 990def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>; 991def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>; 992def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>; 993def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>; 994def B : UncondBranch<BEQ>; 995 996def JAL : JumpLink<"jal">, FJ<3>; 997def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 998def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 999def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>; 1000def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>; 1001def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 1002def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 1003def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall; 1004 1005def RET : RetBase<GPR32Opnd>, MTLO_FM<8>; 1006 1007// Exception handling related node and instructions. 1008// The conversion sequence is: 1009// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1010// MIPSeh_return -> (stack change + indirect branch) 1011// 1012// MIPSeh_return takes the place of regular return instruction 1013// but takes two arguments (V1, V0) which are used for storing 1014// the offset and return address respectively. 1015def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1016 1017def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1018 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1019 1020let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1021 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1022 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1023 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1024 GPR64:$dst), 1025 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1026} 1027 1028/// Multiply and Divide Instructions. 1029def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>, 1030 MULT_FM<0, 0x18>; 1031def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>, 1032 MULT_FM<0, 0x19>; 1033def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>; 1034def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>; 1035 1036def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; 1037def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; 1038def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>; 1039def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>; 1040 1041/// Sign Ext In Register Instructions. 1042def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; 1043def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; 1044 1045/// Count Leading 1046def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; 1047def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; 1048 1049/// Word Swap Bytes Within Halfwords 1050def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; 1051 1052/// No operation. 1053def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1054 1055// FrameIndexes are legalized when they are operands from load/store 1056// instructions. The same not happens for stack address copies, so an 1057// add op with mem ComplexPattern is used and the stack address copy 1058// can be matched. It's similar to Sparc LEA_ADDRi 1059def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1060 1061// MADD*/MSUB* 1062def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1063def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1064def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>; 1065def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>; 1066 1067let Predicates = [HasStdEnc, NotDSP] in { 1068def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; 1069def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; 1070def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>; 1071def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>; 1072def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1073def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1074def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1075def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1076} 1077 1078def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, 1079 0, 1, 1>; 1080def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, 1081 0, 1, 1>; 1082 1083def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1084 1085def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; 1086def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; 1087 1088/// Move Control Registers From/To CPU Registers 1089def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>; 1090def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>; 1091def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1092def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1093 1094//===----------------------------------------------------------------------===// 1095// Instruction aliases 1096//===----------------------------------------------------------------------===// 1097def : InstAlias<"move $dst, $src", 1098 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1099 Requires<[NotMips64]>; 1100def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; 1101def : InstAlias<"addu $rs, $rt, $imm", 1102 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1103def : InstAlias<"add $rs, $rt, $imm", 1104 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1105def : InstAlias<"and $rs, $rt, $imm", 1106 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1107def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1108def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1109def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1110def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1111def : InstAlias<"not $rt, $rs", 1112 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1113def : InstAlias<"neg $rt, $rs", 1114 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1115def : InstAlias<"negu $rt, $rs", 1116 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1117def : InstAlias<"slt $rs, $rt, $imm", 1118 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1119def : InstAlias<"xor $rs, $rt, $imm", 1120 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1121def : InstAlias<"or $rs, $rt, $imm", 1122 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1123def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1124def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1125def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1126def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1127def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1128def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1129def : InstAlias<"bnez $rs,$offset", 1130 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1131def : InstAlias<"beqz $rs,$offset", 1132 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1133def : InstAlias<"syscall", (SYSCALL 0), 1>; 1134 1135def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1136def : InstAlias<"break", (BREAK 0, 0), 1>; 1137def : InstAlias<"ei", (EI ZERO), 1>; 1138def : InstAlias<"di", (DI ZERO), 1>; 1139 1140def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1141def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1142def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1143def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1144def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1145def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1146def : InstAlias<"sub, $rd, $rs, $imm", 1147 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; 1148def : InstAlias<"subu, $rd, $rs, $imm", 1149 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; 1150 1151//===----------------------------------------------------------------------===// 1152// Assembler Pseudo Instructions 1153//===----------------------------------------------------------------------===// 1154 1155class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1156 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1157 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1158def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>; 1159 1160class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1161 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1162 !strconcat(instr_asm, "\t$rt, $addr")> ; 1163def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1164 1165class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1166 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1167 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1168def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; 1169 1170//===----------------------------------------------------------------------===// 1171// Arbitrary patterns that map to one or more instructions 1172//===----------------------------------------------------------------------===// 1173 1174// Load/store pattern templates. 1175class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1176 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1177 1178class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1179 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1180 1181// Small immediates 1182def : MipsPat<(i32 immSExt16:$in), 1183 (ADDiu ZERO, imm:$in)>; 1184def : MipsPat<(i32 immZExt16:$in), 1185 (ORi ZERO, imm:$in)>; 1186def : MipsPat<(i32 immLow16Zero:$in), 1187 (LUi (HI16 imm:$in))>; 1188 1189// Arbitrary immediates 1190def : MipsPat<(i32 imm:$imm), 1191 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1192 1193// Carry MipsPatterns 1194def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1195 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1196let Predicates = [HasStdEnc, NotDSP] in { 1197 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1198 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1199 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1200 (ADDiu GPR32:$src, imm:$imm)>; 1201} 1202 1203// Call 1204def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1205 (JAL tglobaladdr:$dst)>; 1206def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1207 (JAL texternalsym:$dst)>; 1208//def : MipsPat<(MipsJmpLink GPR32:$dst), 1209// (JALR GPR32:$dst)>; 1210 1211// Tail call 1212def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1213 (TAILCALL tglobaladdr:$dst)>; 1214def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1215 (TAILCALL texternalsym:$dst)>; 1216// hi/lo relocs 1217def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1218def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1219def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1220def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1221def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1222def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1223 1224def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1225def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1226def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1227def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1228def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1229def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1230 1231def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1232 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1233def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1234 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1235def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1236 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1237def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1238 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1239def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1240 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1241 1242// gp_rel relocs 1243def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1244 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1245def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1246 (ADDiu GPR32:$gp, tconstpool:$in)>; 1247 1248// wrapper_pic 1249class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1250 MipsPat<(MipsWrapper RC:$gp, node:$in), 1251 (ADDiuOp RC:$gp, node:$in)>; 1252 1253def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1254def : WrapperPat<tconstpool, ADDiu, GPR32>; 1255def : WrapperPat<texternalsym, ADDiu, GPR32>; 1256def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1257def : WrapperPat<tjumptable, ADDiu, GPR32>; 1258def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1259 1260// Mips does not have "not", so we expand our way 1261def : MipsPat<(not GPR32:$in), 1262 (NOR GPR32Opnd:$in, ZERO)>; 1263 1264// extended loads 1265let Predicates = [HasStdEnc] in { 1266 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1267 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1268 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1269} 1270 1271// peepholes 1272let Predicates = [HasStdEnc] in 1273def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1274 1275// brcond patterns 1276multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1277 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1278 Instruction SLTiuOp, Register ZEROReg> { 1279def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1280 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1281def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1282 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1283 1284def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1285 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1286def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1287 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1288def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1289 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1290def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1291 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1292def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1293 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1294def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1295 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1296 1297def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1298 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1299def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1300 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1301 1302def : MipsPat<(brcond RC:$cond, bb:$dst), 1303 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1304} 1305 1306defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1307 1308def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1309 (BLEZ i32:$lhs, bb:$dst)>; 1310def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1311 (BGEZ i32:$lhs, bb:$dst)>; 1312 1313// setcc patterns 1314multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1315 Instruction SLTuOp, Register ZEROReg> { 1316 def : MipsPat<(seteq RC:$lhs, 0), 1317 (SLTiuOp RC:$lhs, 1)>; 1318 def : MipsPat<(setne RC:$lhs, 0), 1319 (SLTuOp ZEROReg, RC:$lhs)>; 1320 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1321 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1322 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1323 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1324} 1325 1326multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1327 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1328 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1329 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1330 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1331} 1332 1333multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1334 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1335 (SLTOp RC:$rhs, RC:$lhs)>; 1336 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1337 (SLTuOp RC:$rhs, RC:$lhs)>; 1338} 1339 1340multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1341 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1342 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1343 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1344 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1345} 1346 1347multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1348 Instruction SLTiuOp> { 1349 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1350 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1351 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1352 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1353} 1354 1355defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1356defm : SetlePats<GPR32, SLT, SLTu>; 1357defm : SetgtPats<GPR32, SLT, SLTu>; 1358defm : SetgePats<GPR32, SLT, SLTu>; 1359defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1360 1361// bswap pattern 1362def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1363 1364// Load halfword/word patterns. 1365let AddedComplexity = 40 in { 1366 let Predicates = [HasStdEnc] in { 1367 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1368 def : LoadRegImmPat<LH, i32, sextloadi16>; 1369 def : LoadRegImmPat<LW, i32, load>; 1370 } 1371} 1372 1373//===----------------------------------------------------------------------===// 1374// Floating Point Support 1375//===----------------------------------------------------------------------===// 1376 1377include "MipsInstrFPU.td" 1378include "Mips64InstrInfo.td" 1379include "MipsCondMov.td" 1380 1381// 1382// Mips16 1383 1384include "Mips16InstrFormats.td" 1385include "Mips16InstrInfo.td" 1386 1387// DSP 1388include "MipsDSPInstrFormats.td" 1389include "MipsDSPInstrInfo.td" 1390 1391// MSA 1392include "MipsMSAInstrFormats.td" 1393include "MipsMSAInstrInfo.td" 1394 1395// Micromips 1396include "MicroMipsInstrFormats.td" 1397include "MicroMipsInstrInfo.td" 1398