MipsInstrInfo.td revision 5c5402564515ad87425af9881619545c096b84b9
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 16-bit zero extended on target immediate. 302// The LO16 param means that only the lower 16 bits of the node 303// immediate are caught. 304// e.g. addiu, sltiu 305def immZExt16 : PatLeaf<(imm), [{ 306 if (N->getValueType(0) == MVT::i32) 307 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 308 else 309 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 310}], LO16>; 311 312// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 313def immLow16Zero : PatLeaf<(imm), [{ 314 int64_t Val = N->getSExtValue(); 315 return isInt<32>(Val) && !(Val & 0xffff); 316}]>; 317 318// shamt field must fit in 5 bits. 319def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 320 321// Mips Address Mode! SDNode frameindex could possibily be a match 322// since load and store instructions from stack used it. 323def addr : 324 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 325 326//===----------------------------------------------------------------------===// 327// Instructions specific format 328//===----------------------------------------------------------------------===// 329 330/// Move Control Registers From/To CPU Registers 331def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 332 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 333def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 334 335def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 336 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 337def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 338 339def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 340 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 341def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 342 343def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 344 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 345def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 346 347// Arithmetic and logical instructions with 3 register operands. 348class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0, 349 InstrItinClass Itin = NoItinerary, 350 SDPatternOperator OpNode = null_frag>: 351 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 352 !strconcat(opstr, "\t$rd, $rs, $rt"), 353 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 354 let isCommutable = isComm; 355 let isReMaterializable = 1; 356} 357 358// Arithmetic and logical instructions with 2 register operands. 359class ArithLogicI<string opstr, Operand Od, RegisterClass RC, 360 SDPatternOperator imm_type = null_frag, 361 SDPatternOperator OpNode = null_frag> : 362 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 363 !strconcat(opstr, "\t$rt, $rs, $imm16"), 364 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 365 let isReMaterializable = 1; 366} 367 368// Arithmetic Multiply ADD/SUB 369let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 370class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 371 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 372 !strconcat(instr_asm, "\t$rs, $rt"), 373 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 374 let rd = 0; 375 let shamt = 0; 376 let isCommutable = isComm; 377} 378 379// Logical 380class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 381 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 382 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 383 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 384 let shamt = 0; 385 let isCommutable = 1; 386} 387 388// Shifts 389class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd, 390 RegisterClass RC, SDPatternOperator OpNode> : 391 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 392 !strconcat(opstr, "\t$rd, $rt, $shamt"), 393 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 394 395// 32-bit shift instructions. 396class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> : 397 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>; 398 399class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>: 400 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 401 !strconcat(opstr, "\t$rd, $rt, $rs"), 402 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; 403 404// Load Upper Imediate 405class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 406 FI<op, (outs RC:$rt), (ins Imm:$imm16), 407 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { 408 let rs = 0; 409 let neverHasSideEffects = 1; 410 let isReMaterializable = 1; 411} 412 413class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 414 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 415 bits<21> addr; 416 let Inst{25-21} = addr{20-16}; 417 let Inst{15-0} = addr{15-0}; 418 let DecoderMethod = "DecodeMem"; 419} 420 421// Memory Load/Store 422let canFoldAsLoad = 1 in 423class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 424 Operand MemOpnd, bit Pseudo>: 425 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 426 !strconcat(instr_asm, "\t$rt, $addr"), 427 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 428 let isPseudo = Pseudo; 429} 430 431class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 432 Operand MemOpnd, bit Pseudo>: 433 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 434 !strconcat(instr_asm, "\t$rt, $addr"), 435 [(OpNode RC:$rt, addr:$addr)], IIStore> { 436 let isPseudo = Pseudo; 437} 438 439// 32-bit load. 440multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 441 bit Pseudo = 0> { 442 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 443 Requires<[NotN64, HasStdEnc]>; 444 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 445 Requires<[IsN64, HasStdEnc]> { 446 let DecoderNamespace = "Mips64"; 447 let isCodeGenOnly = 1; 448 } 449} 450 451// 64-bit load. 452multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 453 bit Pseudo = 0> { 454 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 455 Requires<[NotN64, HasStdEnc]>; 456 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 457 Requires<[IsN64, HasStdEnc]> { 458 let DecoderNamespace = "Mips64"; 459 let isCodeGenOnly = 1; 460 } 461} 462 463// 32-bit store. 464multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 465 bit Pseudo = 0> { 466 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 467 Requires<[NotN64, HasStdEnc]>; 468 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 469 Requires<[IsN64, HasStdEnc]> { 470 let DecoderNamespace = "Mips64"; 471 let isCodeGenOnly = 1; 472 } 473} 474 475// 64-bit store. 476multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 477 bit Pseudo = 0> { 478 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 479 Requires<[NotN64, HasStdEnc]>; 480 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 481 Requires<[IsN64, HasStdEnc]> { 482 let DecoderNamespace = "Mips64"; 483 let isCodeGenOnly = 1; 484 } 485} 486 487// Load/Store Left/Right 488let canFoldAsLoad = 1 in 489class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 490 RegisterClass RC, Operand MemOpnd> : 491 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 492 !strconcat(instr_asm, "\t$rt, $addr"), 493 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 494 string Constraints = "$src = $rt"; 495} 496 497class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 498 RegisterClass RC, Operand MemOpnd>: 499 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 500 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 501 IIStore>; 502 503// 32-bit load left/right. 504multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 505 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 506 Requires<[NotN64, HasStdEnc]>; 507 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 508 Requires<[IsN64, HasStdEnc]> { 509 let DecoderNamespace = "Mips64"; 510 let isCodeGenOnly = 1; 511 } 512} 513 514// 64-bit load left/right. 515multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 516 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 517 Requires<[NotN64, HasStdEnc]>; 518 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 519 Requires<[IsN64, HasStdEnc]> { 520 let DecoderNamespace = "Mips64"; 521 let isCodeGenOnly = 1; 522 } 523} 524 525// 32-bit store left/right. 526multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 527 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 528 Requires<[NotN64, HasStdEnc]>; 529 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 530 Requires<[IsN64, HasStdEnc]> { 531 let DecoderNamespace = "Mips64"; 532 let isCodeGenOnly = 1; 533 } 534} 535 536// 64-bit store left/right. 537multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 538 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 539 Requires<[NotN64, HasStdEnc]>; 540 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 541 Requires<[IsN64, HasStdEnc]> { 542 let DecoderNamespace = "Mips64"; 543 let isCodeGenOnly = 1; 544 } 545} 546 547// Conditional Branch 548class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 549 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 550 !strconcat(opstr, "\t$rs, $rt, $offset"), 551 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 552 FrmI> { 553 let isBranch = 1; 554 let isTerminator = 1; 555 let hasDelaySlot = 1; 556 let Defs = [AT]; 557} 558 559class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 560 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 561 !strconcat(opstr, "\t$rs, $offset"), 562 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 563 let isBranch = 1; 564 let isTerminator = 1; 565 let hasDelaySlot = 1; 566 let Defs = [AT]; 567} 568 569// SetCC 570class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 571 RegisterClass RC>: 572 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 573 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 574 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 575 IIAlu> { 576 let shamt = 0; 577} 578 579class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 580 PatLeaf imm_type, RegisterClass RC>: 581 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 582 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 583 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 584 IIAlu>; 585 586// Jump 587class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 588 SDPatternOperator operator, SDPatternOperator targetoperator>: 589 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 590 [(operator targetoperator:$target)], IIBranch> { 591 let isTerminator=1; 592 let isBarrier=1; 593 let hasDelaySlot = 1; 594 let DecoderMethod = "DecodeJumpTarget"; 595 let Defs = [AT]; 596} 597 598// Unconditional branch 599class UncondBranch<bits<6> op, string instr_asm>: 600 BranchBase<op, (outs), (ins brtarget:$imm16), 601 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 602 let rs = 0; 603 let rt = 0; 604 let isBranch = 1; 605 let isTerminator = 1; 606 let isBarrier = 1; 607 let hasDelaySlot = 1; 608 let Predicates = [RelocPIC, HasStdEnc]; 609 let Defs = [AT]; 610} 611 612// Base class for indirect branch and return instruction classes. 613let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 614class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 615 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 616 let rt = 0; 617 let rd = 0; 618 let shamt = 0; 619} 620 621// Indirect branch 622class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 623 let isBranch = 1; 624 let isIndirectBranch = 1; 625} 626 627// Return instruction 628class RetBase<RegisterClass RC>: JumpFR<RC> { 629 let isReturn = 1; 630 let isCodeGenOnly = 1; 631 let hasCtrlDep = 1; 632 let hasExtraSrcRegAllocReq = 1; 633} 634 635// Jump and Link (Call) 636let isCall=1, hasDelaySlot=1, Defs = [RA] in { 637 class JumpLink<bits<6> op, string instr_asm>: 638 FJ<op, (outs), (ins calltarget:$target), 639 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 640 IIBranch> { 641 let DecoderMethod = "DecodeJumpTarget"; 642 } 643 644 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 645 RegisterClass RC>: 646 FR<op, func, (outs), (ins RC:$rs), 647 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 648 let rt = 0; 649 let rd = 31; 650 let shamt = 0; 651 } 652 653 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 654 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 655 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 656 let rt = _rt; 657 } 658} 659 660// Mul, Div 661class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 662 RegisterClass RC, list<Register> DefRegs>: 663 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 664 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 665 let rd = 0; 666 let shamt = 0; 667 let isCommutable = 1; 668 let Defs = DefRegs; 669 let neverHasSideEffects = 1; 670} 671 672class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 673 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 674 675class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 676 RegisterClass RC, list<Register> DefRegs>: 677 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 678 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 679 [(op RC:$rs, RC:$rt)], itin> { 680 let rd = 0; 681 let shamt = 0; 682 let Defs = DefRegs; 683} 684 685class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 686 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 687 688// Move from Hi/Lo 689class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 690 list<Register> UseRegs>: 691 FR<0x00, func, (outs RC:$rd), (ins), 692 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 693 let rs = 0; 694 let rt = 0; 695 let shamt = 0; 696 let Uses = UseRegs; 697 let neverHasSideEffects = 1; 698} 699 700class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 701 list<Register> DefRegs>: 702 FR<0x00, func, (outs), (ins RC:$rs), 703 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 704 let rt = 0; 705 let rd = 0; 706 let shamt = 0; 707 let Defs = DefRegs; 708 let neverHasSideEffects = 1; 709} 710 711class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 712 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 713 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 714 let isCodeGenOnly = 1; 715} 716 717// Count Leading Ones/Zeros in Word 718class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 719 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 720 !strconcat(instr_asm, "\t$rd, $rs"), 721 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 722 Requires<[HasBitCount, HasStdEnc]> { 723 let shamt = 0; 724 let rt = rd; 725} 726 727class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 728 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 729 !strconcat(instr_asm, "\t$rd, $rs"), 730 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 731 Requires<[HasBitCount, HasStdEnc]> { 732 let shamt = 0; 733 let rt = rd; 734} 735 736// Sign Extend in Register. 737class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 738 RegisterClass RC>: 739 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 740 !strconcat(instr_asm, "\t$rd, $rt"), 741 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 742 let rs = 0; 743 let shamt = sa; 744 let Predicates = [HasSEInReg, HasStdEnc]; 745} 746 747// Subword Swap 748class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 749 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 750 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 751 let rs = 0; 752 let shamt = sa; 753 let Predicates = [HasSwap, HasStdEnc]; 754 let neverHasSideEffects = 1; 755} 756 757// Read Hardware 758class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 759 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 760 "rdhwr\t$rt, $rd", [], IIAlu> { 761 let rs = 0; 762 let shamt = 0; 763} 764 765// Ext and Ins 766class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 767 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 768 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 769 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 770 bits<5> pos; 771 bits<5> sz; 772 let rd = sz; 773 let shamt = pos; 774 let Predicates = [HasMips32r2, HasStdEnc]; 775} 776 777class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 778 FR<0x1f, _funct, (outs RC:$rt), 779 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 780 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 781 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 782 NoItinerary> { 783 bits<5> pos; 784 bits<5> sz; 785 let rd = sz; 786 let shamt = pos; 787 let Predicates = [HasMips32r2, HasStdEnc]; 788 let Constraints = "$src = $rt"; 789} 790 791// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 792class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 793 RegisterClass PRC> : 794 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 795 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 796 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 797 798multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 799 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 800 Requires<[NotN64, HasStdEnc]>; 801 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 802 Requires<[IsN64, HasStdEnc]> { 803 let DecoderNamespace = "Mips64"; 804 } 805} 806 807// Atomic Compare & Swap. 808class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 809 RegisterClass PRC> : 810 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 811 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 812 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 813 814multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 815 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 816 Requires<[NotN64, HasStdEnc]>; 817 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 818 Requires<[IsN64, HasStdEnc]> { 819 let DecoderNamespace = "Mips64"; 820 } 821} 822 823class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 824 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 825 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 826 let mayLoad = 1; 827} 828 829class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 830 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 831 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 832 let mayStore = 1; 833 let Constraints = "$rt = $dst"; 834} 835 836//===----------------------------------------------------------------------===// 837// Pseudo instructions 838//===----------------------------------------------------------------------===// 839 840// Return RA. 841let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 842def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 843 844let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 845def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 846 "!ADJCALLSTACKDOWN $amt", 847 [(callseq_start timm:$amt)]>; 848def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 849 "!ADJCALLSTACKUP $amt1", 850 [(callseq_end timm:$amt1, timm:$amt2)]>; 851} 852 853// When handling PIC code the assembler needs .cpload and .cprestore 854// directives. If the real instructions corresponding these directives 855// are used, we have the same behavior, but get also a bunch of warnings 856// from the assembler. 857let neverHasSideEffects = 1 in 858def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 859 ".cprestore\t$loc", []>; 860 861let usesCustomInserter = 1 in { 862 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 863 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 864 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 865 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 866 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 867 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 868 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 869 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 870 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 871 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 872 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 873 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 874 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 875 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 876 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 877 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 878 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 879 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 880 881 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 882 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 883 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 884 885 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 886 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 887 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 888} 889 890//===----------------------------------------------------------------------===// 891// Instruction definition 892//===----------------------------------------------------------------------===// 893 894class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 895 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 896 !strconcat(instr_asm, "\t$rt, $imm32")> ; 897def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 898 899class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 900 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 901 !strconcat(instr_asm, "\t$rt, $addr")> ; 902def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 903 904class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 905 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 906 !strconcat(instr_asm, "\t$rt, $imm32")> ; 907def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 908 909//===----------------------------------------------------------------------===// 910// MipsI Instructions 911//===----------------------------------------------------------------------===// 912 913/// Arithmetic Instructions (ALU Immediate) 914def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, 915 ADDI_FM<0x9>, IsAsCheapAsAMove; 916def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; 917def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 918def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 919def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; 920def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; 921def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; 922def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 923 924/// Arithmetic Instructions (3-Operand, R-Type) 925def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; 926def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 927def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; 928def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; 929def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 930def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 931def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 932def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 933def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 934def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 935 936/// Shift Instructions 937def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>; 938def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>; 939def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>; 940def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>; 941def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>; 942def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>; 943 944// Rotate Instructions 945let Predicates = [HasMips32r2, HasStdEnc] in { 946 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>; 947 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>; 948} 949 950/// Load and Store Instructions 951/// aligned 952defm LB : LoadM32<0x20, "lb", sextloadi8>; 953defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 954defm LH : LoadM32<0x21, "lh", sextloadi16>; 955defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 956defm LW : LoadM32<0x23, "lw", load>; 957defm SB : StoreM32<0x28, "sb", truncstorei8>; 958defm SH : StoreM32<0x29, "sh", truncstorei16>; 959defm SW : StoreM32<0x2b, "sw", store>; 960 961/// load/store left/right 962defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 963defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 964defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 965defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 966 967let hasSideEffects = 1 in 968def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 969 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 970{ 971 bits<5> stype; 972 let Opcode = 0; 973 let Inst{25-11} = 0; 974 let Inst{10-6} = stype; 975 let Inst{5-0} = 15; 976} 977 978/// Load-linked, Store-conditional 979def LL : LLBase<0x30, "ll", CPURegs, mem>, 980 Requires<[NotN64, HasStdEnc]>; 981def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 982 Requires<[IsN64, HasStdEnc]> { 983 let DecoderNamespace = "Mips64"; 984} 985 986def SC : SCBase<0x38, "sc", CPURegs, mem>, 987 Requires<[NotN64, HasStdEnc]>; 988def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 989 Requires<[IsN64, HasStdEnc]> { 990 let DecoderNamespace = "Mips64"; 991} 992 993/// Jump and Branch Instructions 994def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 995 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 996def JR : IndirectBranch<CPURegs>; 997def B : UncondBranch<0x04, "b">; 998def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 999def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 1000def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 1001def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 1002def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 1003def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 1004 1005let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 1006 hasDelaySlot = 1, Defs = [RA] in 1007def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 1008 1009def JAL : JumpLink<0x03, "jal">; 1010def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 1011def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 1012def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 1013def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 1014def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 1015 1016def RET : RetBase<CPURegs>; 1017 1018/// Multiply and Divide Instructions. 1019def MULT : Mult32<0x18, "mult", IIImul>; 1020def MULTu : Mult32<0x19, "multu", IIImul>; 1021def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 1022def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 1023 1024def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1025def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1026def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1027def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1028 1029/// Sign Ext In Register Instructions. 1030def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1031def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1032 1033/// Count Leading 1034def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1035def CLO : CountLeading1<0x21, "clo", CPURegs>; 1036 1037/// Word Swap Bytes Within Halfwords 1038def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1039 1040/// No operation 1041let addr=0 in 1042 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1043 1044// FrameIndexes are legalized when they are operands from load/store 1045// instructions. The same not happens for stack address copies, so an 1046// add op with mem ComplexPattern is used and the stack address copy 1047// can be matched. It's similar to Sparc LEA_ADDRi 1048def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1049 1050// MADD*/MSUB* 1051def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1052def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1053def MSUB : MArithR<4, "msub", MipsMSub>; 1054def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1055 1056// MUL is a assembly macro in the current used ISAs. In recent ISA's 1057// it is a real instruction. 1058def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 0x02>; 1059 1060def RDHWR : ReadHardware<CPURegs, HWRegs>; 1061 1062def EXT : ExtBase<0, "ext", CPURegs>; 1063def INS : InsBase<4, "ins", CPURegs>; 1064 1065//===----------------------------------------------------------------------===// 1066// Instruction aliases 1067//===----------------------------------------------------------------------===// 1068def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1069def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1070def : InstAlias<"addu $rs,$rt,$imm", 1071 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1072def : InstAlias<"add $rs,$rt,$imm", 1073 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1074def : InstAlias<"and $rs,$rt,$imm", 1075 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1076def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1077def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1078def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1079def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1080def : InstAlias<"slt $rs,$rt,$imm", 1081 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1082def : InstAlias<"xor $rs,$rt,$imm", 1083 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1084 1085//===----------------------------------------------------------------------===// 1086// Arbitrary patterns that map to one or more instructions 1087//===----------------------------------------------------------------------===// 1088 1089// Small immediates 1090def : MipsPat<(i32 immSExt16:$in), 1091 (ADDiu ZERO, imm:$in)>; 1092def : MipsPat<(i32 immZExt16:$in), 1093 (ORi ZERO, imm:$in)>; 1094def : MipsPat<(i32 immLow16Zero:$in), 1095 (LUi (HI16 imm:$in))>; 1096 1097// Arbitrary immediates 1098def : MipsPat<(i32 imm:$imm), 1099 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1100 1101// Carry MipsPatterns 1102def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1103 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1104def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1105 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1106def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1107 (ADDiu CPURegs:$src, imm:$imm)>; 1108 1109// Call 1110def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1111 (JAL tglobaladdr:$dst)>; 1112def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1113 (JAL texternalsym:$dst)>; 1114//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1115// (JALR CPURegs:$dst)>; 1116 1117// Tail call 1118def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1119 (TAILCALL tglobaladdr:$dst)>; 1120def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1121 (TAILCALL texternalsym:$dst)>; 1122// hi/lo relocs 1123def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1124def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1125def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1126def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1127def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1128def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1129 1130def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1131def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1132def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1133def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1134def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1135def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1136 1137def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1138 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1139def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1140 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1141def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1142 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1143def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1144 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1145def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1146 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1147 1148// gp_rel relocs 1149def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1150 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1151def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1152 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1153 1154// wrapper_pic 1155class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1156 MipsPat<(MipsWrapper RC:$gp, node:$in), 1157 (ADDiuOp RC:$gp, node:$in)>; 1158 1159def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1160def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1161def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1162def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1163def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1164def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1165 1166// Mips does not have "not", so we expand our way 1167def : MipsPat<(not CPURegs:$in), 1168 (NOR CPURegs:$in, ZERO)>; 1169 1170// extended loads 1171let Predicates = [NotN64, HasStdEnc] in { 1172 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1173 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1174 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1175} 1176let Predicates = [IsN64, HasStdEnc] in { 1177 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1178 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1179 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1180} 1181 1182// peepholes 1183let Predicates = [NotN64, HasStdEnc] in { 1184 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1185} 1186let Predicates = [IsN64, HasStdEnc] in { 1187 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1188} 1189 1190// brcond patterns 1191multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1192 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1193 Instruction SLTiuOp, Register ZEROReg> { 1194def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1195 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1196def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1197 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1198 1199def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1200 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1201def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1202 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1203def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1204 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1205def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1206 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1207 1208def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1209 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1210def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1211 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1212 1213def : MipsPat<(brcond RC:$cond, bb:$dst), 1214 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1215} 1216 1217defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1218 1219// setcc patterns 1220multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1221 Instruction SLTuOp, Register ZEROReg> { 1222 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1223 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1224 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1225 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1226} 1227 1228multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1229 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1230 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1231 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1232 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1233} 1234 1235multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1236 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1237 (SLTOp RC:$rhs, RC:$lhs)>; 1238 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1239 (SLTuOp RC:$rhs, RC:$lhs)>; 1240} 1241 1242multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1243 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1244 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1245 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1246 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1247} 1248 1249multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1250 Instruction SLTiuOp> { 1251 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1252 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1253 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1254 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1255} 1256 1257defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1258defm : SetlePats<CPURegs, SLT, SLTu>; 1259defm : SetgtPats<CPURegs, SLT, SLTu>; 1260defm : SetgePats<CPURegs, SLT, SLTu>; 1261defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1262 1263// bswap pattern 1264def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1265 1266//===----------------------------------------------------------------------===// 1267// Floating Point Support 1268//===----------------------------------------------------------------------===// 1269 1270include "MipsInstrFPU.td" 1271include "Mips64InstrInfo.td" 1272include "MipsCondMov.td" 1273 1274// 1275// Mips16 1276 1277include "Mips16InstrFormats.td" 1278include "Mips16InstrInfo.td" 1279 1280// DSP 1281include "MipsDSPInstrFormats.td" 1282include "MipsDSPInstrInfo.td" 1283 1284