MipsInstrInfo.td revision 603f69dc2c69ac3f4040e125febd3925dec2bcb2
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, 37 SDTCisSameAs<0, 1>]>; 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Hi and Lo nodes are used to handle global addresses. Used on 56// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 57// static model. (nothing to do with Mips Registers Hi and Lo) 58def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 59def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 60def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 61 62// TlsGd node is used to handle General Dynamic TLS 63def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 64 65// TprelHi and TprelLo nodes are used to handle Local Exec TLS 66def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 67def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 68 69// Thread pointer 70def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 71 72// Return 73def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 74 75// These are target-independent nodes, but have target-specific formats. 76def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 77 [SDNPHasChain, SDNPOutGlue]>; 78def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 80 81// MAdd*/MSub* nodes 82def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 83 [SDNPOptInGlue, SDNPOutGlue]>; 84def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 85 [SDNPOptInGlue, SDNPOutGlue]>; 86def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 87 [SDNPOptInGlue, SDNPOutGlue]>; 88def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 89 [SDNPOptInGlue, SDNPOutGlue]>; 90 91// DivRem(u) nodes 92def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 93 [SDNPOutGlue]>; 94def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 95 [SDNPOutGlue]>; 96 97// Target constant nodes that are not part of any isel patterns and remain 98// unchanged can cause instructions with illegal operands to be emitted. 99// Wrapper node patterns give the instruction selector a chance to replace 100// target constant nodes that would otherwise remain unchanged with ADDiu 101// nodes. Without these wrapper node patterns, the following conditional move 102// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 103// compiled: 104// movn %got(d)($gp), %got(c)($gp), $4 105// This instruction is illegal since movn can take only register operands. 106 107def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 108 109// Pointer to dynamically allocated stack area. 110def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, 111 [SDNPHasChain, SDNPInGlue]>; 112 113def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>; 114 115def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 116def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 117 118def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 120def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 122def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 124def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 126def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 128def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 132def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134 135//===----------------------------------------------------------------------===// 136// Mips Instruction Predicate Definitions. 137//===----------------------------------------------------------------------===// 138def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 139 AssemblerPredicate<"FeatureSEInReg">; 140def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 141 AssemblerPredicate<"FeatureBitCount">; 142def HasSwap : Predicate<"Subtarget.hasSwap()">, 143 AssemblerPredicate<"FeatureSwap">; 144def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 145 AssemblerPredicate<"FeatureCondMov">; 146def HasMips32 : Predicate<"Subtarget.hasMips32()">, 147 AssemblerPredicate<"FeatureMips32">; 148def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 149 AssemblerPredicate<"FeatureMips32r2">; 150def HasMips64 : Predicate<"Subtarget.hasMips64()">, 151 AssemblerPredicate<"FeatureMips64">; 152def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">, 153 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">; 154def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 155 AssemblerPredicate<"!FeatureMips64">; 156def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 157 AssemblerPredicate<"FeatureMips64r2">; 158def IsN64 : Predicate<"Subtarget.isABI_N64()">, 159 AssemblerPredicate<"FeatureN64">; 160def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 161 AssemblerPredicate<"!FeatureN64">; 162def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 163 AssemblerPredicate<"FeatureMips16">; 164def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 165 AssemblerPredicate<"FeatureMips32">; 166def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 167 AssemblerPredicate<"FeatureMips32">; 168def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 169 AssemblerPredicate<"FeatureMips32">; 170def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">, 171 AssemblerPredicate<"!FeatureMips16">; 172 173class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 174 let Predicates = [HasStandardEncoding]; 175} 176 177//===----------------------------------------------------------------------===// 178// Instruction format superclass 179//===----------------------------------------------------------------------===// 180 181include "MipsInstrFormats.td" 182 183//===----------------------------------------------------------------------===// 184// Mips Operand, Complex Patterns and Transformations Definitions. 185//===----------------------------------------------------------------------===// 186 187// Instruction operand types 188def jmptarget : Operand<OtherVT> { 189 let EncoderMethod = "getJumpTargetOpValue"; 190} 191def brtarget : Operand<OtherVT> { 192 let EncoderMethod = "getBranchTargetOpValue"; 193 let OperandType = "OPERAND_PCREL"; 194 let DecoderMethod = "DecodeBranchTarget"; 195} 196def calltarget : Operand<iPTR> { 197 let EncoderMethod = "getJumpTargetOpValue"; 198} 199def calltarget64: Operand<i64>; 200def simm16 : Operand<i32> { 201 let DecoderMethod= "DecodeSimm16"; 202} 203def simm16_64 : Operand<i64>; 204def shamt : Operand<i32>; 205 206// Unsigned Operand 207def uimm16 : Operand<i32> { 208 let PrintMethod = "printUnsignedImm"; 209} 210 211// Address operand 212def mem : Operand<i32> { 213 let PrintMethod = "printMemOperand"; 214 let MIOperandInfo = (ops CPURegs, simm16); 215 let EncoderMethod = "getMemEncoding"; 216} 217 218def mem64 : Operand<i64> { 219 let PrintMethod = "printMemOperand"; 220 let MIOperandInfo = (ops CPU64Regs, simm16_64); 221 let EncoderMethod = "getMemEncoding"; 222} 223 224def mem_ea : Operand<i32> { 225 let PrintMethod = "printMemOperandEA"; 226 let MIOperandInfo = (ops CPURegs, simm16); 227 let EncoderMethod = "getMemEncoding"; 228} 229 230def mem_ea_64 : Operand<i64> { 231 let PrintMethod = "printMemOperandEA"; 232 let MIOperandInfo = (ops CPU64Regs, simm16_64); 233 let EncoderMethod = "getMemEncoding"; 234} 235 236// size operand of ext instruction 237def size_ext : Operand<i32> { 238 let EncoderMethod = "getSizeExtEncoding"; 239 let DecoderMethod = "DecodeExtSize"; 240} 241 242// size operand of ins instruction 243def size_ins : Operand<i32> { 244 let EncoderMethod = "getSizeInsEncoding"; 245 let DecoderMethod = "DecodeInsSize"; 246} 247 248// Transformation Function - get the lower 16 bits. 249def LO16 : SDNodeXForm<imm, [{ 250 return getImm(N, N->getZExtValue() & 0xFFFF); 251}]>; 252 253// Transformation Function - get the higher 16 bits. 254def HI16 : SDNodeXForm<imm, [{ 255 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 256}]>; 257 258// Node immediate fits as 16-bit sign extended on target immediate. 259// e.g. addi, andi 260def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 261 262// Node immediate fits as 16-bit zero extended on target immediate. 263// The LO16 param means that only the lower 16 bits of the node 264// immediate are caught. 265// e.g. addiu, sltiu 266def immZExt16 : PatLeaf<(imm), [{ 267 if (N->getValueType(0) == MVT::i32) 268 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 269 else 270 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 271}], LO16>; 272 273// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 274def immLow16Zero : PatLeaf<(imm), [{ 275 int64_t Val = N->getSExtValue(); 276 return isInt<32>(Val) && !(Val & 0xffff); 277}]>; 278 279// shamt field must fit in 5 bits. 280def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 281 282// Mips Address Mode! SDNode frameindex could possibily be a match 283// since load and store instructions from stack used it. 284def addr : 285 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 286 287//===----------------------------------------------------------------------===// 288// Pattern fragment for load/store 289//===----------------------------------------------------------------------===// 290class UnalignedLoad<PatFrag Node> : 291 PatFrag<(ops node:$ptr), (Node node:$ptr), [{ 292 LoadSDNode *LD = cast<LoadSDNode>(N); 293 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment(); 294}]>; 295 296class AlignedLoad<PatFrag Node> : 297 PatFrag<(ops node:$ptr), (Node node:$ptr), [{ 298 LoadSDNode *LD = cast<LoadSDNode>(N); 299 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment(); 300}]>; 301 302class UnalignedStore<PatFrag Node> : 303 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{ 304 StoreSDNode *SD = cast<StoreSDNode>(N); 305 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment(); 306}]>; 307 308class AlignedStore<PatFrag Node> : 309 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{ 310 StoreSDNode *SD = cast<StoreSDNode>(N); 311 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment(); 312}]>; 313 314// Load/Store PatFrags. 315def sextloadi16_a : AlignedLoad<sextloadi16>; 316def zextloadi16_a : AlignedLoad<zextloadi16>; 317def extloadi16_a : AlignedLoad<extloadi16>; 318def load_a : AlignedLoad<load>; 319def sextloadi32_a : AlignedLoad<sextloadi32>; 320def zextloadi32_a : AlignedLoad<zextloadi32>; 321def extloadi32_a : AlignedLoad<extloadi32>; 322def truncstorei16_a : AlignedStore<truncstorei16>; 323def store_a : AlignedStore<store>; 324def truncstorei32_a : AlignedStore<truncstorei32>; 325def sextloadi16_u : UnalignedLoad<sextloadi16>; 326def zextloadi16_u : UnalignedLoad<zextloadi16>; 327def extloadi16_u : UnalignedLoad<extloadi16>; 328def load_u : UnalignedLoad<load>; 329def sextloadi32_u : UnalignedLoad<sextloadi32>; 330def zextloadi32_u : UnalignedLoad<zextloadi32>; 331def extloadi32_u : UnalignedLoad<extloadi32>; 332def truncstorei16_u : UnalignedStore<truncstorei16>; 333def store_u : UnalignedStore<store>; 334def truncstorei32_u : UnalignedStore<truncstorei32>; 335 336//===----------------------------------------------------------------------===// 337// Instructions specific format 338//===----------------------------------------------------------------------===// 339 340// Arithmetic and logical instructions with 3 register operands. 341class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, 342 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 343 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 344 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 345 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> { 346 let shamt = 0; 347 let isCommutable = isComm; 348 let isReMaterializable = 1; 349} 350 351class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm, 352 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 353 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 354 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> { 355 let shamt = 0; 356 let isCommutable = isComm; 357} 358 359// Arithmetic and logical instructions with 2 register operands. 360class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode, 361 Operand Od, PatLeaf imm_type, RegisterClass RC> : 362 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 363 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 364 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> { 365 let isReMaterializable = 1; 366} 367 368class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode, 369 Operand Od, PatLeaf imm_type, RegisterClass RC> : 370 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 371 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>; 372 373// Arithmetic Multiply ADD/SUB 374let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 375class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 376 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 377 !strconcat(instr_asm, "\t$rs, $rt"), 378 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 379 let rd = 0; 380 let shamt = 0; 381 let isCommutable = isComm; 382} 383 384// Logical 385class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 386 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 387 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 388 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 389 let shamt = 0; 390 let isCommutable = 1; 391} 392 393// Shifts 394class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm, 395 SDNode OpNode, PatFrag PF, Operand ImmOpnd, 396 RegisterClass RC>: 397 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 398 !strconcat(instr_asm, "\t$rd, $rt, $shamt"), 399 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> { 400 let rs = isRotate; 401} 402 403// 32-bit shift instructions. 404class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm, 405 SDNode OpNode>: 406 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>; 407 408class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, 409 SDNode OpNode, RegisterClass RC>: 410 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 411 !strconcat(instr_asm, "\t$rd, $rt, $rs"), 412 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { 413 let shamt = isRotate; 414} 415 416// Load Upper Imediate 417class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 418 FI<op, (outs RC:$rt), (ins Imm:$imm16), 419 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> { 420 let rs = 0; 421 let neverHasSideEffects = 1; 422 let isReMaterializable = 1; 423} 424 425class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 426 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 427 bits<21> addr; 428 let Inst{25-21} = addr{20-16}; 429 let Inst{15-0} = addr{15-0}; 430 let DecoderMethod = "DecodeMem"; 431} 432 433// Memory Load/Store 434let canFoldAsLoad = 1 in 435class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 436 Operand MemOpnd, bit Pseudo>: 437 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 438 !strconcat(instr_asm, "\t$rt, $addr"), 439 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 440 let isPseudo = Pseudo; 441} 442 443class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 444 Operand MemOpnd, bit Pseudo>: 445 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 446 !strconcat(instr_asm, "\t$rt, $addr"), 447 [(OpNode RC:$rt, addr:$addr)], IIStore> { 448 let isPseudo = Pseudo; 449} 450 451// 32-bit load. 452multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 453 bit Pseudo = 0> { 454 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 455 Requires<[NotN64, HasStandardEncoding]>; 456 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 457 Requires<[IsN64, HasStandardEncoding]> { 458 let DecoderNamespace = "Mips64"; 459 let isCodeGenOnly = 1; 460 } 461} 462 463// 64-bit load. 464multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 465 bit Pseudo = 0> { 466 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 467 Requires<[NotN64, HasStandardEncoding]>; 468 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 469 Requires<[IsN64, HasStandardEncoding]> { 470 let DecoderNamespace = "Mips64"; 471 let isCodeGenOnly = 1; 472 } 473} 474 475// 32-bit store. 476multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 477 bit Pseudo = 0> { 478 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 479 Requires<[NotN64, HasStandardEncoding]>; 480 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 481 Requires<[IsN64, HasStandardEncoding]> { 482 let DecoderNamespace = "Mips64"; 483 let isCodeGenOnly = 1; 484 } 485} 486 487// 64-bit store. 488multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 489 bit Pseudo = 0> { 490 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 491 Requires<[NotN64, HasStandardEncoding]>; 492 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 493 Requires<[IsN64, HasStandardEncoding]> { 494 let DecoderNamespace = "Mips64"; 495 let isCodeGenOnly = 1; 496 } 497} 498 499// Load/Store Left/Right 500let canFoldAsLoad = 1 in 501class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 502 RegisterClass RC, Operand MemOpnd> : 503 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 504 !strconcat(instr_asm, "\t$rt, $addr"), 505 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 506 string Constraints = "$src = $rt"; 507} 508 509class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 510 RegisterClass RC, Operand MemOpnd>: 511 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 512 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 513 IIStore>; 514 515// 32-bit load left/right. 516multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 517 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 518 Requires<[NotN64, HasStandardEncoding]>; 519 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 520 Requires<[IsN64, HasStandardEncoding]> { 521 let DecoderNamespace = "Mips64"; 522 let isCodeGenOnly = 1; 523 } 524} 525 526// 64-bit load left/right. 527multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 528 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 529 Requires<[NotN64, HasStandardEncoding]>; 530 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 531 Requires<[IsN64, HasStandardEncoding]> { 532 let DecoderNamespace = "Mips64"; 533 let isCodeGenOnly = 1; 534 } 535} 536 537// 32-bit store left/right. 538multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 539 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 540 Requires<[NotN64, HasStandardEncoding]>; 541 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 542 Requires<[IsN64, HasStandardEncoding]> { 543 let DecoderNamespace = "Mips64"; 544 let isCodeGenOnly = 1; 545 } 546} 547 548// 64-bit store left/right. 549multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 550 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 551 Requires<[NotN64, HasStandardEncoding]>; 552 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 553 Requires<[IsN64, HasStandardEncoding]> { 554 let DecoderNamespace = "Mips64"; 555 let isCodeGenOnly = 1; 556 } 557} 558 559// Conditional Branch 560class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>: 561 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 562 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 563 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { 564 let isBranch = 1; 565 let isTerminator = 1; 566 let hasDelaySlot = 1; 567 let Defs = [AT]; 568} 569 570class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op, 571 RegisterClass RC>: 572 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16), 573 !strconcat(instr_asm, "\t$rs, $imm16"), 574 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { 575 let rt = _rt; 576 let isBranch = 1; 577 let isTerminator = 1; 578 let hasDelaySlot = 1; 579 let Defs = [AT]; 580} 581 582// SetCC 583class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 584 RegisterClass RC>: 585 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 586 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 587 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 588 IIAlu> { 589 let shamt = 0; 590} 591 592class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 593 PatLeaf imm_type, RegisterClass RC>: 594 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 595 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 596 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 597 IIAlu>; 598 599// Jump 600class JumpFJ<bits<6> op, string instr_asm>: 601 FJ<op, (outs), (ins jmptarget:$target), 602 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> { 603 let isBranch=1; 604 let isTerminator=1; 605 let isBarrier=1; 606 let hasDelaySlot = 1; 607 let Predicates = [RelocStatic, HasStandardEncoding]; 608 let DecoderMethod = "DecodeJumpTarget"; 609 let Defs = [AT]; 610} 611 612// Unconditional branch 613class UncondBranch<bits<6> op, string instr_asm>: 614 BranchBase<op, (outs), (ins brtarget:$imm16), 615 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 616 let rs = 0; 617 let rt = 0; 618 let isBranch = 1; 619 let isTerminator = 1; 620 let isBarrier = 1; 621 let hasDelaySlot = 1; 622 let Predicates = [RelocPIC, HasStandardEncoding]; 623 let Defs = [AT]; 624} 625 626// Base class for indirect branch and return instruction classes. 627let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 628class JumpFR<RegisterClass RC, list<dag> pattern>: 629 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", pattern, IIBranch> { 630 let rt = 0; 631 let rd = 0; 632 let shamt = 0; 633} 634 635// Indirect branch 636class IndirectBranch<RegisterClass RC>: JumpFR<RC, [(brind RC:$rs)]> { 637 let isBranch = 1; 638 let isIndirectBranch = 1; 639} 640 641// Return instruction 642class RetBase<RegisterClass RC>: JumpFR<RC, []> { 643 let isReturn = 1; 644 let isCodeGenOnly = 1; 645 let hasCtrlDep = 1; 646 let hasExtraSrcRegAllocReq = 1; 647} 648 649// Jump and Link (Call) 650let isCall=1, hasDelaySlot=1, Defs = [RA] in { 651 class JumpLink<bits<6> op, string instr_asm>: 652 FJ<op, (outs), (ins calltarget:$target), 653 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 654 IIBranch> { 655 let DecoderMethod = "DecodeJumpTarget"; 656 } 657 658 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 659 RegisterClass RC>: 660 FR<op, func, (outs), (ins RC:$rs), 661 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 662 let rt = 0; 663 let rd = 31; 664 let shamt = 0; 665 } 666 667 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 668 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 669 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 670 let rt = _rt; 671 } 672} 673 674// Mul, Div 675class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 676 RegisterClass RC, list<Register> DefRegs>: 677 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 678 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 679 let rd = 0; 680 let shamt = 0; 681 let isCommutable = 1; 682 let Defs = DefRegs; 683 let neverHasSideEffects = 1; 684} 685 686class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 687 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 688 689class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 690 RegisterClass RC, list<Register> DefRegs>: 691 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 692 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 693 [(op RC:$rs, RC:$rt)], itin> { 694 let rd = 0; 695 let shamt = 0; 696 let Defs = DefRegs; 697} 698 699class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 700 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 701 702// Move from Hi/Lo 703class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 704 list<Register> UseRegs>: 705 FR<0x00, func, (outs RC:$rd), (ins), 706 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 707 let rs = 0; 708 let rt = 0; 709 let shamt = 0; 710 let Uses = UseRegs; 711 let neverHasSideEffects = 1; 712} 713 714class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 715 list<Register> DefRegs>: 716 FR<0x00, func, (outs), (ins RC:$rs), 717 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 718 let rt = 0; 719 let rd = 0; 720 let shamt = 0; 721 let Defs = DefRegs; 722 let neverHasSideEffects = 1; 723} 724 725class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> : 726 FMem<0x09, (outs RC:$rt), (ins Mem:$addr), 727 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>; 728 729// Count Leading Ones/Zeros in Word 730class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 731 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 732 !strconcat(instr_asm, "\t$rd, $rs"), 733 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 734 Requires<[HasBitCount, HasStandardEncoding]> { 735 let shamt = 0; 736 let rt = rd; 737} 738 739class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 740 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 741 !strconcat(instr_asm, "\t$rd, $rs"), 742 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 743 Requires<[HasBitCount, HasStandardEncoding]> { 744 let shamt = 0; 745 let rt = rd; 746} 747 748// Sign Extend in Register. 749class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 750 RegisterClass RC>: 751 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 752 !strconcat(instr_asm, "\t$rd, $rt"), 753 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 754 let rs = 0; 755 let shamt = sa; 756 let Predicates = [HasSEInReg, HasStandardEncoding]; 757} 758 759// Subword Swap 760class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 761 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 762 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 763 let rs = 0; 764 let shamt = sa; 765 let Predicates = [HasSwap, HasStandardEncoding]; 766 let neverHasSideEffects = 1; 767} 768 769// Read Hardware 770class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 771 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 772 "rdhwr\t$rt, $rd", [], IIAlu> { 773 let rs = 0; 774 let shamt = 0; 775} 776 777// Ext and Ins 778class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 779 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 780 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 781 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 782 bits<5> pos; 783 bits<5> sz; 784 let rd = sz; 785 let shamt = pos; 786 let Predicates = [HasMips32r2, HasStandardEncoding]; 787} 788 789class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 790 FR<0x1f, _funct, (outs RC:$rt), 791 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 792 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 793 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 794 NoItinerary> { 795 bits<5> pos; 796 bits<5> sz; 797 let rd = sz; 798 let shamt = pos; 799 let Predicates = [HasMips32r2, HasStandardEncoding]; 800 let Constraints = "$src = $rt"; 801} 802 803// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 804class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 805 RegisterClass PRC> : 806 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 807 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 808 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 809 810multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 811 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 812 Requires<[NotN64, HasStandardEncoding]>; 813 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 814 Requires<[IsN64, HasStandardEncoding]> { 815 let DecoderNamespace = "Mips64"; 816 } 817} 818 819// Atomic Compare & Swap. 820class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 821 RegisterClass PRC> : 822 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 823 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 824 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 825 826multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 827 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 828 Requires<[NotN64, HasStandardEncoding]>; 829 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 830 Requires<[IsN64, HasStandardEncoding]> { 831 let DecoderNamespace = "Mips64"; 832 } 833} 834 835class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 836 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 837 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 838 let mayLoad = 1; 839} 840 841class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 842 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 843 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 844 let mayStore = 1; 845 let Constraints = "$rt = $dst"; 846} 847 848//===----------------------------------------------------------------------===// 849// Pseudo instructions 850//===----------------------------------------------------------------------===// 851 852// Return RA. 853let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 854def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 855 856let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 857def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 858 "!ADJCALLSTACKDOWN $amt", 859 [(callseq_start timm:$amt)]>; 860def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 861 "!ADJCALLSTACKUP $amt1", 862 [(callseq_end timm:$amt1, timm:$amt2)]>; 863} 864 865// When handling PIC code the assembler needs .cpload and .cprestore 866// directives. If the real instructions corresponding these directives 867// are used, we have the same behavior, but get also a bunch of warnings 868// from the assembler. 869let neverHasSideEffects = 1 in 870def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 871 ".cprestore\t$loc", []>; 872 873let usesCustomInserter = 1 in { 874 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 875 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 876 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 877 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 878 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 879 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 880 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 881 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 882 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 883 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 884 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 885 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 886 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 887 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 888 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 889 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 890 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 891 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 892 893 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 894 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 895 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 896 897 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 898 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 899 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 900} 901 902//===----------------------------------------------------------------------===// 903// Instruction definition 904//===----------------------------------------------------------------------===// 905 906//===----------------------------------------------------------------------===// 907// MipsI Instructions 908//===----------------------------------------------------------------------===// 909 910/// Arithmetic Instructions (ALU Immediate) 911def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>; 912def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; 913def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 914def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 915def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; 916def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; 917def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; 918def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 919 920/// Arithmetic Instructions (3-Operand, R-Type) 921def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; 922def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>; 923def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; 924def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>; 925def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 926def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 927def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; 928def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; 929def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; 930def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 931 932/// Shift Instructions 933def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; 934def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>; 935def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>; 936def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>; 937def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>; 938def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>; 939 940// Rotate Instructions 941let Predicates = [HasMips32r2, HasStandardEncoding] in { 942 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>; 943 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>; 944} 945 946/// Load and Store Instructions 947/// aligned 948defm LB : LoadM32<0x20, "lb", sextloadi8>; 949defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 950defm LH : LoadM32<0x21, "lh", sextloadi16_a>; 951defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>; 952defm LW : LoadM32<0x23, "lw", load_a>; 953defm SB : StoreM32<0x28, "sb", truncstorei8>; 954defm SH : StoreM32<0x29, "sh", truncstorei16_a>; 955defm SW : StoreM32<0x2b, "sw", store_a>; 956 957/// unaligned 958defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>; 959defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>; 960defm ULW : LoadM32<0x23, "ulw", load_u, 1>; 961defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>; 962defm USW : StoreM32<0x2b, "usw", store_u, 1>; 963 964/// load/store left/right 965defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 966defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 967defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 968defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 969 970let hasSideEffects = 1 in 971def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 972 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 973{ 974 bits<5> stype; 975 let Opcode = 0; 976 let Inst{25-11} = 0; 977 let Inst{10-6} = stype; 978 let Inst{5-0} = 15; 979} 980 981/// Load-linked, Store-conditional 982def LL : LLBase<0x30, "ll", CPURegs, mem>, 983 Requires<[NotN64, HasStandardEncoding]>; 984def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 985 Requires<[IsN64, HasStandardEncoding]> { 986 let DecoderNamespace = "Mips64"; 987} 988 989def SC : SCBase<0x38, "sc", CPURegs, mem>, 990 Requires<[NotN64, HasStandardEncoding]>; 991def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 992 Requires<[IsN64, HasStandardEncoding]> { 993 let DecoderNamespace = "Mips64"; 994} 995 996/// Jump and Branch Instructions 997def J : JumpFJ<0x02, "j">; 998def JR : IndirectBranch<CPURegs>; 999def B : UncondBranch<0x04, "b">; 1000def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; 1001def BNE : CBranch<0x05, "bne", setne, CPURegs>; 1002def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; 1003def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 1004def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; 1005def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; 1006 1007let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 1008 hasDelaySlot = 1, Defs = [RA] in 1009def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 1010 1011def JAL : JumpLink<0x03, "jal">; 1012def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 1013def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 1014def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 1015 1016def RET : RetBase<CPURegs>; 1017 1018/// Multiply and Divide Instructions. 1019def MULT : Mult32<0x18, "mult", IIImul>; 1020def MULTu : Mult32<0x19, "multu", IIImul>; 1021def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 1022def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 1023 1024def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1025def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1026def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1027def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1028 1029/// Sign Ext In Register Instructions. 1030def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1031def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1032 1033/// Count Leading 1034def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1035def CLO : CountLeading1<0x21, "clo", CPURegs>; 1036 1037/// Word Swap Bytes Within Halfwords 1038def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1039 1040/// No operation 1041let addr=0 in 1042 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1043 1044// FrameIndexes are legalized when they are operands from load/store 1045// instructions. The same not happens for stack address copies, so an 1046// add op with mem ComplexPattern is used and the stack address copy 1047// can be matched. It's similar to Sparc LEA_ADDRi 1048def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> { 1049 let isCodeGenOnly = 1; 1050} 1051 1052// DynAlloc node points to dynamically allocated stack space. 1053// $sp is added to the list of implicitly used registers to prevent dead code 1054// elimination from removing instructions that modify $sp. 1055let Uses = [SP] in 1056def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> { 1057 let isCodeGenOnly = 1; 1058} 1059 1060// MADD*/MSUB* 1061def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1062def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1063def MSUB : MArithR<4, "msub", MipsMSub>; 1064def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1065 1066// MUL is a assembly macro in the current used ISAs. In recent ISA's 1067// it is a real instruction. 1068def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, 1069 Requires<[HasMips32, HasStandardEncoding]>; 1070 1071def RDHWR : ReadHardware<CPURegs, HWRegs>; 1072 1073def EXT : ExtBase<0, "ext", CPURegs>; 1074def INS : InsBase<4, "ins", CPURegs>; 1075 1076//===----------------------------------------------------------------------===// 1077// Arbitrary patterns that map to one or more instructions 1078//===----------------------------------------------------------------------===// 1079 1080// Small immediates 1081def : MipsPat<(i32 immSExt16:$in), 1082 (ADDiu ZERO, imm:$in)>; 1083def : MipsPat<(i32 immZExt16:$in), 1084 (ORi ZERO, imm:$in)>; 1085def : MipsPat<(i32 immLow16Zero:$in), 1086 (LUi (HI16 imm:$in))>; 1087 1088// Arbitrary immediates 1089def : MipsPat<(i32 imm:$imm), 1090 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1091 1092// Carry MipsPatterns 1093def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1094 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1095def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1096 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1097def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1098 (ADDiu CPURegs:$src, imm:$imm)>; 1099 1100// Call 1101def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1102 (JAL tglobaladdr:$dst)>; 1103def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1104 (JAL texternalsym:$dst)>; 1105//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1106// (JALR CPURegs:$dst)>; 1107 1108// hi/lo relocs 1109def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1110def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1111def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1112def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1113def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1114 1115def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1116def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1117def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1118def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1119def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1120 1121def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1122 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1123def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1124 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1125def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1126 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1127def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1128 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1129def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1130 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1131 1132// gp_rel relocs 1133def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1134 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1135def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1136 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1137 1138// wrapper_pic 1139class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1140 MipsPat<(MipsWrapper RC:$gp, node:$in), 1141 (ADDiuOp RC:$gp, node:$in)>; 1142 1143def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1144def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1145def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1146def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1147def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1148def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1149 1150// Mips does not have "not", so we expand our way 1151def : MipsPat<(not CPURegs:$in), 1152 (NOR CPURegs:$in, ZERO)>; 1153 1154// extended loads 1155let Predicates = [NotN64, HasStandardEncoding] in { 1156 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1157 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1158 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>; 1159 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>; 1160} 1161let Predicates = [IsN64, HasStandardEncoding] in { 1162 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1163 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1164 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>; 1165 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>; 1166} 1167 1168// peepholes 1169let Predicates = [NotN64, HasStandardEncoding] in { 1170 def : MipsPat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1171 def : MipsPat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>; 1172} 1173let Predicates = [IsN64, HasStandardEncoding] in { 1174 def : MipsPat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1175 def : MipsPat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>; 1176} 1177 1178// brcond patterns 1179multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1180 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1181 Instruction SLTiuOp, Register ZEROReg> { 1182def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1183 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1184def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1185 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1186 1187def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1188 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1189def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1190 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1191def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1192 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1193def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1194 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1195 1196def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1197 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1198def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1199 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1200 1201def : MipsPat<(brcond RC:$cond, bb:$dst), 1202 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1203} 1204 1205defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1206 1207// setcc patterns 1208multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1209 Instruction SLTuOp, Register ZEROReg> { 1210 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1211 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1212 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1213 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1214} 1215 1216multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1217 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1218 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1219 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1220 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1221} 1222 1223multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1224 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1225 (SLTOp RC:$rhs, RC:$lhs)>; 1226 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1227 (SLTuOp RC:$rhs, RC:$lhs)>; 1228} 1229 1230multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1231 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1232 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1233 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1234 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1235} 1236 1237multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1238 Instruction SLTiuOp> { 1239 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1240 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1241 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1242 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1243} 1244 1245defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1246defm : SetlePats<CPURegs, SLT, SLTu>; 1247defm : SetgtPats<CPURegs, SLT, SLTu>; 1248defm : SetgePats<CPURegs, SLT, SLTu>; 1249defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1250 1251// select MipsDynAlloc 1252def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; 1253 1254// bswap pattern 1255def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1256 1257//===----------------------------------------------------------------------===// 1258// Floating Point Support 1259//===----------------------------------------------------------------------===// 1260 1261include "MipsInstrFPU.td" 1262include "Mips64InstrInfo.td" 1263include "MipsCondMov.td" 1264 1265// 1266// Mips16 1267 1268include "Mips16InstrFormats.td" 1269include "Mips16InstrInfo.td" 1270