MipsInstrInfo.td revision 6f297afb7ea6ab53be1feae4a335e7b1cb7a1f02
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 36def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 37 38def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 39 40def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 41 42def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 44def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 46 SDTCisSameAs<0, 4>]>; 47 48def SDTMipsLoadLR : SDTypeProfile<1, 2, 49 [SDTCisInt<0>, SDTCisPtrTy<1>, 50 SDTCisSameAs<0, 2>]>; 51 52// Call 53def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 55 SDNPVariadic]>; 56 57// Tail call 58def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 60 61// Hi and Lo nodes are used to handle global addresses. Used on 62// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 63// static model. (nothing to do with Mips Registers Hi and Lo) 64def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 65def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 66def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 67 68// TlsGd node is used to handle General Dynamic TLS 69def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 70 71// TprelHi and TprelLo nodes are used to handle Local Exec TLS 72def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 73def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 74 75// Thread pointer 76def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 77 78// Return 79def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 81 82// These are target-independent nodes, but have target-specific formats. 83def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 85def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 86 [SDNPHasChain, SDNPSideEffect, 87 SDNPOptInGlue, SDNPOutGlue]>; 88 89// Node used to extract integer from LO/HI register. 90def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, 186 AssemblerPredicate<"FeatureMicroMips">; 187def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, 188 AssemblerPredicate<"!FeatureMicroMips">; 189 190class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 191 let Predicates = [HasStdEnc]; 192} 193 194class IsCommutable { 195 bit isCommutable = 1; 196} 197 198class IsBranch { 199 bit isBranch = 1; 200} 201 202class IsReturn { 203 bit isReturn = 1; 204} 205 206class IsCall { 207 bit isCall = 1; 208} 209 210class IsTailCall { 211 bit isCall = 1; 212 bit isTerminator = 1; 213 bit isReturn = 1; 214 bit isBarrier = 1; 215 bit hasExtraSrcRegAllocReq = 1; 216 bit isCodeGenOnly = 1; 217} 218 219class IsAsCheapAsAMove { 220 bit isAsCheapAsAMove = 1; 221} 222 223class NeverHasSideEffects { 224 bit neverHasSideEffects = 1; 225} 226 227//===----------------------------------------------------------------------===// 228// Instruction format superclass 229//===----------------------------------------------------------------------===// 230 231include "MipsInstrFormats.td" 232 233//===----------------------------------------------------------------------===// 234// Mips Operand, Complex Patterns and Transformations Definitions. 235//===----------------------------------------------------------------------===// 236 237// Instruction operand types 238def jmptarget : Operand<OtherVT> { 239 let EncoderMethod = "getJumpTargetOpValue"; 240} 241def brtarget : Operand<OtherVT> { 242 let EncoderMethod = "getBranchTargetOpValue"; 243 let OperandType = "OPERAND_PCREL"; 244 let DecoderMethod = "DecodeBranchTarget"; 245} 246def calltarget : Operand<iPTR> { 247 let EncoderMethod = "getJumpTargetOpValue"; 248} 249def calltarget64: Operand<i64>; 250def simm16 : Operand<i32> { 251 let DecoderMethod= "DecodeSimm16"; 252} 253 254def simm20 : Operand<i32> { 255} 256 257def uimm20 : Operand<i32> { 258} 259 260def uimm10 : Operand<i32> { 261} 262 263def simm16_64 : Operand<i64>; 264def shamt : Operand<i32>; 265 266// Unsigned Operand 267def uimm5 : Operand<i32> { 268 let PrintMethod = "printUnsignedImm"; 269} 270 271def uimm16 : Operand<i32> { 272 let PrintMethod = "printUnsignedImm"; 273} 274 275def MipsMemAsmOperand : AsmOperandClass { 276 let Name = "Mem"; 277 let ParserMethod = "parseMemOperand"; 278} 279 280// Address operand 281def mem : Operand<i32> { 282 let PrintMethod = "printMemOperand"; 283 let MIOperandInfo = (ops GPR32, simm16); 284 let EncoderMethod = "getMemEncoding"; 285 let ParserMatchClass = MipsMemAsmOperand; 286 let OperandType = "OPERAND_MEMORY"; 287} 288 289def mem64 : Operand<i64> { 290 let PrintMethod = "printMemOperand"; 291 let MIOperandInfo = (ops GPR64, simm16_64); 292 let EncoderMethod = "getMemEncoding"; 293 let ParserMatchClass = MipsMemAsmOperand; 294 let OperandType = "OPERAND_MEMORY"; 295} 296 297def mem_ea : Operand<i32> { 298 let PrintMethod = "printMemOperandEA"; 299 let MIOperandInfo = (ops GPR32, simm16); 300 let EncoderMethod = "getMemEncoding"; 301 let OperandType = "OPERAND_MEMORY"; 302} 303 304def mem_ea_64 : Operand<i64> { 305 let PrintMethod = "printMemOperandEA"; 306 let MIOperandInfo = (ops GPR64, simm16_64); 307 let EncoderMethod = "getMemEncoding"; 308 let OperandType = "OPERAND_MEMORY"; 309} 310 311// size operand of ext instruction 312def size_ext : Operand<i32> { 313 let EncoderMethod = "getSizeExtEncoding"; 314 let DecoderMethod = "DecodeExtSize"; 315} 316 317// size operand of ins instruction 318def size_ins : Operand<i32> { 319 let EncoderMethod = "getSizeInsEncoding"; 320 let DecoderMethod = "DecodeInsSize"; 321} 322 323// Transformation Function - get the lower 16 bits. 324def LO16 : SDNodeXForm<imm, [{ 325 return getImm(N, N->getZExtValue() & 0xFFFF); 326}]>; 327 328// Transformation Function - get the higher 16 bits. 329def HI16 : SDNodeXForm<imm, [{ 330 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 331}]>; 332 333// Plus 1. 334def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 335 336// Node immediate fits as 16-bit sign extended on target immediate. 337// e.g. addi, andi 338def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 339 340// Node immediate fits as 16-bit sign extended on target immediate. 341// e.g. addi, andi 342def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 343 344// Node immediate fits as 15-bit sign extended on target immediate. 345// e.g. addi, andi 346def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 347 348// Node immediate fits as 16-bit zero extended on target immediate. 349// The LO16 param means that only the lower 16 bits of the node 350// immediate are caught. 351// e.g. addiu, sltiu 352def immZExt16 : PatLeaf<(imm), [{ 353 if (N->getValueType(0) == MVT::i32) 354 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 355 else 356 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 357}], LO16>; 358 359// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 360def immLow16Zero : PatLeaf<(imm), [{ 361 int64_t Val = N->getSExtValue(); 362 return isInt<32>(Val) && !(Val & 0xffff); 363}]>; 364 365// shamt field must fit in 5 bits. 366def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 367 368// True if (N + 1) fits in 16-bit field. 369def immSExt16Plus1 : PatLeaf<(imm), [{ 370 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 371}]>; 372 373// Mips Address Mode! SDNode frameindex could possibily be a match 374// since load and store instructions from stack used it. 375def addr : 376 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 377 378def addrRegImm : 379 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 380 381def addrDefault : 382 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 383 384//===----------------------------------------------------------------------===// 385// Instructions specific format 386//===----------------------------------------------------------------------===// 387 388// Arithmetic and logical instructions with 3 register operands. 389class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 390 InstrItinClass Itin = NoItinerary, 391 SDPatternOperator OpNode = null_frag>: 392 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 393 !strconcat(opstr, "\t$rd, $rs, $rt"), 394 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 395 let isCommutable = isComm; 396 let isReMaterializable = 1; 397} 398 399// Arithmetic and logical instructions with 2 register operands. 400class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 401 InstrItinClass Itin = NoItinerary, 402 SDPatternOperator imm_type = null_frag, 403 SDPatternOperator OpNode = null_frag> : 404 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 405 !strconcat(opstr, "\t$rt, $rs, $imm16"), 406 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 407 Itin, FrmI, opstr> { 408 let isReMaterializable = 1; 409 let TwoOperandAliasConstraint = "$rs = $rt"; 410} 411 412// Arithmetic Multiply ADD/SUB 413class MArithR<string opstr, bit isComm = 0> : 414 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 415 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> { 416 let Defs = [HI0, LO0]; 417 let Uses = [HI0, LO0]; 418 let isCommutable = isComm; 419} 420 421// Logical 422class LogicNOR<string opstr, RegisterOperand RO>: 423 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 424 !strconcat(opstr, "\t$rd, $rs, $rt"), 425 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> { 426 let isCommutable = 1; 427} 428 429// Shifts 430class shift_rotate_imm<string opstr, Operand ImmOpnd, 431 RegisterOperand RO, SDPatternOperator OpNode = null_frag, 432 SDPatternOperator PF = null_frag> : 433 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 434 !strconcat(opstr, "\t$rd, $rt, $shamt"), 435 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>; 436 437class shift_rotate_reg<string opstr, RegisterOperand RO, 438 SDPatternOperator OpNode = null_frag>: 439 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 440 !strconcat(opstr, "\t$rd, $rt, $rs"), 441 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>; 442 443// Load Upper Imediate 444class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 445 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 446 [], IIArith, FrmI>, IsAsCheapAsAMove { 447 let neverHasSideEffects = 1; 448 let isReMaterializable = 1; 449} 450 451class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 452 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 453 bits<21> addr; 454 let Inst{25-21} = addr{20-16}; 455 let Inst{15-0} = addr{15-0}; 456 let DecoderMethod = "DecodeMem"; 457} 458 459// Memory Load/Store 460class Load<string opstr, SDPatternOperator OpNode, DAGOperand RO, 461 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr, 462 string ofsuffix> : 463 InstSE<(outs RO:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 464 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, 465 !strconcat(opstr, ofsuffix)> { 466 let DecoderMethod = "DecodeMem"; 467 let canFoldAsLoad = 1; 468 let mayLoad = 1; 469} 470 471class Store<string opstr, SDPatternOperator OpNode, DAGOperand RO, 472 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr, 473 string ofsuffix> : 474 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 475 [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI, 476 !strconcat(opstr, ofsuffix)> { 477 let DecoderMethod = "DecodeMem"; 478 let mayStore = 1; 479} 480 481multiclass LoadM<string opstr, DAGOperand RO, 482 SDPatternOperator OpNode = null_frag, 483 InstrItinClass Itin = NoItinerary, 484 ComplexPattern Addr = addr> { 485 def NAME : Load<opstr, OpNode, RO, Itin, mem, Addr, "">, 486 Requires<[NotN64, HasStdEnc]>; 487 def _P8 : Load<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">, 488 Requires<[IsN64, HasStdEnc]> { 489 let DecoderNamespace = "Mips64"; 490 let isCodeGenOnly = 1; 491 } 492} 493 494multiclass StoreM<string opstr, DAGOperand RO, 495 SDPatternOperator OpNode = null_frag, 496 InstrItinClass Itin = NoItinerary, 497 ComplexPattern Addr = addr> { 498 def NAME : Store<opstr, OpNode, RO, Itin, mem, Addr, "">, 499 Requires<[NotN64, HasStdEnc]>; 500 def _P8 : Store<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">, 501 Requires<[IsN64, HasStdEnc]> { 502 let DecoderNamespace = "Mips64"; 503 let isCodeGenOnly = 1; 504 } 505} 506 507// Load/Store Left/Right 508let canFoldAsLoad = 1 in 509class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 510 Operand MemOpnd> : 511 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src), 512 !strconcat(opstr, "\t$rt, $addr"), 513 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> { 514 let DecoderMethod = "DecodeMem"; 515 string Constraints = "$src = $rt"; 516} 517 518class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 519 Operand MemOpnd>: 520 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 521 [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> { 522 let DecoderMethod = "DecodeMem"; 523} 524 525multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterOperand RO> { 526 def NAME : LoadLeftRight<opstr, OpNode, RO, mem>, 527 Requires<[NotN64, HasStdEnc, NotInMicroMips]>; 528 def _P8 : LoadLeftRight<opstr, OpNode, RO, mem64>, 529 Requires<[IsN64, HasStdEnc]> { 530 let DecoderNamespace = "Mips64"; 531 let isCodeGenOnly = 1; 532 } 533} 534 535multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterOperand RO> { 536 def NAME : StoreLeftRight<opstr, OpNode, RO, mem>, 537 Requires<[NotN64, HasStdEnc, NotInMicroMips]>; 538 def _P8 : StoreLeftRight<opstr, OpNode, RO, mem64>, 539 Requires<[IsN64, HasStdEnc]> { 540 let DecoderNamespace = "Mips64"; 541 let isCodeGenOnly = 1; 542 } 543} 544 545// Conditional Branch 546class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> : 547 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset), 548 !strconcat(opstr, "\t$rs, $rt, $offset"), 549 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 550 FrmI> { 551 let isBranch = 1; 552 let isTerminator = 1; 553 let hasDelaySlot = 1; 554 let Defs = [AT]; 555} 556 557class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> : 558 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 559 !strconcat(opstr, "\t$rs, $offset"), 560 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 561 let isBranch = 1; 562 let isTerminator = 1; 563 let hasDelaySlot = 1; 564 let Defs = [AT]; 565} 566 567// SetCC 568class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 569 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 570 !strconcat(opstr, "\t$rd, $rs, $rt"), 571 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 572 IIslt, FrmR, opstr>; 573 574class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 575 RegisterOperand RO>: 576 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 577 !strconcat(opstr, "\t$rt, $rs, $imm16"), 578 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 579 IIslt, FrmI, opstr>; 580 581// Jump 582class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 583 SDPatternOperator targetoperator> : 584 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 585 [(operator targetoperator:$target)], IIBranch, FrmJ> { 586 let isTerminator=1; 587 let isBarrier=1; 588 let hasDelaySlot = 1; 589 let DecoderMethod = "DecodeJumpTarget"; 590 let Defs = [AT]; 591} 592 593// Unconditional branch 594class UncondBranch<string opstr> : 595 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 596 [(br bb:$offset)], IIBranch, FrmI> { 597 let isBranch = 1; 598 let isTerminator = 1; 599 let isBarrier = 1; 600 let hasDelaySlot = 1; 601 let Predicates = [RelocPIC, HasStdEnc]; 602 let Defs = [AT]; 603} 604 605// Base class for indirect branch and return instruction classes. 606let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 607class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>: 608 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>; 609 610// Indirect branch 611class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> { 612 let isBranch = 1; 613 let isIndirectBranch = 1; 614} 615 616// Return instruction 617class RetBase<RegisterOperand RO>: JumpFR<RO> { 618 let isReturn = 1; 619 let isCodeGenOnly = 1; 620 let hasCtrlDep = 1; 621 let hasExtraSrcRegAllocReq = 1; 622} 623 624// Jump and Link (Call) 625let isCall=1, hasDelaySlot=1, Defs = [RA] in { 626 class JumpLink<string opstr> : 627 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 628 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 629 let DecoderMethod = "DecodeJumpTarget"; 630 } 631 632 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 633 Register RetReg, RegisterOperand ResRO = RO>: 634 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 635 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 636 637 class JumpLinkReg<string opstr, RegisterOperand RO>: 638 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 639 [], IIBranch, FrmR>; 640 641 class BGEZAL_FT<string opstr, RegisterOperand RO> : 642 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 643 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 644 645} 646 647class BAL_BR_Pseudo<Instruction RealInst> : 648 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 649 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 650 let isBranch = 1; 651 let isTerminator = 1; 652 let isBarrier = 1; 653 let hasDelaySlot = 1; 654 let Defs = [RA]; 655} 656 657// Syscall 658class SYS_FT<string opstr> : 659 InstSE<(outs), (ins uimm20:$code_), 660 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; 661// Break 662class BRK_FT<string opstr> : 663 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 664 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; 665 666// (D)Eret 667class ER_FT<string opstr> : 668 InstSE<(outs), (ins), 669 opstr, [], NoItinerary, FrmOther>; 670 671// Interrupts 672class DEI_FT<string opstr, RegisterOperand RO> : 673 InstSE<(outs RO:$rt), (ins), 674 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>; 675 676// Wait 677class WAIT_FT<string opstr> : 678 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> { 679 let Inst{31-26} = 0x10; 680 let Inst{25} = 1; 681 let Inst{24-6} = 0; 682 let Inst{5-0} = 0x20; 683} 684 685// Sync 686let hasSideEffects = 1 in 687class SYNC_FT : 688 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 689 NoItinerary, FrmOther>; 690 691let hasSideEffects = 1 in 692class TEQ_FT<string opstr, RegisterOperand RO> : 693 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 694 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; 695 696// Mul, Div 697class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 698 list<Register> DefRegs> : 699 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 700 itin, FrmR, opstr> { 701 let isCommutable = 1; 702 let Defs = DefRegs; 703 let neverHasSideEffects = 1; 704} 705 706// Pseudo multiply/divide instruction with explicit accumulator register 707// operands. 708class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 709 SDPatternOperator OpNode, InstrItinClass Itin, 710 bit IsComm = 1, bit HasSideEffects = 0, 711 bit UsesCustomInserter = 0> : 712 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 713 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 714 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 715 let isCommutable = IsComm; 716 let hasSideEffects = HasSideEffects; 717 let usesCustomInserter = UsesCustomInserter; 718} 719 720// Pseudo multiply add/sub instruction with explicit accumulator register 721// operands. 722class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 723 : PseudoSE<(outs ACC64:$ac), 724 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 725 [(set ACC64:$ac, 726 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 727 IIImult>, 728 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 729 string Constraints = "$acin = $ac"; 730} 731 732class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 733 list<Register> DefRegs> : 734 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 735 [], itin, FrmR> { 736 let Defs = DefRegs; 737} 738 739// Move from Hi/Lo 740class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>: 741 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 742 let Uses = UseRegs; 743 let neverHasSideEffects = 1; 744} 745 746class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 747 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 748 let Defs = DefRegs; 749 let neverHasSideEffects = 1; 750} 751 752class EffectiveAddress<string opstr, RegisterOperand RO, Operand Mem> : 753 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 754 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> { 755 let isCodeGenOnly = 1; 756 let DecoderMethod = "DecodeMem"; 757} 758 759// Count Leading Ones/Zeros in Word 760class CountLeading0<string opstr, RegisterOperand RO>: 761 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 762 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>, 763 Requires<[HasBitCount, HasStdEnc]>; 764 765class CountLeading1<string opstr, RegisterOperand RO>: 766 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 767 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>, 768 Requires<[HasBitCount, HasStdEnc]>; 769 770 771// Sign Extend in Register. 772class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> : 773 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 774 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> { 775 let Predicates = [HasSEInReg, HasStdEnc]; 776} 777 778// Subword Swap 779class SubwordSwap<string opstr, RegisterOperand RO>: 780 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 781 NoItinerary, FrmR> { 782 let Predicates = [HasSwap, HasStdEnc]; 783 let neverHasSideEffects = 1; 784} 785 786// Read Hardware 787class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 788 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 789 IIArith, FrmR>; 790 791// Ext and Ins 792class ExtBase<string opstr, RegisterOperand RO>: 793 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 794 !strconcat(opstr, " $rt, $rs, $pos, $size"), 795 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 796 FrmR> { 797 let Predicates = [HasMips32r2, HasStdEnc]; 798} 799 800class InsBase<string opstr, RegisterOperand RO>: 801 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 802 !strconcat(opstr, " $rt, $rs, $pos, $size"), 803 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 804 NoItinerary, FrmR> { 805 let Predicates = [HasMips32r2, HasStdEnc]; 806 let Constraints = "$src = $rt"; 807} 808 809// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 810class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 811 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 812 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 813 814multiclass Atomic2Ops32<PatFrag Op> { 815 def NAME : Atomic2Ops<Op, GPR32, GPR32>, Requires<[NotN64, HasStdEnc]>; 816 def _P8 : Atomic2Ops<Op, GPR32, GPR64>, Requires<[IsN64, HasStdEnc]>; 817} 818 819// Atomic Compare & Swap. 820class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 821 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 822 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 823 824multiclass AtomicCmpSwap32<PatFrag Op> { 825 def NAME : AtomicCmpSwap<Op, GPR32, GPR32>, 826 Requires<[NotN64, HasStdEnc]>; 827 def _P8 : AtomicCmpSwap<Op, GPR32, GPR64>, 828 Requires<[IsN64, HasStdEnc]>; 829} 830 831class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 832 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 833 [], NoItinerary, FrmI> { 834 let DecoderMethod = "DecodeMem"; 835 let mayLoad = 1; 836} 837 838class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 839 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 840 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 841 let DecoderMethod = "DecodeMem"; 842 let mayStore = 1; 843 let Constraints = "$rt = $dst"; 844} 845 846class MFC3OP<dag outs, dag ins, string asmstr> : 847 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 848 849let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in 850def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> { 851 let Inst = 0x0000000d; 852} 853 854//===----------------------------------------------------------------------===// 855// Pseudo instructions 856//===----------------------------------------------------------------------===// 857 858// Return RA. 859let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 860def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 861 862let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 863def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 864 [(callseq_start timm:$amt)]>; 865def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 866 [(callseq_end timm:$amt1, timm:$amt2)]>; 867} 868 869let usesCustomInserter = 1 in { 870 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 871 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 872 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 873 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 874 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 875 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 876 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 877 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 878 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 879 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 880 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 881 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 882 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 883 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 884 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 885 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 886 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 887 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 888 889 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 890 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 891 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 892 893 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 894 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 895 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 896} 897 898/// Pseudo instructions for loading and storing accumulator registers. 899let isPseudo = 1, isCodeGenOnly = 1 in { 900 defm LOAD_ACC64 : LoadM<"", ACC64>; 901 defm STORE_ACC64 : StoreM<"", ACC64>; 902} 903 904//===----------------------------------------------------------------------===// 905// Instruction definition 906//===----------------------------------------------------------------------===// 907//===----------------------------------------------------------------------===// 908// MipsI Instructions 909//===----------------------------------------------------------------------===// 910 911/// Arithmetic Instructions (ALU Immediate) 912def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16, 913 add>, 914 ADDI_FM<0x9>, IsAsCheapAsAMove; 915def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>; 916def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 917 SLTI_FM<0xa>; 918def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 919 SLTI_FM<0xb>; 920def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16, 921 and>, 922 ADDI_FM<0xc>; 923def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16, 924 or>, 925 ADDI_FM<0xd>; 926def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16, 927 xor>, 928 ADDI_FM<0xe>; 929def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 930 931/// Arithmetic Instructions (3-Operand, R-Type) 932def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>, 933 ADD_FM<0, 0x21>; 934def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>, 935 ADD_FM<0, 0x23>; 936def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>, 937 ADD_FM<0x1c, 2>; 938def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 939def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 940def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 941def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 942def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>, 943 ADD_FM<0, 0x24>; 944def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>, 945 ADD_FM<0, 0x25>; 946def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>, 947 ADD_FM<0, 0x26>; 948def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 949 950/// Shift Instructions 951def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>, 952 SRA_FM<0, 0>; 953def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>, 954 SRA_FM<2, 0>; 955def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>, 956 SRA_FM<3, 0>; 957def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>; 958def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>; 959def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>; 960 961// Rotate Instructions 962let Predicates = [HasMips32r2, HasStdEnc] in { 963 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr, 964 immZExt5>, 965 SRA_FM<2, 1>; 966 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>, 967 SRLV_FM<6, 1>; 968} 969 970/// Load and Store Instructions 971/// aligned 972defm LB : LoadM<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>; 973defm LBu : LoadM<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel, 974 LW_FM<0x24>; 975defm LH : LoadM<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel, 976 LW_FM<0x21>; 977defm LHu : LoadM<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; 978defm LW : LoadM<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, 979 LW_FM<0x23>; 980defm SB : StoreM<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; 981defm SH : StoreM<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; 982defm SW : StoreM<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; 983 984/// load/store left/right 985defm LWL : LoadLeftRightM<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>; 986defm LWR : LoadLeftRightM<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>; 987defm SWL : StoreLeftRightM<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>; 988defm SWR : StoreLeftRightM<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>; 989 990def SYNC : SYNC_FT, SYNC_FM; 991def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 992 993def BREAK : BRK_FT<"break">, BRK_FM<0xd>; 994def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; 995 996def ERET : ER_FT<"eret">, ER_FM<0x18>; 997def DERET : ER_FT<"deret">, ER_FM<0x1f>; 998 999def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; 1000def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>; 1001 1002def WAIT : WAIT_FT<"wait">; 1003 1004/// Load-linked, Store-conditional 1005let Predicates = [NotN64, HasStdEnc] in { 1006 def LL : LLBase<"ll", GPR32Opnd, mem>, LW_FM<0x30>; 1007 def SC : SCBase<"sc", GPR32Opnd, mem>, LW_FM<0x38>; 1008} 1009 1010let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 1011 def LL_P8 : LLBase<"ll", GPR32Opnd, mem64>, LW_FM<0x30>; 1012 def SC_P8 : SCBase<"sc", GPR32Opnd, mem64>, LW_FM<0x38>; 1013} 1014 1015/// Jump and Branch Instructions 1016def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 1017 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 1018def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>; 1019def B : UncondBranch<"b">, B_FM; 1020def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>; 1021def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>; 1022def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>; 1023def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>; 1024def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>; 1025def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>; 1026 1027def JAL : JumpLink<"jal">, FJ<3>; 1028def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 1029def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 1030def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>; 1031def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>; 1032def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 1033def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 1034def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall; 1035 1036def RET : RetBase<GPR32Opnd>, MTLO_FM<8>; 1037 1038// Exception handling related node and instructions. 1039// The conversion sequence is: 1040// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1041// MIPSeh_return -> (stack change + indirect branch) 1042// 1043// MIPSeh_return takes the place of regular return instruction 1044// but takes two arguments (V1, V0) which are used for storing 1045// the offset and return address respectively. 1046def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1047 1048def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1049 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1050 1051let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1052 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1053 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1054 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1055 GPR64:$dst), 1056 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1057} 1058 1059/// Multiply and Divide Instructions. 1060def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>, 1061 MULT_FM<0, 0x18>; 1062def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>, 1063 MULT_FM<0, 0x19>; 1064def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; 1065def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; 1066def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>; 1067def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>; 1068def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, 1069 0, 1, 1>; 1070def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, 1071 0, 1, 1>; 1072 1073def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; 1074def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; 1075def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>; 1076def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>; 1077 1078/// Sign Ext In Register Instructions. 1079def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; 1080def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; 1081 1082/// Count Leading 1083def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; 1084def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; 1085 1086/// Word Swap Bytes Within Halfwords 1087def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; 1088 1089/// No operation. 1090def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1091 1092// FrameIndexes are legalized when they are operands from load/store 1093// instructions. The same not happens for stack address copies, so an 1094// add op with mem ComplexPattern is used and the stack address copy 1095// can be matched. It's similar to Sparc LEA_ADDRi 1096def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd, mem_ea>, LW_FM<9>; 1097 1098// MADD*/MSUB* 1099def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1100def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1101def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1102def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1103def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1104def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1105def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1106def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1107 1108def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1109 1110def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>; 1111def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>; 1112 1113/// Move Control Registers From/To CPU Registers 1114def MFC0_3OP : MFC3OP<(outs GPR32Opnd:$rt), 1115 (ins GPR32Opnd:$rd, uimm16:$sel), 1116 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 1117 1118def MTC0_3OP : MFC3OP<(outs GPR32Opnd:$rd, uimm16:$sel), 1119 (ins GPR32Opnd:$rt), 1120 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 1121 1122def MFC2_3OP : MFC3OP<(outs GPR32Opnd:$rt), 1123 (ins GPR32Opnd:$rd, uimm16:$sel), 1124 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 1125 1126def MTC2_3OP : MFC3OP<(outs GPR32Opnd:$rd, uimm16:$sel), 1127 (ins GPR32Opnd:$rt), 1128 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 1129 1130//===----------------------------------------------------------------------===// 1131// Instruction aliases 1132//===----------------------------------------------------------------------===// 1133def : InstAlias<"move $dst, $src", 1134 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1135 Requires<[NotMips64]>; 1136def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; 1137def : InstAlias<"addu $rs, $rt, $imm", 1138 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1139def : InstAlias<"add $rs, $rt, $imm", 1140 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1141def : InstAlias<"and $rs, $rt, $imm", 1142 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1143def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1144def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1145def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1146def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1147def : InstAlias<"not $rt, $rs", 1148 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1149def : InstAlias<"neg $rt, $rs", 1150 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1151def : InstAlias<"negu $rt, $rs", 1152 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1153def : InstAlias<"slt $rs, $rt, $imm", 1154 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1155def : InstAlias<"xor $rs, $rt, $imm", 1156 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1157def : InstAlias<"or $rs, $rt, $imm", 1158 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1159def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1160def : InstAlias<"mfc0 $rt, $rd", 1161 (MFC0_3OP GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1162def : InstAlias<"mtc0 $rt, $rd", 1163 (MTC0_3OP GPR32Opnd:$rd, 0, GPR32Opnd:$rt), 0>; 1164def : InstAlias<"mfc2 $rt, $rd", 1165 (MFC2_3OP GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1166def : InstAlias<"mtc2 $rt, $rd", 1167 (MTC2_3OP GPR32Opnd:$rd, 0, GPR32Opnd:$rt), 0>; 1168def : InstAlias<"bnez $rs,$offset", 1169 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1170def : InstAlias<"beqz $rs,$offset", 1171 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1172def : InstAlias<"syscall", (SYSCALL 0), 1>; 1173 1174def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1175def : InstAlias<"break", (BREAK 0, 0), 1>; 1176def : InstAlias<"ei", (EI ZERO), 1>; 1177def : InstAlias<"di", (DI ZERO), 1>; 1178//===----------------------------------------------------------------------===// 1179// Assembler Pseudo Instructions 1180//===----------------------------------------------------------------------===// 1181 1182class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1183 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1184 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1185def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>; 1186 1187class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1188 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1189 !strconcat(instr_asm, "\t$rt, $addr")> ; 1190def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1191 1192class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1193 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1194 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1195def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>; 1196 1197 1198 1199//===----------------------------------------------------------------------===// 1200// Arbitrary patterns that map to one or more instructions 1201//===----------------------------------------------------------------------===// 1202 1203// Load/store pattern templates. 1204class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1205 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1206 1207class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1208 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1209 1210// Small immediates 1211def : MipsPat<(i32 immSExt16:$in), 1212 (ADDiu ZERO, imm:$in)>; 1213def : MipsPat<(i32 immZExt16:$in), 1214 (ORi ZERO, imm:$in)>; 1215def : MipsPat<(i32 immLow16Zero:$in), 1216 (LUi (HI16 imm:$in))>; 1217 1218// Arbitrary immediates 1219def : MipsPat<(i32 imm:$imm), 1220 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1221 1222// Carry MipsPatterns 1223def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1224 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1225let Predicates = [HasStdEnc, NotDSP] in { 1226 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1227 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1228 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1229 (ADDiu GPR32:$src, imm:$imm)>; 1230} 1231 1232// Call 1233def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1234 (JAL tglobaladdr:$dst)>; 1235def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1236 (JAL texternalsym:$dst)>; 1237//def : MipsPat<(MipsJmpLink GPR32:$dst), 1238// (JALR GPR32:$dst)>; 1239 1240// Tail call 1241def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1242 (TAILCALL tglobaladdr:$dst)>; 1243def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1244 (TAILCALL texternalsym:$dst)>; 1245// hi/lo relocs 1246def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1247def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1248def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1249def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1250def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1251def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1252 1253def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1254def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1255def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1256def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1257def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1258def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1259 1260def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1261 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1262def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1263 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1264def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1265 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1266def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1267 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1268def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1269 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1270 1271// gp_rel relocs 1272def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1273 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1274def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1275 (ADDiu GPR32:$gp, tconstpool:$in)>; 1276 1277// wrapper_pic 1278class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1279 MipsPat<(MipsWrapper RC:$gp, node:$in), 1280 (ADDiuOp RC:$gp, node:$in)>; 1281 1282def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1283def : WrapperPat<tconstpool, ADDiu, GPR32>; 1284def : WrapperPat<texternalsym, ADDiu, GPR32>; 1285def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1286def : WrapperPat<tjumptable, ADDiu, GPR32>; 1287def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1288 1289// Mips does not have "not", so we expand our way 1290def : MipsPat<(not GPR32:$in), 1291 (NOR GPR32Opnd:$in, ZERO)>; 1292 1293// extended loads 1294let Predicates = [NotN64, HasStdEnc] in { 1295 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1296 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1297 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1298} 1299let Predicates = [IsN64, HasStdEnc] in { 1300 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1301 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1302 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1303} 1304 1305// peepholes 1306let Predicates = [NotN64, HasStdEnc] in { 1307 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1308} 1309let Predicates = [IsN64, HasStdEnc] in { 1310 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1311} 1312 1313// brcond patterns 1314multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1315 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1316 Instruction SLTiuOp, Register ZEROReg> { 1317def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1318 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1319def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1320 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1321 1322def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1323 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1324def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1325 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1326def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1327 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1328def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1329 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1330def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1331 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1332def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1333 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1334 1335def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1336 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1337def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1338 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1339 1340def : MipsPat<(brcond RC:$cond, bb:$dst), 1341 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1342} 1343 1344defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1345 1346def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1347 (BLEZ i32:$lhs, bb:$dst)>; 1348def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1349 (BGEZ i32:$lhs, bb:$dst)>; 1350 1351// setcc patterns 1352multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1353 Instruction SLTuOp, Register ZEROReg> { 1354 def : MipsPat<(seteq RC:$lhs, 0), 1355 (SLTiuOp RC:$lhs, 1)>; 1356 def : MipsPat<(setne RC:$lhs, 0), 1357 (SLTuOp ZEROReg, RC:$lhs)>; 1358 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1359 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1360 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1361 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1362} 1363 1364multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1365 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1366 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1367 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1368 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1369} 1370 1371multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1372 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1373 (SLTOp RC:$rhs, RC:$lhs)>; 1374 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1375 (SLTuOp RC:$rhs, RC:$lhs)>; 1376} 1377 1378multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1379 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1380 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1381 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1382 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1383} 1384 1385multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1386 Instruction SLTiuOp> { 1387 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1388 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1389 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1390 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1391} 1392 1393defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1394defm : SetlePats<GPR32, SLT, SLTu>; 1395defm : SetgtPats<GPR32, SLT, SLTu>; 1396defm : SetgePats<GPR32, SLT, SLTu>; 1397defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1398 1399// bswap pattern 1400def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1401 1402// mflo/hi patterns. 1403def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)), 1404 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>; 1405 1406// Load halfword/word patterns. 1407let AddedComplexity = 40 in { 1408 let Predicates = [NotN64, HasStdEnc] in { 1409 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1410 def : LoadRegImmPat<LH, i32, sextloadi16>; 1411 def : LoadRegImmPat<LW, i32, load>; 1412 } 1413 let Predicates = [IsN64, HasStdEnc] in { 1414 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>; 1415 def : LoadRegImmPat<LH_P8, i32, sextloadi16>; 1416 def : LoadRegImmPat<LW_P8, i32, load>; 1417 } 1418} 1419 1420//===----------------------------------------------------------------------===// 1421// Floating Point Support 1422//===----------------------------------------------------------------------===// 1423 1424include "MipsInstrFPU.td" 1425include "Mips64InstrInfo.td" 1426include "MipsCondMov.td" 1427 1428// 1429// Mips16 1430 1431include "Mips16InstrFormats.td" 1432include "Mips16InstrInfo.td" 1433 1434// DSP 1435include "MipsDSPInstrFormats.td" 1436include "MipsDSPInstrInfo.td" 1437 1438// MSA 1439include "MipsMSAInstrFormats.td" 1440include "MipsMSAInstrInfo.td" 1441 1442// Micromips 1443include "MicroMipsInstrFormats.td" 1444include "MicroMipsInstrInfo.td" 1445