MipsInstrInfo.td revision 8e719fac46c3c79dedfde86bf439819444223537
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 15-bit sign extended on target immediate. 302// e.g. addi, andi 303def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 304 305// Node immediate fits as 16-bit zero extended on target immediate. 306// The LO16 param means that only the lower 16 bits of the node 307// immediate are caught. 308// e.g. addiu, sltiu 309def immZExt16 : PatLeaf<(imm), [{ 310 if (N->getValueType(0) == MVT::i32) 311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 312 else 313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 314}], LO16>; 315 316// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 317def immLow16Zero : PatLeaf<(imm), [{ 318 int64_t Val = N->getSExtValue(); 319 return isInt<32>(Val) && !(Val & 0xffff); 320}]>; 321 322// shamt field must fit in 5 bits. 323def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 324 325// Mips Address Mode! SDNode frameindex could possibily be a match 326// since load and store instructions from stack used it. 327def addr : 328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 329 330//===----------------------------------------------------------------------===// 331// Instructions specific format 332//===----------------------------------------------------------------------===// 333 334// Arithmetic and logical instructions with 3 register operands. 335class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0, 336 InstrItinClass Itin = NoItinerary, 337 SDPatternOperator OpNode = null_frag>: 338 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 339 !strconcat(opstr, "\t$rd, $rs, $rt"), 340 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 341 let isCommutable = isComm; 342 let isReMaterializable = 1; 343} 344 345// Arithmetic and logical instructions with 2 register operands. 346class ArithLogicI<string opstr, Operand Od, RegisterClass RC, 347 SDPatternOperator imm_type = null_frag, 348 SDPatternOperator OpNode = null_frag> : 349 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 350 !strconcat(opstr, "\t$rt, $rs, $imm16"), 351 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 352 let isReMaterializable = 1; 353} 354 355// Arithmetic Multiply ADD/SUB 356let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 357class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 358 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 359 !strconcat(instr_asm, "\t$rs, $rt"), 360 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 361 let rd = 0; 362 let shamt = 0; 363 let isCommutable = isComm; 364} 365 366// Logical 367class LogicNOR<string opstr, RegisterClass RC>: 368 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 369 !strconcat(opstr, "\t$rd, $rs, $rt"), 370 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 371 let isCommutable = 1; 372} 373 374// Shifts 375class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd, 376 RegisterClass RC, SDPatternOperator OpNode> : 377 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 378 !strconcat(opstr, "\t$rd, $rt, $shamt"), 379 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 380 381// 32-bit shift instructions. 382class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> : 383 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>; 384 385class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>: 386 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 387 !strconcat(opstr, "\t$rd, $rt, $rs"), 388 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; 389 390// Load Upper Imediate 391class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 392 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 393 [], IIAlu, FrmI>, IsAsCheapAsAMove { 394 let neverHasSideEffects = 1; 395 let isReMaterializable = 1; 396} 397 398class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 399 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 400 bits<21> addr; 401 let Inst{25-21} = addr{20-16}; 402 let Inst{15-0} = addr{15-0}; 403 let DecoderMethod = "DecodeMem"; 404} 405 406// Memory Load/Store 407let canFoldAsLoad = 1 in 408class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 409 Operand MemOpnd, bit Pseudo>: 410 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 411 !strconcat(instr_asm, "\t$rt, $addr"), 412 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 413 let isPseudo = Pseudo; 414} 415 416class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 417 Operand MemOpnd, bit Pseudo>: 418 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 419 !strconcat(instr_asm, "\t$rt, $addr"), 420 [(OpNode RC:$rt, addr:$addr)], IIStore> { 421 let isPseudo = Pseudo; 422} 423 424// 32-bit load. 425multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 426 bit Pseudo = 0> { 427 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 428 Requires<[NotN64, HasStdEnc]>; 429 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 430 Requires<[IsN64, HasStdEnc]> { 431 let DecoderNamespace = "Mips64"; 432 let isCodeGenOnly = 1; 433 } 434} 435 436// 64-bit load. 437multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 438 bit Pseudo = 0> { 439 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 440 Requires<[NotN64, HasStdEnc]>; 441 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 442 Requires<[IsN64, HasStdEnc]> { 443 let DecoderNamespace = "Mips64"; 444 let isCodeGenOnly = 1; 445 } 446} 447 448// 32-bit store. 449multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 450 bit Pseudo = 0> { 451 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 452 Requires<[NotN64, HasStdEnc]>; 453 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 454 Requires<[IsN64, HasStdEnc]> { 455 let DecoderNamespace = "Mips64"; 456 let isCodeGenOnly = 1; 457 } 458} 459 460// 64-bit store. 461multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 462 bit Pseudo = 0> { 463 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 464 Requires<[NotN64, HasStdEnc]>; 465 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 466 Requires<[IsN64, HasStdEnc]> { 467 let DecoderNamespace = "Mips64"; 468 let isCodeGenOnly = 1; 469 } 470} 471 472// Load/Store Left/Right 473let canFoldAsLoad = 1 in 474class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 475 RegisterClass RC, Operand MemOpnd> : 476 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 477 !strconcat(instr_asm, "\t$rt, $addr"), 478 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 479 string Constraints = "$src = $rt"; 480} 481 482class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 483 RegisterClass RC, Operand MemOpnd>: 484 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 485 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 486 IIStore>; 487 488// 32-bit load left/right. 489multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 490 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 491 Requires<[NotN64, HasStdEnc]>; 492 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 493 Requires<[IsN64, HasStdEnc]> { 494 let DecoderNamespace = "Mips64"; 495 let isCodeGenOnly = 1; 496 } 497} 498 499// 64-bit load left/right. 500multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 501 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 502 Requires<[NotN64, HasStdEnc]>; 503 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 504 Requires<[IsN64, HasStdEnc]> { 505 let DecoderNamespace = "Mips64"; 506 let isCodeGenOnly = 1; 507 } 508} 509 510// 32-bit store left/right. 511multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 512 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 513 Requires<[NotN64, HasStdEnc]>; 514 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 515 Requires<[IsN64, HasStdEnc]> { 516 let DecoderNamespace = "Mips64"; 517 let isCodeGenOnly = 1; 518 } 519} 520 521// 64-bit store left/right. 522multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 523 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 524 Requires<[NotN64, HasStdEnc]>; 525 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 526 Requires<[IsN64, HasStdEnc]> { 527 let DecoderNamespace = "Mips64"; 528 let isCodeGenOnly = 1; 529 } 530} 531 532// Conditional Branch 533class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 534 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 535 !strconcat(opstr, "\t$rs, $rt, $offset"), 536 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 537 FrmI> { 538 let isBranch = 1; 539 let isTerminator = 1; 540 let hasDelaySlot = 1; 541 let Defs = [AT]; 542} 543 544class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 545 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 546 !strconcat(opstr, "\t$rs, $offset"), 547 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 548 let isBranch = 1; 549 let isTerminator = 1; 550 let hasDelaySlot = 1; 551 let Defs = [AT]; 552} 553 554// SetCC 555class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 556 InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 557 !strconcat(opstr, "\t$rd, $rs, $rt"), 558 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 559 560class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 561 RegisterClass RC>: 562 InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 563 !strconcat(opstr, "\t$rt, $rs, $imm16"), 564 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>; 565 566// Jump 567class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 568 SDPatternOperator operator, SDPatternOperator targetoperator>: 569 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 570 [(operator targetoperator:$target)], IIBranch> { 571 let isTerminator=1; 572 let isBarrier=1; 573 let hasDelaySlot = 1; 574 let DecoderMethod = "DecodeJumpTarget"; 575 let Defs = [AT]; 576} 577 578// Unconditional branch 579class UncondBranch<string opstr> : 580 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 581 [(br bb:$offset)], IIBranch, FrmI> { 582 let isBranch = 1; 583 let isTerminator = 1; 584 let isBarrier = 1; 585 let hasDelaySlot = 1; 586 let Predicates = [RelocPIC, HasStdEnc]; 587 let Defs = [AT]; 588} 589 590// Base class for indirect branch and return instruction classes. 591let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 592class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 593 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 594 let rt = 0; 595 let rd = 0; 596 let shamt = 0; 597} 598 599// Indirect branch 600class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 601 let isBranch = 1; 602 let isIndirectBranch = 1; 603} 604 605// Return instruction 606class RetBase<RegisterClass RC>: JumpFR<RC> { 607 let isReturn = 1; 608 let isCodeGenOnly = 1; 609 let hasCtrlDep = 1; 610 let hasExtraSrcRegAllocReq = 1; 611} 612 613// Jump and Link (Call) 614let isCall=1, hasDelaySlot=1, Defs = [RA] in { 615 class JumpLink<bits<6> op, string instr_asm>: 616 FJ<op, (outs), (ins calltarget:$target), 617 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 618 IIBranch> { 619 let DecoderMethod = "DecodeJumpTarget"; 620 } 621 622 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 623 RegisterClass RC>: 624 FR<op, func, (outs), (ins RC:$rs), 625 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 626 let rt = 0; 627 let rd = 31; 628 let shamt = 0; 629 } 630 631 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 632 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 633 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 634 let rt = _rt; 635 } 636} 637 638// Mul, Div 639class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 640 RegisterClass RC, list<Register> DefRegs>: 641 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 642 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 643 let rd = 0; 644 let shamt = 0; 645 let isCommutable = 1; 646 let Defs = DefRegs; 647 let neverHasSideEffects = 1; 648} 649 650class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 651 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 652 653class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 654 RegisterClass RC, list<Register> DefRegs>: 655 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 656 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 657 [(op RC:$rs, RC:$rt)], itin> { 658 let rd = 0; 659 let shamt = 0; 660 let Defs = DefRegs; 661} 662 663class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 664 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 665 666// Move from Hi/Lo 667class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 668 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 669 let Uses = UseRegs; 670 let neverHasSideEffects = 1; 671} 672 673class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 674 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 675 let Defs = DefRegs; 676 let neverHasSideEffects = 1; 677} 678 679class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 680 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 681 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 682 let isCodeGenOnly = 1; 683} 684 685// Count Leading Ones/Zeros in Word 686class CountLeading0<string opstr, RegisterClass RC>: 687 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 688 [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>, 689 Requires<[HasBitCount, HasStdEnc]>; 690 691class CountLeading1<string opstr, RegisterClass RC>: 692 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 693 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>, 694 Requires<[HasBitCount, HasStdEnc]>; 695 696 697// Sign Extend in Register. 698class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 699 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 700 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 701 let Predicates = [HasSEInReg, HasStdEnc]; 702} 703 704// Subword Swap 705class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 706 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 707 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 708 let rs = 0; 709 let shamt = sa; 710 let Predicates = [HasSwap, HasStdEnc]; 711 let neverHasSideEffects = 1; 712} 713 714// Read Hardware 715class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 716 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 717 "rdhwr\t$rt, $rd", [], IIAlu> { 718 let rs = 0; 719 let shamt = 0; 720} 721 722// Ext and Ins 723class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 724 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 725 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 726 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 727 bits<5> pos; 728 bits<5> sz; 729 let rd = sz; 730 let shamt = pos; 731 let Predicates = [HasMips32r2, HasStdEnc]; 732} 733 734class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 735 FR<0x1f, _funct, (outs RC:$rt), 736 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 737 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 738 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 739 NoItinerary> { 740 bits<5> pos; 741 bits<5> sz; 742 let rd = sz; 743 let shamt = pos; 744 let Predicates = [HasMips32r2, HasStdEnc]; 745 let Constraints = "$src = $rt"; 746} 747 748// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 749class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 750 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 751 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 752 753multiclass Atomic2Ops32<PatFrag Op> { 754 def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 755 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 756 Requires<[IsN64, HasStdEnc]> { 757 let DecoderNamespace = "Mips64"; 758 } 759} 760 761// Atomic Compare & Swap. 762class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 763 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 764 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 765 766multiclass AtomicCmpSwap32<PatFrag Op> { 767 def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>, 768 Requires<[NotN64, HasStdEnc]>; 769 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 770 Requires<[IsN64, HasStdEnc]> { 771 let DecoderNamespace = "Mips64"; 772 } 773} 774 775class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 776 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 777 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 778 let mayLoad = 1; 779} 780 781class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 782 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 783 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 784 let mayStore = 1; 785 let Constraints = "$rt = $dst"; 786} 787 788//===----------------------------------------------------------------------===// 789// Pseudo instructions 790//===----------------------------------------------------------------------===// 791 792// Return RA. 793let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 794def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 795 796let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 797def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 798 [(callseq_start timm:$amt)]>; 799def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 800 [(callseq_end timm:$amt1, timm:$amt2)]>; 801} 802 803let usesCustomInserter = 1 in { 804 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 805 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 806 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 807 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 808 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 809 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 810 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 811 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 812 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 813 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 814 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 815 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 816 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 817 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 818 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 819 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 820 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 821 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 822 823 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 824 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 825 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 826 827 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 828 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 829 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 830} 831 832//===----------------------------------------------------------------------===// 833// Instruction definition 834//===----------------------------------------------------------------------===// 835//===----------------------------------------------------------------------===// 836// MipsI Instructions 837//===----------------------------------------------------------------------===// 838 839/// Arithmetic Instructions (ALU Immediate) 840def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, 841 ADDI_FM<0x9>, IsAsCheapAsAMove; 842def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; 843def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 844def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 845def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; 846def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; 847def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; 848def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 849 850/// Arithmetic Instructions (3-Operand, R-Type) 851def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; 852def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 853def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 854def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; 855def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; 856def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 857def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 858def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 859def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 860def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 861def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>; 862 863/// Shift Instructions 864def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>; 865def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>; 866def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>; 867def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>; 868def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>; 869def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>; 870 871// Rotate Instructions 872let Predicates = [HasMips32r2, HasStdEnc] in { 873 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>; 874 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>; 875} 876 877/// Load and Store Instructions 878/// aligned 879defm LB : LoadM32<0x20, "lb", sextloadi8>; 880defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 881defm LH : LoadM32<0x21, "lh", sextloadi16>; 882defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 883defm LW : LoadM32<0x23, "lw", load>; 884defm SB : StoreM32<0x28, "sb", truncstorei8>; 885defm SH : StoreM32<0x29, "sh", truncstorei16>; 886defm SW : StoreM32<0x2b, "sw", store>; 887 888/// load/store left/right 889defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 890defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 891defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 892defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 893 894let hasSideEffects = 1 in 895def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 896 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 897{ 898 bits<5> stype; 899 let Opcode = 0; 900 let Inst{25-11} = 0; 901 let Inst{10-6} = stype; 902 let Inst{5-0} = 15; 903} 904 905/// Load-linked, Store-conditional 906def LL : LLBase<0x30, "ll", CPURegs, mem>, 907 Requires<[NotN64, HasStdEnc]>; 908def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 909 Requires<[IsN64, HasStdEnc]> { 910 let DecoderNamespace = "Mips64"; 911} 912 913def SC : SCBase<0x38, "sc", CPURegs, mem>, 914 Requires<[NotN64, HasStdEnc]>; 915def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 916 Requires<[IsN64, HasStdEnc]> { 917 let DecoderNamespace = "Mips64"; 918} 919 920/// Jump and Branch Instructions 921def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 922 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 923def JR : IndirectBranch<CPURegs>; 924def B : UncondBranch<"b">, B_FM; 925def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 926def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 927def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 928def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 929def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 930def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 931 932let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 933 hasDelaySlot = 1, Defs = [RA] in 934def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 935 936def JAL : JumpLink<0x03, "jal">; 937def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 938def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 939def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 940def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 941def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 942 943def RET : RetBase<CPURegs>; 944 945/// Multiply and Divide Instructions. 946def MULT : Mult32<0x18, "mult", IIImul>; 947def MULTu : Mult32<0x19, "multu", IIImul>; 948def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 949def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 950 951def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 952def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 953def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 954def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 955 956/// Sign Ext In Register Instructions. 957def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10>; 958def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18>; 959 960/// Count Leading 961def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>; 962def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>; 963 964/// Word Swap Bytes Within Halfwords 965def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 966 967/// No operation 968let addr=0 in 969 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 970 971// FrameIndexes are legalized when they are operands from load/store 972// instructions. The same not happens for stack address copies, so an 973// add op with mem ComplexPattern is used and the stack address copy 974// can be matched. It's similar to Sparc LEA_ADDRi 975def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 976 977// MADD*/MSUB* 978def MADD : MArithR<0, "madd", MipsMAdd, 1>; 979def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 980def MSUB : MArithR<4, "msub", MipsMSub>; 981def MSUBU : MArithR<5, "msubu", MipsMSubu>; 982 983def RDHWR : ReadHardware<CPURegs, HWRegs>; 984 985def EXT : ExtBase<0, "ext", CPURegs>; 986def INS : InsBase<4, "ins", CPURegs>; 987 988/// Move Control Registers From/To CPU Registers 989def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 990 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 991def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 992 993def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 994 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 995def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 996 997def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 998 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 999def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 1000 1001def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 1002 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 1003def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 1004 1005//===----------------------------------------------------------------------===// 1006// Instruction aliases 1007//===----------------------------------------------------------------------===// 1008def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1009def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1010def : InstAlias<"addu $rs,$rt,$imm", 1011 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1012def : InstAlias<"add $rs,$rt,$imm", 1013 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1014def : InstAlias<"and $rs,$rt,$imm", 1015 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1016def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1017def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1018def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1019def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1020def : InstAlias<"slt $rs,$rt,$imm", 1021 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1022def : InstAlias<"xor $rs,$rt,$imm", 1023 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1024 1025//===----------------------------------------------------------------------===// 1026// Assembler Pseudo Instructions 1027//===----------------------------------------------------------------------===// 1028 1029class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 1030 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 1031 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1032def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 1033 1034class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 1035 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 1036 !strconcat(instr_asm, "\t$rt, $addr")> ; 1037def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 1038 1039class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 1040 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 1041 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1042def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 1043 1044 1045 1046//===----------------------------------------------------------------------===// 1047// Arbitrary patterns that map to one or more instructions 1048//===----------------------------------------------------------------------===// 1049 1050// Small immediates 1051def : MipsPat<(i32 immSExt16:$in), 1052 (ADDiu ZERO, imm:$in)>; 1053def : MipsPat<(i32 immZExt16:$in), 1054 (ORi ZERO, imm:$in)>; 1055def : MipsPat<(i32 immLow16Zero:$in), 1056 (LUi (HI16 imm:$in))>; 1057 1058// Arbitrary immediates 1059def : MipsPat<(i32 imm:$imm), 1060 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1061 1062// Carry MipsPatterns 1063def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1064 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1065def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1066 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1067def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1068 (ADDiu CPURegs:$src, imm:$imm)>; 1069 1070// Call 1071def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1072 (JAL tglobaladdr:$dst)>; 1073def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1074 (JAL texternalsym:$dst)>; 1075//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1076// (JALR CPURegs:$dst)>; 1077 1078// Tail call 1079def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1080 (TAILCALL tglobaladdr:$dst)>; 1081def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1082 (TAILCALL texternalsym:$dst)>; 1083// hi/lo relocs 1084def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1085def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1086def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1087def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1088def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1089def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1090 1091def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1092def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1093def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1094def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1095def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1096def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1097 1098def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1099 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1100def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1101 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1102def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1103 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1104def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1105 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1106def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1107 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1108 1109// gp_rel relocs 1110def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1111 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1112def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1113 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1114 1115// wrapper_pic 1116class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1117 MipsPat<(MipsWrapper RC:$gp, node:$in), 1118 (ADDiuOp RC:$gp, node:$in)>; 1119 1120def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1121def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1122def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1123def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1124def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1125def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1126 1127// Mips does not have "not", so we expand our way 1128def : MipsPat<(not CPURegs:$in), 1129 (NOR CPURegs:$in, ZERO)>; 1130 1131// extended loads 1132let Predicates = [NotN64, HasStdEnc] in { 1133 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1134 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1135 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1136} 1137let Predicates = [IsN64, HasStdEnc] in { 1138 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1139 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1140 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1141} 1142 1143// peepholes 1144let Predicates = [NotN64, HasStdEnc] in { 1145 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1146} 1147let Predicates = [IsN64, HasStdEnc] in { 1148 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1149} 1150 1151// brcond patterns 1152multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1153 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1154 Instruction SLTiuOp, Register ZEROReg> { 1155def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1156 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1157def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1158 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1159 1160def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1161 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1162def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1163 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1164def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1165 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1166def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1167 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1168 1169def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1170 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1171def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1172 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1173 1174def : MipsPat<(brcond RC:$cond, bb:$dst), 1175 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1176} 1177 1178defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1179 1180// setcc patterns 1181multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1182 Instruction SLTuOp, Register ZEROReg> { 1183 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1184 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1185 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1186 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1187} 1188 1189multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1190 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1191 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1192 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1193 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1194} 1195 1196multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1197 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1198 (SLTOp RC:$rhs, RC:$lhs)>; 1199 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1200 (SLTuOp RC:$rhs, RC:$lhs)>; 1201} 1202 1203multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1204 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1205 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1206 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1207 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1208} 1209 1210multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1211 Instruction SLTiuOp> { 1212 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1213 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1214 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1215 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1216} 1217 1218defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1219defm : SetlePats<CPURegs, SLT, SLTu>; 1220defm : SetgtPats<CPURegs, SLT, SLTu>; 1221defm : SetgePats<CPURegs, SLT, SLTu>; 1222defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1223 1224// bswap pattern 1225def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1226 1227//===----------------------------------------------------------------------===// 1228// Floating Point Support 1229//===----------------------------------------------------------------------===// 1230 1231include "MipsInstrFPU.td" 1232include "Mips64InstrInfo.td" 1233include "MipsCondMov.td" 1234 1235// 1236// Mips16 1237 1238include "Mips16InstrFormats.td" 1239include "Mips16InstrInfo.td" 1240 1241// DSP 1242include "MipsDSPInstrFormats.td" 1243include "MipsDSPInstrInfo.td" 1244 1245