MipsInstrInfo.td revision 94fcfaf3a9f1179edb3b8053fe7b23eab6fb83bb
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 76 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 77 78// These are target-independent nodes, but have target-specific formats. 79def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 80 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 81def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 82 [SDNPHasChain, SDNPSideEffect, 83 SDNPOptInGlue, SDNPOutGlue]>; 84 85// MAdd*/MSub* nodes 86def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 87 [SDNPOptInGlue, SDNPOutGlue]>; 88def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 89 [SDNPOptInGlue, SDNPOutGlue]>; 90def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 91 [SDNPOptInGlue, SDNPOutGlue]>; 92def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 93 [SDNPOptInGlue, SDNPOutGlue]>; 94 95// DivRem(u) nodes 96def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 97 [SDNPOutGlue]>; 98def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 99 [SDNPOutGlue]>; 100 101// Target constant nodes that are not part of any isel patterns and remain 102// unchanged can cause instructions with illegal operands to be emitted. 103// Wrapper node patterns give the instruction selector a chance to replace 104// target constant nodes that would otherwise remain unchanged with ADDiu 105// nodes. Without these wrapper node patterns, the following conditional move 106// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 107// compiled: 108// movn %got(d)($gp), %got(c)($gp), $4 109// This instruction is illegal since movn can take only register operands. 110 111def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 112 113def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 114 115def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 116def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 117 118def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 120def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 122def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 124def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 126def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 128def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 132def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134 135//===----------------------------------------------------------------------===// 136// Mips Instruction Predicate Definitions. 137//===----------------------------------------------------------------------===// 138def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 139 AssemblerPredicate<"FeatureSEInReg">; 140def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 141 AssemblerPredicate<"FeatureBitCount">; 142def HasSwap : Predicate<"Subtarget.hasSwap()">, 143 AssemblerPredicate<"FeatureSwap">; 144def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 145 AssemblerPredicate<"FeatureCondMov">; 146def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 147 AssemblerPredicate<"FeatureFPIdx">; 148def HasMips32 : Predicate<"Subtarget.hasMips32()">, 149 AssemblerPredicate<"FeatureMips32">; 150def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 151 AssemblerPredicate<"FeatureMips32r2">; 152def HasMips64 : Predicate<"Subtarget.hasMips64()">, 153 AssemblerPredicate<"FeatureMips64">; 154def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 155 AssemblerPredicate<"!FeatureMips64">; 156def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 157 AssemblerPredicate<"FeatureMips64r2">; 158def IsN64 : Predicate<"Subtarget.isABI_N64()">, 159 AssemblerPredicate<"FeatureN64">; 160def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 161 AssemblerPredicate<"!FeatureN64">; 162def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 163 AssemblerPredicate<"FeatureMips16">; 164def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 165 AssemblerPredicate<"FeatureMips32">; 166def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 167 AssemblerPredicate<"FeatureMips32">; 168def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 169 AssemblerPredicate<"FeatureMips32">; 170def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 171 AssemblerPredicate<"!FeatureMips16">; 172 173class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 174 let Predicates = [HasStdEnc]; 175} 176 177class IsCommutable { 178 bit isCommutable = 1; 179} 180 181class IsBranch { 182 bit isBranch = 1; 183} 184 185class IsReturn { 186 bit isReturn = 1; 187} 188 189class IsCall { 190 bit isCall = 1; 191} 192 193class IsTailCall { 194 bit isCall = 1; 195 bit isTerminator = 1; 196 bit isReturn = 1; 197 bit isBarrier = 1; 198 bit hasExtraSrcRegAllocReq = 1; 199 bit isCodeGenOnly = 1; 200} 201 202class IsAsCheapAsAMove { 203 bit isAsCheapAsAMove = 1; 204} 205 206class NeverHasSideEffects { 207 bit neverHasSideEffects = 1; 208} 209 210//===----------------------------------------------------------------------===// 211// Instruction format superclass 212//===----------------------------------------------------------------------===// 213 214include "MipsInstrFormats.td" 215 216//===----------------------------------------------------------------------===// 217// Mips Operand, Complex Patterns and Transformations Definitions. 218//===----------------------------------------------------------------------===// 219 220// Instruction operand types 221def jmptarget : Operand<OtherVT> { 222 let EncoderMethod = "getJumpTargetOpValue"; 223} 224def brtarget : Operand<OtherVT> { 225 let EncoderMethod = "getBranchTargetOpValue"; 226 let OperandType = "OPERAND_PCREL"; 227 let DecoderMethod = "DecodeBranchTarget"; 228} 229def calltarget : Operand<iPTR> { 230 let EncoderMethod = "getJumpTargetOpValue"; 231} 232def calltarget64: Operand<i64>; 233def simm16 : Operand<i32> { 234 let DecoderMethod= "DecodeSimm16"; 235} 236 237def simm20 : Operand<i32> { 238} 239 240def simm16_64 : Operand<i64>; 241def shamt : Operand<i32>; 242 243// Unsigned Operand 244def uimm16 : Operand<i32> { 245 let PrintMethod = "printUnsignedImm"; 246} 247 248def MipsMemAsmOperand : AsmOperandClass { 249 let Name = "Mem"; 250 let ParserMethod = "parseMemOperand"; 251} 252 253// Address operand 254def mem : Operand<i32> { 255 let PrintMethod = "printMemOperand"; 256 let MIOperandInfo = (ops CPURegs, simm16); 257 let EncoderMethod = "getMemEncoding"; 258 let ParserMatchClass = MipsMemAsmOperand; 259 let OperandType = "OPERAND_MEMORY"; 260} 261 262def mem64 : Operand<i64> { 263 let PrintMethod = "printMemOperand"; 264 let MIOperandInfo = (ops CPU64Regs, simm16_64); 265 let EncoderMethod = "getMemEncoding"; 266 let ParserMatchClass = MipsMemAsmOperand; 267 let OperandType = "OPERAND_MEMORY"; 268} 269 270def mem_ea : Operand<i32> { 271 let PrintMethod = "printMemOperandEA"; 272 let MIOperandInfo = (ops CPURegs, simm16); 273 let EncoderMethod = "getMemEncoding"; 274 let OperandType = "OPERAND_MEMORY"; 275} 276 277def mem_ea_64 : Operand<i64> { 278 let PrintMethod = "printMemOperandEA"; 279 let MIOperandInfo = (ops CPU64Regs, simm16_64); 280 let EncoderMethod = "getMemEncoding"; 281 let OperandType = "OPERAND_MEMORY"; 282} 283 284// size operand of ext instruction 285def size_ext : Operand<i32> { 286 let EncoderMethod = "getSizeExtEncoding"; 287 let DecoderMethod = "DecodeExtSize"; 288} 289 290// size operand of ins instruction 291def size_ins : Operand<i32> { 292 let EncoderMethod = "getSizeInsEncoding"; 293 let DecoderMethod = "DecodeInsSize"; 294} 295 296// Transformation Function - get the lower 16 bits. 297def LO16 : SDNodeXForm<imm, [{ 298 return getImm(N, N->getZExtValue() & 0xFFFF); 299}]>; 300 301// Transformation Function - get the higher 16 bits. 302def HI16 : SDNodeXForm<imm, [{ 303 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 304}]>; 305 306// Plus 1. 307def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 308 309// Node immediate fits as 16-bit sign extended on target immediate. 310// e.g. addi, andi 311def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 312 313// Node immediate fits as 16-bit sign extended on target immediate. 314// e.g. addi, andi 315def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 316 317// Node immediate fits as 15-bit sign extended on target immediate. 318// e.g. addi, andi 319def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 320 321// Node immediate fits as 16-bit zero extended on target immediate. 322// The LO16 param means that only the lower 16 bits of the node 323// immediate are caught. 324// e.g. addiu, sltiu 325def immZExt16 : PatLeaf<(imm), [{ 326 if (N->getValueType(0) == MVT::i32) 327 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 328 else 329 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 330}], LO16>; 331 332// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 333def immLow16Zero : PatLeaf<(imm), [{ 334 int64_t Val = N->getSExtValue(); 335 return isInt<32>(Val) && !(Val & 0xffff); 336}]>; 337 338// shamt field must fit in 5 bits. 339def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 340 341// True if (N + 1) fits in 16-bit field. 342def immSExt16Plus1 : PatLeaf<(imm), [{ 343 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 344}]>; 345 346// Mips Address Mode! SDNode frameindex could possibily be a match 347// since load and store instructions from stack used it. 348def addr : 349 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 350 351def addrRegImm : 352 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 353 354def addrDefault : 355 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 356 357//===----------------------------------------------------------------------===// 358// Instructions specific format 359//===----------------------------------------------------------------------===// 360 361// Arithmetic and logical instructions with 3 register operands. 362class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 363 InstrItinClass Itin = NoItinerary, 364 SDPatternOperator OpNode = null_frag>: 365 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 366 !strconcat(opstr, "\t$rd, $rs, $rt"), 367 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { 368 let isCommutable = isComm; 369 let isReMaterializable = 1; 370 string BaseOpcode; 371 string Arch; 372} 373 374// Arithmetic and logical instructions with 2 register operands. 375class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 376 SDPatternOperator imm_type = null_frag, 377 SDPatternOperator OpNode = null_frag> : 378 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 379 !strconcat(opstr, "\t$rt, $rs, $imm16"), 380 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> { 381 let isReMaterializable = 1; 382} 383 384// Arithmetic Multiply ADD/SUB 385class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> : 386 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 387 !strconcat(opstr, "\t$rs, $rt"), 388 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> { 389 let Defs = [HI, LO]; 390 let Uses = [HI, LO]; 391 let isCommutable = isComm; 392} 393 394// Logical 395class LogicNOR<string opstr, RegisterOperand RC>: 396 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 397 !strconcat(opstr, "\t$rd, $rs, $rt"), 398 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 399 let isCommutable = 1; 400} 401 402// Shifts 403class shift_rotate_imm<string opstr, Operand ImmOpnd, 404 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 405 SDPatternOperator PF = null_frag> : 406 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 407 !strconcat(opstr, "\t$rd, $rt, $shamt"), 408 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 409 410class shift_rotate_reg<string opstr, RegisterOperand RC, 411 SDPatternOperator OpNode = null_frag>: 412 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 413 !strconcat(opstr, "\t$rd, $rt, $rs"), 414 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>; 415 416// Load Upper Imediate 417class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 418 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 419 [], IIAlu, FrmI>, IsAsCheapAsAMove { 420 let neverHasSideEffects = 1; 421 let isReMaterializable = 1; 422} 423 424class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 425 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 426 bits<21> addr; 427 let Inst{25-21} = addr{20-16}; 428 let Inst{15-0} = addr{15-0}; 429 let DecoderMethod = "DecodeMem"; 430} 431 432// Memory Load/Store 433class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 434 Operand MemOpnd> : 435 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 436 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 437 let DecoderMethod = "DecodeMem"; 438 let canFoldAsLoad = 1; 439} 440 441class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 442 Operand MemOpnd> : 443 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 444 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 445 let DecoderMethod = "DecodeMem"; 446} 447 448multiclass LoadM<string opstr, RegisterClass RC, 449 SDPatternOperator OpNode = null_frag> { 450 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 451 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 452 let DecoderNamespace = "Mips64"; 453 let isCodeGenOnly = 1; 454 } 455} 456 457multiclass StoreM<string opstr, RegisterClass RC, 458 SDPatternOperator OpNode = null_frag> { 459 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 460 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 461 let DecoderNamespace = "Mips64"; 462 let isCodeGenOnly = 1; 463 } 464} 465 466// Load/Store Left/Right 467let canFoldAsLoad = 1 in 468class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 469 Operand MemOpnd> : 470 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 471 !strconcat(opstr, "\t$rt, $addr"), 472 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 473 let DecoderMethod = "DecodeMem"; 474 string Constraints = "$src = $rt"; 475} 476 477class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 478 Operand MemOpnd>: 479 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 480 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 481 let DecoderMethod = "DecodeMem"; 482} 483 484multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 485 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 486 Requires<[NotN64, HasStdEnc]>; 487 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 488 Requires<[IsN64, HasStdEnc]> { 489 let DecoderNamespace = "Mips64"; 490 let isCodeGenOnly = 1; 491 } 492} 493 494multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 495 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 496 Requires<[NotN64, HasStdEnc]>; 497 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 498 Requires<[IsN64, HasStdEnc]> { 499 let DecoderNamespace = "Mips64"; 500 let isCodeGenOnly = 1; 501 } 502} 503 504// Conditional Branch 505class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 506 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 507 !strconcat(opstr, "\t$rs, $rt, $offset"), 508 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 509 FrmI> { 510 let isBranch = 1; 511 let isTerminator = 1; 512 let hasDelaySlot = 1; 513 let Defs = [AT]; 514} 515 516class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 517 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 518 !strconcat(opstr, "\t$rs, $offset"), 519 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 520 let isBranch = 1; 521 let isTerminator = 1; 522 let hasDelaySlot = 1; 523 let Defs = [AT]; 524} 525 526// SetCC 527class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 528 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 529 !strconcat(opstr, "\t$rd, $rs, $rt"), 530 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 531 532class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 533 RegisterClass RC>: 534 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 535 !strconcat(opstr, "\t$rt, $rs, $imm16"), 536 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 537 IIAlu, FrmI>; 538 539// Jump 540class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 541 SDPatternOperator targetoperator> : 542 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 543 [(operator targetoperator:$target)], IIBranch, FrmJ> { 544 let isTerminator=1; 545 let isBarrier=1; 546 let hasDelaySlot = 1; 547 let DecoderMethod = "DecodeJumpTarget"; 548 let Defs = [AT]; 549} 550 551// Unconditional branch 552class UncondBranch<string opstr> : 553 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 554 [(br bb:$offset)], IIBranch, FrmI> { 555 let isBranch = 1; 556 let isTerminator = 1; 557 let isBarrier = 1; 558 let hasDelaySlot = 1; 559 let Predicates = [RelocPIC, HasStdEnc]; 560 let Defs = [AT]; 561} 562 563// Base class for indirect branch and return instruction classes. 564let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 565class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 566 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 567 568// Indirect branch 569class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 570 let isBranch = 1; 571 let isIndirectBranch = 1; 572} 573 574// Return instruction 575class RetBase<RegisterClass RC>: JumpFR<RC> { 576 let isReturn = 1; 577 let isCodeGenOnly = 1; 578 let hasCtrlDep = 1; 579 let hasExtraSrcRegAllocReq = 1; 580} 581 582// Jump and Link (Call) 583let isCall=1, hasDelaySlot=1, Defs = [RA] in { 584 class JumpLink<string opstr> : 585 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 586 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 587 let DecoderMethod = "DecodeJumpTarget"; 588 } 589 590 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 591 Register RetReg>: 592 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 593 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 594 595 class JumpLinkReg<string opstr, RegisterClass RC>: 596 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 597 [], IIBranch, FrmR>; 598 599 class BGEZAL_FT<string opstr, RegisterOperand RO> : 600 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 601 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 602 603} 604 605class BAL_FT : 606 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 607 let isBranch = 1; 608 let isTerminator = 1; 609 let isBarrier = 1; 610 let hasDelaySlot = 1; 611 let Defs = [RA]; 612} 613 614// Sync 615let hasSideEffects = 1 in 616class SYNC_FT : 617 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 618 NoItinerary, FrmOther>; 619 620// Mul, Div 621class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 622 list<Register> DefRegs> : 623 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 624 itin, FrmR> { 625 let isCommutable = 1; 626 let Defs = DefRegs; 627 let neverHasSideEffects = 1; 628} 629 630class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO, 631 list<Register> DefRegs> : 632 InstSE<(outs), (ins RO:$rs, RO:$rt), 633 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin, 634 FrmR> { 635 let Defs = DefRegs; 636} 637 638// Move from Hi/Lo 639class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 640 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 641 let Uses = UseRegs; 642 let neverHasSideEffects = 1; 643} 644 645class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 646 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 647 let Defs = DefRegs; 648 let neverHasSideEffects = 1; 649} 650 651class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 652 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 653 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 654 let isCodeGenOnly = 1; 655 let DecoderMethod = "DecodeMem"; 656} 657 658// Count Leading Ones/Zeros in Word 659class CountLeading0<string opstr, RegisterOperand RO>: 660 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 661 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 662 Requires<[HasBitCount, HasStdEnc]>; 663 664class CountLeading1<string opstr, RegisterOperand RO>: 665 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 666 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 667 Requires<[HasBitCount, HasStdEnc]>; 668 669 670// Sign Extend in Register. 671class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 672 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 673 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 674 let Predicates = [HasSEInReg, HasStdEnc]; 675} 676 677// Subword Swap 678class SubwordSwap<string opstr, RegisterOperand RO>: 679 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 680 NoItinerary, FrmR> { 681 let Predicates = [HasSwap, HasStdEnc]; 682 let neverHasSideEffects = 1; 683} 684 685// Read Hardware 686class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 687 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 688 IIAlu, FrmR>; 689 690// Ext and Ins 691class ExtBase<string opstr, RegisterOperand RO>: 692 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 693 !strconcat(opstr, " $rt, $rs, $pos, $size"), 694 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 695 FrmR> { 696 let Predicates = [HasMips32r2, HasStdEnc]; 697} 698 699class InsBase<string opstr, RegisterOperand RO>: 700 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 701 !strconcat(opstr, " $rt, $rs, $pos, $size"), 702 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 703 NoItinerary, FrmR> { 704 let Predicates = [HasMips32r2, HasStdEnc]; 705 let Constraints = "$src = $rt"; 706} 707 708// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 709class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 710 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 711 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 712 713multiclass Atomic2Ops32<PatFrag Op> { 714 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 715 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 716 Requires<[IsN64, HasStdEnc]> { 717 let DecoderNamespace = "Mips64"; 718 } 719} 720 721// Atomic Compare & Swap. 722class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 723 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 724 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 725 726multiclass AtomicCmpSwap32<PatFrag Op> { 727 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 728 Requires<[NotN64, HasStdEnc]>; 729 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 730 Requires<[IsN64, HasStdEnc]> { 731 let DecoderNamespace = "Mips64"; 732 } 733} 734 735class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 736 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 737 [], NoItinerary, FrmI> { 738 let DecoderMethod = "DecodeMem"; 739 let mayLoad = 1; 740} 741 742class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 743 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 744 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 745 let DecoderMethod = "DecodeMem"; 746 let mayStore = 1; 747 let Constraints = "$rt = $dst"; 748} 749 750class MFC3OP<dag outs, dag ins, string asmstr> : 751 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 752 753//===----------------------------------------------------------------------===// 754// Pseudo instructions 755//===----------------------------------------------------------------------===// 756 757// Return RA. 758let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 759def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 760 761let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 762def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 763 [(callseq_start timm:$amt)]>; 764def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 765 [(callseq_end timm:$amt1, timm:$amt2)]>; 766} 767 768let usesCustomInserter = 1 in { 769 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 770 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 771 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 772 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 773 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 774 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 775 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 776 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 777 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 778 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 779 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 780 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 781 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 782 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 783 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 784 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 785 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 786 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 787 788 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 789 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 790 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 791 792 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 793 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 794 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 795} 796 797//===----------------------------------------------------------------------===// 798// Instruction definition 799//===----------------------------------------------------------------------===// 800//===----------------------------------------------------------------------===// 801// MipsI Instructions 802//===----------------------------------------------------------------------===// 803 804/// Arithmetic Instructions (ALU Immediate) 805def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 806 ADDI_FM<0x9>, IsAsCheapAsAMove; 807def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 808def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 809def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 810def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 811 ADDI_FM<0xc>; 812def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 813 ADDI_FM<0xd>; 814def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 815 ADDI_FM<0xe>; 816def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 817 818/// Arithmetic Instructions (3-Operand, R-Type) 819def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>; 820def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 821def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 822def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 823def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 824def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 825def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 826def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 827def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 828def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 829def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 830 831/// Shift Instructions 832def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 833 SRA_FM<0, 0>; 834def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 835 SRA_FM<2, 0>; 836def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 837 SRA_FM<3, 0>; 838def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 839def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 840def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 841 842// Rotate Instructions 843let Predicates = [HasMips32r2, HasStdEnc] in { 844 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>, 845 SRA_FM<2, 1>; 846 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>; 847} 848 849/// Load and Store Instructions 850/// aligned 851defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 852defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; 853defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; 854defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 855defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; 856defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 857defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 858defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 859 860/// load/store left/right 861defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 862defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 863defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 864defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 865 866def SYNC : SYNC_FT, SYNC_FM; 867 868/// Load-linked, Store-conditional 869let Predicates = [NotN64, HasStdEnc] in { 870 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 871 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 872} 873 874let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 875 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 876 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 877} 878 879/// Jump and Branch Instructions 880def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 881 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 882def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 883def B : UncondBranch<"b">, B_FM; 884def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 885def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 886def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 887def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 888def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 889def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 890 891def BAL_BR: BAL_FT, BAL_FM; 892 893def JAL : JumpLink<"jal">, FJ<3>; 894def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 895def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 896def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 897def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 898def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 899def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 900 901def RET : RetBase<CPURegs>, MTLO_FM<8>; 902 903// Exception handling related node and instructions. 904// The conversion sequence is: 905// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 906// MIPSeh_return -> (stack change + indirect branch) 907// 908// MIPSeh_return takes the place of regular return instruction 909// but takes two arguments (V1, V0) which are used for storing 910// the offset and return address respectively. 911def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 912 913def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 914 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 915 916let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 917 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 918 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 919 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 920 CPU64Regs:$dst), 921 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 922} 923 924/// Multiply and Divide Instructions. 925def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>; 926def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>; 927def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>, 928 MULT_FM<0, 0x1a>; 929def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>, 930 MULT_FM<0, 0x1b>; 931 932def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 933def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 934def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 935def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 936 937/// Sign Ext In Register Instructions. 938def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 939def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 940 941/// Count Leading 942def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 943def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 944 945/// Word Swap Bytes Within Halfwords 946def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 947 948/// No operation. 949def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 950 951// FrameIndexes are legalized when they are operands from load/store 952// instructions. The same not happens for stack address copies, so an 953// add op with mem ComplexPattern is used and the stack address copy 954// can be matched. It's similar to Sparc LEA_ADDRi 955def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 956 957// MADD*/MSUB* 958def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; 959def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; 960def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; 961def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; 962 963def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 964 965def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 966def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 967 968/// Move Control Registers From/To CPU Registers 969def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 970 (ins CPURegsOpnd:$rd, uimm16:$sel), 971 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 972 973def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 974 (ins CPURegsOpnd:$rt), 975 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 976 977def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 978 (ins CPURegsOpnd:$rd, uimm16:$sel), 979 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 980 981def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 982 (ins CPURegsOpnd:$rt), 983 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 984 985//===----------------------------------------------------------------------===// 986// Instruction aliases 987//===----------------------------------------------------------------------===// 988def : InstAlias<"move $dst, $src", 989 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 990 Requires<[NotMips64]>; 991def : InstAlias<"move $dst, $src", 992 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 993 Requires<[NotMips64]>; 994def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 995def : InstAlias<"addu $rs, $rt, $imm", 996 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 997def : InstAlias<"add $rs, $rt, $imm", 998 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 999def : InstAlias<"and $rs, $rt, $imm", 1000 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1001def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1002 Requires<[NotMips64]>; 1003def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1004def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1005def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1006 Requires<[NotMips64]>; 1007def : InstAlias<"not $rt, $rs", 1008 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1009def : InstAlias<"neg $rt, $rs", 1010 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1011def : InstAlias<"negu $rt, $rs", 1012 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1013def : InstAlias<"slt $rs, $rt, $imm", 1014 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1015def : InstAlias<"xor $rs, $rt, $imm", 1016 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 1017 Requires<[NotMips64]>; 1018def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1019def : InstAlias<"mfc0 $rt, $rd", 1020 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1021def : InstAlias<"mtc0 $rt, $rd", 1022 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1023def : InstAlias<"mfc2 $rt, $rd", 1024 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1025def : InstAlias<"mtc2 $rt, $rd", 1026 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1027 1028//===----------------------------------------------------------------------===// 1029// Assembler Pseudo Instructions 1030//===----------------------------------------------------------------------===// 1031 1032class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1033 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1034 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1035def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1036 1037class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1038 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1039 !strconcat(instr_asm, "\t$rt, $addr")> ; 1040def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1041 1042class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1043 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1044 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1045def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1046 1047 1048 1049//===----------------------------------------------------------------------===// 1050// Arbitrary patterns that map to one or more instructions 1051//===----------------------------------------------------------------------===// 1052 1053// Small immediates 1054def : MipsPat<(i32 immSExt16:$in), 1055 (ADDiu ZERO, imm:$in)>; 1056def : MipsPat<(i32 immZExt16:$in), 1057 (ORi ZERO, imm:$in)>; 1058def : MipsPat<(i32 immLow16Zero:$in), 1059 (LUi (HI16 imm:$in))>; 1060 1061// Arbitrary immediates 1062def : MipsPat<(i32 imm:$imm), 1063 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1064 1065// Carry MipsPatterns 1066def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1067 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1068def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1069 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1070def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1071 (ADDiu CPURegs:$src, imm:$imm)>; 1072 1073// Call 1074def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1075 (JAL tglobaladdr:$dst)>; 1076def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1077 (JAL texternalsym:$dst)>; 1078//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1079// (JALR CPURegs:$dst)>; 1080 1081// Tail call 1082def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1083 (TAILCALL tglobaladdr:$dst)>; 1084def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1085 (TAILCALL texternalsym:$dst)>; 1086// hi/lo relocs 1087def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1088def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1089def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1090def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1091def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1092def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1093 1094def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1095def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1096def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1097def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1098def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1099def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1100 1101def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1102 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1103def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1104 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1105def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1106 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1107def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1108 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1109def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1110 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1111 1112// gp_rel relocs 1113def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1114 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1115def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1116 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1117 1118// wrapper_pic 1119class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1120 MipsPat<(MipsWrapper RC:$gp, node:$in), 1121 (ADDiuOp RC:$gp, node:$in)>; 1122 1123def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1124def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1125def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1126def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1127def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1128def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1129 1130// Mips does not have "not", so we expand our way 1131def : MipsPat<(not CPURegs:$in), 1132 (NOR CPURegsOpnd:$in, ZERO)>; 1133 1134// extended loads 1135let Predicates = [NotN64, HasStdEnc] in { 1136 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1137 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1138 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1139} 1140let Predicates = [IsN64, HasStdEnc] in { 1141 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1142 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1143 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1144} 1145 1146// peepholes 1147let Predicates = [NotN64, HasStdEnc] in { 1148 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1149} 1150let Predicates = [IsN64, HasStdEnc] in { 1151 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1152} 1153 1154// brcond patterns 1155multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1156 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1157 Instruction SLTiuOp, Register ZEROReg> { 1158def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1159 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1160def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1161 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1162 1163def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1164 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1165def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1166 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1167def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1168 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1169def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1170 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1171 1172def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1173 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1174def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1175 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1176 1177def : MipsPat<(brcond RC:$cond, bb:$dst), 1178 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1179} 1180 1181defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1182 1183// setcc patterns 1184multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1185 Instruction SLTuOp, Register ZEROReg> { 1186 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1187 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1188 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1189 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1190} 1191 1192multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1193 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1194 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1195 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1196 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1197} 1198 1199multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1200 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1201 (SLTOp RC:$rhs, RC:$lhs)>; 1202 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1203 (SLTuOp RC:$rhs, RC:$lhs)>; 1204} 1205 1206multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1207 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1208 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1209 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1210 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1211} 1212 1213multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1214 Instruction SLTiuOp> { 1215 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1216 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1217 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1218 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1219} 1220 1221defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1222defm : SetlePats<CPURegs, SLT, SLTu>; 1223defm : SetgtPats<CPURegs, SLT, SLTu>; 1224defm : SetgePats<CPURegs, SLT, SLTu>; 1225defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1226 1227// bswap pattern 1228def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1229 1230//===----------------------------------------------------------------------===// 1231// Floating Point Support 1232//===----------------------------------------------------------------------===// 1233 1234include "MipsInstrFPU.td" 1235include "Mips64InstrInfo.td" 1236include "MipsCondMov.td" 1237 1238// 1239// Mips16 1240 1241include "Mips16InstrFormats.td" 1242include "Mips16InstrInfo.td" 1243 1244// DSP 1245include "MipsDSPInstrFormats.td" 1246include "MipsDSPInstrInfo.td" 1247 1248