MipsInstrInfo.td revision 997c5dead83fc237280888696e1fa719563fc7f1
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 36def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 37 38def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 39 40def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 41 42def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 44def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 46 SDTCisSameAs<0, 4>]>; 47 48def SDTMipsLoadLR : SDTypeProfile<1, 2, 49 [SDTCisInt<0>, SDTCisPtrTy<1>, 50 SDTCisSameAs<0, 2>]>; 51 52// Call 53def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 55 SDNPVariadic]>; 56 57// Tail call 58def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 60 61// Hi and Lo nodes are used to handle global addresses. Used on 62// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 63// static model. (nothing to do with Mips Registers Hi and Lo) 64def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 65def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 66def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 67 68// TlsGd node is used to handle General Dynamic TLS 69def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 70 71// TprelHi and TprelLo nodes are used to handle Local Exec TLS 72def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 73def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 74 75// Thread pointer 76def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 77 78// Return 79def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 81 82// These are target-independent nodes, but have target-specific formats. 83def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 85def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 86 [SDNPHasChain, SDNPSideEffect, 87 SDNPOptInGlue, SDNPOutGlue]>; 88 89// Node used to extract integer from LO/HI register. 90def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, 186 AssemblerPredicate<"FeatureMicroMips">; 187def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, 188 AssemblerPredicate<"!FeatureMicroMips">; 189def IsLE : Predicate<"Subtarget.isLittle()">; 190def IsBE : Predicate<"!Subtarget.isLittle()">; 191 192class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 193 let Predicates = [HasStdEnc]; 194} 195 196class IsCommutable { 197 bit isCommutable = 1; 198} 199 200class IsBranch { 201 bit isBranch = 1; 202} 203 204class IsReturn { 205 bit isReturn = 1; 206} 207 208class IsCall { 209 bit isCall = 1; 210} 211 212class IsTailCall { 213 bit isCall = 1; 214 bit isTerminator = 1; 215 bit isReturn = 1; 216 bit isBarrier = 1; 217 bit hasExtraSrcRegAllocReq = 1; 218 bit isCodeGenOnly = 1; 219} 220 221class IsAsCheapAsAMove { 222 bit isAsCheapAsAMove = 1; 223} 224 225class NeverHasSideEffects { 226 bit neverHasSideEffects = 1; 227} 228 229//===----------------------------------------------------------------------===// 230// Instruction format superclass 231//===----------------------------------------------------------------------===// 232 233include "MipsInstrFormats.td" 234 235//===----------------------------------------------------------------------===// 236// Mips Operand, Complex Patterns and Transformations Definitions. 237//===----------------------------------------------------------------------===// 238 239// Instruction operand types 240def jmptarget : Operand<OtherVT> { 241 let EncoderMethod = "getJumpTargetOpValue"; 242} 243def brtarget : Operand<OtherVT> { 244 let EncoderMethod = "getBranchTargetOpValue"; 245 let OperandType = "OPERAND_PCREL"; 246 let DecoderMethod = "DecodeBranchTarget"; 247} 248def calltarget : Operand<iPTR> { 249 let EncoderMethod = "getJumpTargetOpValue"; 250} 251 252def simm16 : Operand<i32> { 253 let DecoderMethod= "DecodeSimm16"; 254} 255 256def simm20 : Operand<i32> { 257} 258 259def uimm20 : Operand<i32> { 260} 261 262def uimm10 : Operand<i32> { 263} 264 265def simm16_64 : Operand<i64>; 266def shamt : Operand<i32>; 267 268// Unsigned Operand 269def uimm5 : Operand<i32> { 270 let PrintMethod = "printUnsignedImm"; 271} 272 273def uimm16 : Operand<i32> { 274 let PrintMethod = "printUnsignedImm"; 275} 276 277def MipsMemAsmOperand : AsmOperandClass { 278 let Name = "Mem"; 279 let ParserMethod = "parseMemOperand"; 280} 281 282def PtrRegAsmOperand : AsmOperandClass { 283 let Name = "PtrReg"; 284 let ParserMethod = "parsePtrReg"; 285} 286 287// Address operand 288def mem : Operand<iPTR> { 289 let PrintMethod = "printMemOperand"; 290 let MIOperandInfo = (ops ptr_rc, simm16); 291 let EncoderMethod = "getMemEncoding"; 292 let ParserMatchClass = MipsMemAsmOperand; 293 let OperandType = "OPERAND_MEMORY"; 294} 295 296def mem_ea : Operand<iPTR> { 297 let PrintMethod = "printMemOperandEA"; 298 let MIOperandInfo = (ops ptr_rc, simm16); 299 let EncoderMethod = "getMemEncoding"; 300 let OperandType = "OPERAND_MEMORY"; 301} 302 303def PtrRC : Operand<iPTR> { 304 let MIOperandInfo = (ops ptr_rc); 305 let DecoderMethod = "DecodePtrRegisterClass"; 306 let ParserMatchClass = PtrRegAsmOperand; 307} 308 309// size operand of ext instruction 310def size_ext : Operand<i32> { 311 let EncoderMethod = "getSizeExtEncoding"; 312 let DecoderMethod = "DecodeExtSize"; 313} 314 315// size operand of ins instruction 316def size_ins : Operand<i32> { 317 let EncoderMethod = "getSizeInsEncoding"; 318 let DecoderMethod = "DecodeInsSize"; 319} 320 321// Transformation Function - get the lower 16 bits. 322def LO16 : SDNodeXForm<imm, [{ 323 return getImm(N, N->getZExtValue() & 0xFFFF); 324}]>; 325 326// Transformation Function - get the higher 16 bits. 327def HI16 : SDNodeXForm<imm, [{ 328 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 329}]>; 330 331// Plus 1. 332def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 333 334// Node immediate fits as 16-bit sign extended on target immediate. 335// e.g. addi, andi 336def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 337 338// Node immediate fits as 16-bit sign extended on target immediate. 339// e.g. addi, andi 340def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 341 342// Node immediate fits as 15-bit sign extended on target immediate. 343// e.g. addi, andi 344def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 345 346// Node immediate fits as 16-bit zero extended on target immediate. 347// The LO16 param means that only the lower 16 bits of the node 348// immediate are caught. 349// e.g. addiu, sltiu 350def immZExt16 : PatLeaf<(imm), [{ 351 if (N->getValueType(0) == MVT::i32) 352 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 353 else 354 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 355}], LO16>; 356 357// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 358def immLow16Zero : PatLeaf<(imm), [{ 359 int64_t Val = N->getSExtValue(); 360 return isInt<32>(Val) && !(Val & 0xffff); 361}]>; 362 363// shamt field must fit in 5 bits. 364def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 365 366// True if (N + 1) fits in 16-bit field. 367def immSExt16Plus1 : PatLeaf<(imm), [{ 368 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 369}]>; 370 371// Mips Address Mode! SDNode frameindex could possibily be a match 372// since load and store instructions from stack used it. 373def addr : 374 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 375 376def addrRegImm : 377 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 378 379def addrRegReg : 380 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 381 382def addrDefault : 383 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 384 385//===----------------------------------------------------------------------===// 386// Instructions specific format 387//===----------------------------------------------------------------------===// 388 389// Arithmetic and logical instructions with 3 register operands. 390class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 391 InstrItinClass Itin = NoItinerary, 392 SDPatternOperator OpNode = null_frag>: 393 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 394 !strconcat(opstr, "\t$rd, $rs, $rt"), 395 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 396 let isCommutable = isComm; 397 let isReMaterializable = 1; 398} 399 400// Arithmetic and logical instructions with 2 register operands. 401class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 402 InstrItinClass Itin = NoItinerary, 403 SDPatternOperator imm_type = null_frag, 404 SDPatternOperator OpNode = null_frag> : 405 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 406 !strconcat(opstr, "\t$rt, $rs, $imm16"), 407 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 408 Itin, FrmI, opstr> { 409 let isReMaterializable = 1; 410 let TwoOperandAliasConstraint = "$rs = $rt"; 411} 412 413// Arithmetic Multiply ADD/SUB 414class MArithR<string opstr, bit isComm = 0> : 415 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 416 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> { 417 let Defs = [HI0, LO0]; 418 let Uses = [HI0, LO0]; 419 let isCommutable = isComm; 420} 421 422// Logical 423class LogicNOR<string opstr, RegisterOperand RO>: 424 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 425 !strconcat(opstr, "\t$rd, $rs, $rt"), 426 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> { 427 let isCommutable = 1; 428} 429 430// Shifts 431class shift_rotate_imm<string opstr, Operand ImmOpnd, 432 RegisterOperand RO, SDPatternOperator OpNode = null_frag, 433 SDPatternOperator PF = null_frag> : 434 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 435 !strconcat(opstr, "\t$rd, $rt, $shamt"), 436 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>; 437 438class shift_rotate_reg<string opstr, RegisterOperand RO, 439 SDPatternOperator OpNode = null_frag>: 440 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 441 !strconcat(opstr, "\t$rd, $rt, $rs"), 442 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>; 443 444// Load Upper Imediate 445class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 446 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 447 [], IIArith, FrmI>, IsAsCheapAsAMove { 448 let neverHasSideEffects = 1; 449 let isReMaterializable = 1; 450} 451 452// Memory Load/Store 453class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 454 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 455 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 456 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 457 let DecoderMethod = "DecodeMem"; 458 let canFoldAsLoad = 1; 459 let mayLoad = 1; 460} 461 462class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 463 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 464 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 465 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 466 let DecoderMethod = "DecodeMem"; 467 let mayStore = 1; 468} 469 470// Load/Store Left/Right 471let canFoldAsLoad = 1 in 472class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 473 InstrItinClass Itin> : 474 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 475 !strconcat(opstr, "\t$rt, $addr"), 476 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 477 let DecoderMethod = "DecodeMem"; 478 string Constraints = "$src = $rt"; 479} 480 481class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 482 InstrItinClass Itin> : 483 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 484 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 485 let DecoderMethod = "DecodeMem"; 486} 487 488// Conditional Branch 489class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> : 490 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset), 491 !strconcat(opstr, "\t$rs, $rt, $offset"), 492 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 493 FrmI> { 494 let isBranch = 1; 495 let isTerminator = 1; 496 let hasDelaySlot = 1; 497 let Defs = [AT]; 498} 499 500class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> : 501 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 502 !strconcat(opstr, "\t$rs, $offset"), 503 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 504 let isBranch = 1; 505 let isTerminator = 1; 506 let hasDelaySlot = 1; 507 let Defs = [AT]; 508} 509 510// SetCC 511class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 512 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 513 !strconcat(opstr, "\t$rd, $rs, $rt"), 514 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 515 IIslt, FrmR, opstr>; 516 517class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 518 RegisterOperand RO>: 519 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 520 !strconcat(opstr, "\t$rt, $rs, $imm16"), 521 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 522 IIslt, FrmI, opstr>; 523 524// Jump 525class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 526 SDPatternOperator targetoperator> : 527 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 528 [(operator targetoperator:$target)], IIBranch, FrmJ> { 529 let isTerminator=1; 530 let isBarrier=1; 531 let hasDelaySlot = 1; 532 let DecoderMethod = "DecodeJumpTarget"; 533 let Defs = [AT]; 534} 535 536// Unconditional branch 537class UncondBranch<Instruction BEQInst> : 538 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, 539 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 540 let isBranch = 1; 541 let isTerminator = 1; 542 let isBarrier = 1; 543 let hasDelaySlot = 1; 544 let Predicates = [RelocPIC, HasStdEnc]; 545 let Defs = [AT]; 546} 547 548// Base class for indirect branch and return instruction classes. 549let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 550class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>: 551 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>; 552 553// Indirect branch 554class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> { 555 let isBranch = 1; 556 let isIndirectBranch = 1; 557} 558 559// Return instruction 560class RetBase<RegisterOperand RO>: JumpFR<RO> { 561 let isReturn = 1; 562 let isCodeGenOnly = 1; 563 let hasCtrlDep = 1; 564 let hasExtraSrcRegAllocReq = 1; 565} 566 567// Jump and Link (Call) 568let isCall=1, hasDelaySlot=1, Defs = [RA] in { 569 class JumpLink<string opstr> : 570 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 571 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 572 let DecoderMethod = "DecodeJumpTarget"; 573 } 574 575 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 576 Register RetReg, RegisterOperand ResRO = RO>: 577 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 578 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 579 580 class JumpLinkReg<string opstr, RegisterOperand RO>: 581 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 582 [], IIBranch, FrmR>; 583 584 class BGEZAL_FT<string opstr, RegisterOperand RO> : 585 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 586 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 587 588} 589 590class BAL_BR_Pseudo<Instruction RealInst> : 591 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 592 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 593 let isBranch = 1; 594 let isTerminator = 1; 595 let isBarrier = 1; 596 let hasDelaySlot = 1; 597 let Defs = [RA]; 598} 599 600// Syscall 601class SYS_FT<string opstr> : 602 InstSE<(outs), (ins uimm20:$code_), 603 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; 604// Break 605class BRK_FT<string opstr> : 606 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 607 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; 608 609// (D)Eret 610class ER_FT<string opstr> : 611 InstSE<(outs), (ins), 612 opstr, [], NoItinerary, FrmOther>; 613 614// Interrupts 615class DEI_FT<string opstr, RegisterOperand RO> : 616 InstSE<(outs RO:$rt), (ins), 617 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>; 618 619// Wait 620class WAIT_FT<string opstr> : 621 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> { 622 let Inst{31-26} = 0x10; 623 let Inst{25} = 1; 624 let Inst{24-6} = 0; 625 let Inst{5-0} = 0x20; 626} 627 628// Sync 629let hasSideEffects = 1 in 630class SYNC_FT : 631 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 632 NoItinerary, FrmOther>; 633 634let hasSideEffects = 1 in 635class TEQ_FT<string opstr, RegisterOperand RO> : 636 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 637 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; 638 639class TEQI_FT<string opstr, RegisterOperand RO> : 640 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 641 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>; 642// Mul, Div 643class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 644 list<Register> DefRegs> : 645 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 646 itin, FrmR, opstr> { 647 let isCommutable = 1; 648 let Defs = DefRegs; 649 let neverHasSideEffects = 1; 650} 651 652// Pseudo multiply/divide instruction with explicit accumulator register 653// operands. 654class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 655 SDPatternOperator OpNode, InstrItinClass Itin, 656 bit IsComm = 1, bit HasSideEffects = 0, 657 bit UsesCustomInserter = 0> : 658 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 659 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 660 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 661 let isCommutable = IsComm; 662 let hasSideEffects = HasSideEffects; 663 let usesCustomInserter = UsesCustomInserter; 664} 665 666// Pseudo multiply add/sub instruction with explicit accumulator register 667// operands. 668class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 669 : PseudoSE<(outs ACC64:$ac), 670 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 671 [(set ACC64:$ac, 672 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 673 IIImult>, 674 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 675 string Constraints = "$acin = $ac"; 676} 677 678class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 679 list<Register> DefRegs> : 680 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 681 [], itin, FrmR> { 682 let Defs = DefRegs; 683} 684 685// Move from Hi/Lo 686class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>: 687 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, 688 FrmR, opstr> { 689 let Uses = UseRegs; 690 let neverHasSideEffects = 1; 691} 692 693class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 694 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, 695 FrmR, opstr> { 696 let Defs = DefRegs; 697 let neverHasSideEffects = 1; 698} 699 700class EffectiveAddress<string opstr, RegisterOperand RO> : 701 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 702 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> { 703 let isCodeGenOnly = 1; 704 let DecoderMethod = "DecodeMem"; 705} 706 707// Count Leading Ones/Zeros in Word 708class CountLeading0<string opstr, RegisterOperand RO>: 709 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 710 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>, 711 Requires<[HasBitCount, HasStdEnc]>; 712 713class CountLeading1<string opstr, RegisterOperand RO>: 714 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 715 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>, 716 Requires<[HasBitCount, HasStdEnc]>; 717 718 719// Sign Extend in Register. 720class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> : 721 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 722 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> { 723 let Predicates = [HasSEInReg, HasStdEnc]; 724} 725 726// Subword Swap 727class SubwordSwap<string opstr, RegisterOperand RO>: 728 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 729 NoItinerary, FrmR> { 730 let Predicates = [HasSwap, HasStdEnc]; 731 let neverHasSideEffects = 1; 732} 733 734// Read Hardware 735class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 736 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 737 IIArith, FrmR>; 738 739// Ext and Ins 740class ExtBase<string opstr, RegisterOperand RO>: 741 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 742 !strconcat(opstr, " $rt, $rs, $pos, $size"), 743 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 744 FrmR> { 745 let Predicates = [HasMips32r2, HasStdEnc]; 746} 747 748class InsBase<string opstr, RegisterOperand RO>: 749 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 750 !strconcat(opstr, " $rt, $rs, $pos, $size"), 751 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 752 NoItinerary, FrmR> { 753 let Predicates = [HasMips32r2, HasStdEnc]; 754 let Constraints = "$src = $rt"; 755} 756 757// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 758class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 759 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 760 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 761 762// Atomic Compare & Swap. 763class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 764 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 765 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 766 767class LLBase<string opstr, RegisterOperand RO> : 768 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 769 [], NoItinerary, FrmI> { 770 let DecoderMethod = "DecodeMem"; 771 let mayLoad = 1; 772} 773 774class SCBase<string opstr, RegisterOperand RO> : 775 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 776 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 777 let DecoderMethod = "DecodeMem"; 778 let mayStore = 1; 779 let Constraints = "$rt = $dst"; 780} 781 782class MFC3OP<string asmstr, RegisterOperand RO> : 783 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 784 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 785 786class TrapBase<Instruction RealInst> 787 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>, 788 PseudoInstExpansion<(RealInst 0, 0)> { 789 let isBarrier = 1; 790 let isTerminator = 1; 791 let isCodeGenOnly = 1; 792} 793 794//===----------------------------------------------------------------------===// 795// Pseudo instructions 796//===----------------------------------------------------------------------===// 797 798// Return RA. 799let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 800def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 801 802let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 803def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 804 [(callseq_start timm:$amt)]>; 805def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 806 [(callseq_end timm:$amt1, timm:$amt2)]>; 807} 808 809let usesCustomInserter = 1 in { 810 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 811 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 812 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 813 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 814 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 815 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 816 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 817 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 818 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 819 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 820 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 821 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 822 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 823 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 824 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 825 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 826 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 827 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 828 829 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 830 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 831 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 832 833 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 834 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 835 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 836} 837 838/// Pseudo instructions for loading and storing accumulator registers. 839let isPseudo = 1, isCodeGenOnly = 1 in { 840 def LOAD_ACC64 : Load<"", ACC64>; 841 def STORE_ACC64 : Store<"", ACC64>; 842} 843 844//===----------------------------------------------------------------------===// 845// Instruction definition 846//===----------------------------------------------------------------------===// 847//===----------------------------------------------------------------------===// 848// MipsI Instructions 849//===----------------------------------------------------------------------===// 850 851/// Arithmetic Instructions (ALU Immediate) 852def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16, 853 add>, 854 ADDI_FM<0x9>, IsAsCheapAsAMove; 855def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>; 856def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 857 SLTI_FM<0xa>; 858def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 859 SLTI_FM<0xb>; 860def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16, 861 and>, 862 ADDI_FM<0xc>; 863def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16, 864 or>, 865 ADDI_FM<0xd>; 866def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16, 867 xor>, 868 ADDI_FM<0xe>; 869def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 870 871/// Arithmetic Instructions (3-Operand, R-Type) 872def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>, 873 ADD_FM<0, 0x21>; 874def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>, 875 ADD_FM<0, 0x23>; 876def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>, 877 ADD_FM<0x1c, 2>; 878def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 879def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 880def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 881def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 882def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>, 883 ADD_FM<0, 0x24>; 884def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>, 885 ADD_FM<0, 0x25>; 886def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>, 887 ADD_FM<0, 0x26>; 888def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 889 890/// Shift Instructions 891def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>, 892 SRA_FM<0, 0>; 893def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>, 894 SRA_FM<2, 0>; 895def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>, 896 SRA_FM<3, 0>; 897def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>; 898def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>; 899def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>; 900 901// Rotate Instructions 902let Predicates = [HasMips32r2, HasStdEnc] in { 903 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr, 904 immZExt5>, 905 SRA_FM<2, 1>; 906 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>, 907 SRLV_FM<6, 1>; 908} 909 910/// Load and Store Instructions 911/// aligned 912def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>; 913def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel, 914 LW_FM<0x24>; 915def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel, 916 LW_FM<0x21>; 917def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; 918def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, 919 LW_FM<0x23>; 920def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; 921def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; 922def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; 923 924/// load/store left/right 925def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>; 926def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>; 927def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>; 928def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>; 929 930def SYNC : SYNC_FT, SYNC_FM; 931def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 932def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; 933def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; 934def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; 935def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; 936def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; 937 938def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>; 939def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>; 940def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>; 941def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>; 942def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>; 943def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>; 944 945def BREAK : BRK_FT<"break">, BRK_FM<0xd>; 946def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; 947def TRAP : TrapBase<BREAK>; 948 949def ERET : ER_FT<"eret">, ER_FM<0x18>; 950def DERET : ER_FT<"deret">, ER_FM<0x1f>; 951 952def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; 953def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>; 954 955def WAIT : WAIT_FT<"wait">; 956 957/// Load-linked, Store-conditional 958def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>; 959def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>; 960 961/// Jump and Branch Instructions 962def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 963 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 964def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>; 965def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>; 966def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>; 967def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>; 968def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>; 969def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>; 970def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>; 971def B : UncondBranch<BEQ>; 972 973def JAL : JumpLink<"jal">, FJ<3>; 974def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 975def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 976def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>; 977def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>; 978def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 979def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 980def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall; 981 982def RET : RetBase<GPR32Opnd>, MTLO_FM<8>; 983 984// Exception handling related node and instructions. 985// The conversion sequence is: 986// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 987// MIPSeh_return -> (stack change + indirect branch) 988// 989// MIPSeh_return takes the place of regular return instruction 990// but takes two arguments (V1, V0) which are used for storing 991// the offset and return address respectively. 992def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 993 994def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 995 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 996 997let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 998 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 999 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1000 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1001 GPR64:$dst), 1002 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1003} 1004 1005/// Multiply and Divide Instructions. 1006def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>, 1007 MULT_FM<0, 0x18>; 1008def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>, 1009 MULT_FM<0, 0x19>; 1010def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; 1011def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; 1012def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>; 1013def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>; 1014def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, 1015 0, 1, 1>; 1016def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, 1017 0, 1, 1>; 1018 1019def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; 1020def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; 1021def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>; 1022def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>; 1023 1024/// Sign Ext In Register Instructions. 1025def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; 1026def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; 1027 1028/// Count Leading 1029def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; 1030def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; 1031 1032/// Word Swap Bytes Within Halfwords 1033def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; 1034 1035/// No operation. 1036def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1037 1038// FrameIndexes are legalized when they are operands from load/store 1039// instructions. The same not happens for stack address copies, so an 1040// add op with mem ComplexPattern is used and the stack address copy 1041// can be matched. It's similar to Sparc LEA_ADDRi 1042def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1043 1044// MADD*/MSUB* 1045def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1046def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1047def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>; 1048def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>; 1049def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1050def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1051def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1052def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1053 1054def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1055 1056def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>; 1057def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>; 1058 1059/// Move Control Registers From/To CPU Registers 1060def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>; 1061def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>; 1062def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1063def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1064 1065//===----------------------------------------------------------------------===// 1066// Instruction aliases 1067//===----------------------------------------------------------------------===// 1068def : InstAlias<"move $dst, $src", 1069 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1070 Requires<[NotMips64]>; 1071def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; 1072def : InstAlias<"addu $rs, $rt, $imm", 1073 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1074def : InstAlias<"add $rs, $rt, $imm", 1075 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1076def : InstAlias<"and $rs, $rt, $imm", 1077 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1078def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1079def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1080def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1081def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1082def : InstAlias<"not $rt, $rs", 1083 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1084def : InstAlias<"neg $rt, $rs", 1085 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1086def : InstAlias<"negu $rt, $rs", 1087 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1088def : InstAlias<"slt $rs, $rt, $imm", 1089 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1090def : InstAlias<"xor $rs, $rt, $imm", 1091 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1092def : InstAlias<"or $rs, $rt, $imm", 1093 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1094def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1095def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1096def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1097def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1098def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1099def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1100def : InstAlias<"bnez $rs,$offset", 1101 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1102def : InstAlias<"beqz $rs,$offset", 1103 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1104def : InstAlias<"syscall", (SYSCALL 0), 1>; 1105 1106def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1107def : InstAlias<"break", (BREAK 0, 0), 1>; 1108def : InstAlias<"ei", (EI ZERO), 1>; 1109def : InstAlias<"di", (DI ZERO), 1>; 1110 1111def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1112def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1113def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1114def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1115def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1116def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1117//===----------------------------------------------------------------------===// 1118// Assembler Pseudo Instructions 1119//===----------------------------------------------------------------------===// 1120 1121class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1122 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1123 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1124def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>; 1125 1126class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1127 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1128 !strconcat(instr_asm, "\t$rt, $addr")> ; 1129def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1130 1131class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1132 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1133 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1134def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>; 1135 1136 1137 1138//===----------------------------------------------------------------------===// 1139// Arbitrary patterns that map to one or more instructions 1140//===----------------------------------------------------------------------===// 1141 1142// Load/store pattern templates. 1143class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1144 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1145 1146class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1147 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1148 1149// Small immediates 1150def : MipsPat<(i32 immSExt16:$in), 1151 (ADDiu ZERO, imm:$in)>; 1152def : MipsPat<(i32 immZExt16:$in), 1153 (ORi ZERO, imm:$in)>; 1154def : MipsPat<(i32 immLow16Zero:$in), 1155 (LUi (HI16 imm:$in))>; 1156 1157// Arbitrary immediates 1158def : MipsPat<(i32 imm:$imm), 1159 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1160 1161// Carry MipsPatterns 1162def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1163 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1164let Predicates = [HasStdEnc, NotDSP] in { 1165 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1166 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1167 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1168 (ADDiu GPR32:$src, imm:$imm)>; 1169} 1170 1171// Call 1172def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1173 (JAL tglobaladdr:$dst)>; 1174def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1175 (JAL texternalsym:$dst)>; 1176//def : MipsPat<(MipsJmpLink GPR32:$dst), 1177// (JALR GPR32:$dst)>; 1178 1179// Tail call 1180def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1181 (TAILCALL tglobaladdr:$dst)>; 1182def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1183 (TAILCALL texternalsym:$dst)>; 1184// hi/lo relocs 1185def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1186def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1187def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1188def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1189def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1190def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1191 1192def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1193def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1194def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1195def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1196def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1197def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1198 1199def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1200 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1201def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1202 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1203def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1204 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1205def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1206 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1207def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1208 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1209 1210// gp_rel relocs 1211def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1212 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1213def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1214 (ADDiu GPR32:$gp, tconstpool:$in)>; 1215 1216// wrapper_pic 1217class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1218 MipsPat<(MipsWrapper RC:$gp, node:$in), 1219 (ADDiuOp RC:$gp, node:$in)>; 1220 1221def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1222def : WrapperPat<tconstpool, ADDiu, GPR32>; 1223def : WrapperPat<texternalsym, ADDiu, GPR32>; 1224def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1225def : WrapperPat<tjumptable, ADDiu, GPR32>; 1226def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1227 1228// Mips does not have "not", so we expand our way 1229def : MipsPat<(not GPR32:$in), 1230 (NOR GPR32Opnd:$in, ZERO)>; 1231 1232// extended loads 1233let Predicates = [HasStdEnc] in { 1234 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1235 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1236 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1237} 1238 1239// peepholes 1240let Predicates = [HasStdEnc] in 1241def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1242 1243// brcond patterns 1244multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1245 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1246 Instruction SLTiuOp, Register ZEROReg> { 1247def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1248 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1249def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1250 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1251 1252def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1253 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1254def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1255 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1256def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1257 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1258def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1259 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1260def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1261 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1262def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1263 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1264 1265def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1266 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1267def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1268 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1269 1270def : MipsPat<(brcond RC:$cond, bb:$dst), 1271 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1272} 1273 1274defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1275 1276def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1277 (BLEZ i32:$lhs, bb:$dst)>; 1278def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1279 (BGEZ i32:$lhs, bb:$dst)>; 1280 1281// setcc patterns 1282multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1283 Instruction SLTuOp, Register ZEROReg> { 1284 def : MipsPat<(seteq RC:$lhs, 0), 1285 (SLTiuOp RC:$lhs, 1)>; 1286 def : MipsPat<(setne RC:$lhs, 0), 1287 (SLTuOp ZEROReg, RC:$lhs)>; 1288 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1289 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1290 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1291 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1292} 1293 1294multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1295 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1296 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1297 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1298 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1299} 1300 1301multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1302 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1303 (SLTOp RC:$rhs, RC:$lhs)>; 1304 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1305 (SLTuOp RC:$rhs, RC:$lhs)>; 1306} 1307 1308multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1309 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1310 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1311 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1312 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1313} 1314 1315multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1316 Instruction SLTiuOp> { 1317 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1318 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1319 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1320 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1321} 1322 1323defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1324defm : SetlePats<GPR32, SLT, SLTu>; 1325defm : SetgtPats<GPR32, SLT, SLTu>; 1326defm : SetgePats<GPR32, SLT, SLTu>; 1327defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1328 1329// bswap pattern 1330def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1331 1332// mflo/hi patterns. 1333def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)), 1334 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>; 1335 1336// Load halfword/word patterns. 1337let AddedComplexity = 40 in { 1338 let Predicates = [HasStdEnc] in { 1339 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1340 def : LoadRegImmPat<LH, i32, sextloadi16>; 1341 def : LoadRegImmPat<LW, i32, load>; 1342 } 1343} 1344 1345//===----------------------------------------------------------------------===// 1346// Floating Point Support 1347//===----------------------------------------------------------------------===// 1348 1349include "MipsInstrFPU.td" 1350include "Mips64InstrInfo.td" 1351include "MipsCondMov.td" 1352 1353// 1354// Mips16 1355 1356include "Mips16InstrFormats.td" 1357include "Mips16InstrInfo.td" 1358 1359// DSP 1360include "MipsDSPInstrFormats.td" 1361include "MipsDSPInstrInfo.td" 1362 1363// MSA 1364include "MipsMSAInstrFormats.td" 1365include "MipsMSAInstrInfo.td" 1366 1367// Micromips 1368include "MicroMipsInstrFormats.td" 1369include "MicroMipsInstrInfo.td" 1370