MipsInstrInfo.td revision ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 16-bit zero extended on target immediate. 302// The LO16 param means that only the lower 16 bits of the node 303// immediate are caught. 304// e.g. addiu, sltiu 305def immZExt16 : PatLeaf<(imm), [{ 306 if (N->getValueType(0) == MVT::i32) 307 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 308 else 309 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 310}], LO16>; 311 312// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 313def immLow16Zero : PatLeaf<(imm), [{ 314 int64_t Val = N->getSExtValue(); 315 return isInt<32>(Val) && !(Val & 0xffff); 316}]>; 317 318// shamt field must fit in 5 bits. 319def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 320 321// Mips Address Mode! SDNode frameindex could possibily be a match 322// since load and store instructions from stack used it. 323def addr : 324 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 325 326//===----------------------------------------------------------------------===// 327// Instructions specific format 328//===----------------------------------------------------------------------===// 329 330/// Move Control Registers From/To CPU Registers 331def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 332 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 333def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 334 335def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 336 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 337def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 338 339def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 340 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 341def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 342 343def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 344 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 345def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 346 347// Arithmetic and logical instructions with 3 register operands. 348class ArithLogicR<string opstr, InstrItinClass Itin, RegisterClass RC, 349 bit isComm = 0, SDPatternOperator OpNode = null_frag>: 350 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 351 !strconcat(opstr, "\t$rd, $rs, $rt"), 352 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 353 let isCommutable = isComm; 354 let isReMaterializable = 1; 355} 356 357// Arithmetic and logical instructions with 2 register operands. 358class ArithLogicI<string opstr, Operand Od, PatLeaf imm_type, 359 RegisterClass RC, SDPatternOperator OpNode = null_frag> : 360 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 361 !strconcat(opstr, "\t$rt, $rs, $imm16"), 362 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 363 let isReMaterializable = 1; 364} 365 366// Arithmetic Multiply ADD/SUB 367let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 368class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 369 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 370 !strconcat(instr_asm, "\t$rs, $rt"), 371 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 372 let rd = 0; 373 let shamt = 0; 374 let isCommutable = isComm; 375} 376 377// Logical 378class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 379 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 380 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 381 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 382 let shamt = 0; 383 let isCommutable = 1; 384} 385 386// Shifts 387class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm, 388 SDNode OpNode, PatFrag PF, Operand ImmOpnd, 389 RegisterClass RC>: 390 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 391 !strconcat(instr_asm, "\t$rd, $rt, $shamt"), 392 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> { 393 let rs = isRotate; 394} 395 396// 32-bit shift instructions. 397class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm, 398 SDNode OpNode>: 399 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>; 400 401class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, 402 SDNode OpNode, RegisterClass RC>: 403 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 404 !strconcat(instr_asm, "\t$rd, $rt, $rs"), 405 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { 406 let shamt = isRotate; 407} 408 409// Load Upper Imediate 410class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 411 FI<op, (outs RC:$rt), (ins Imm:$imm16), 412 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { 413 let rs = 0; 414 let neverHasSideEffects = 1; 415 let isReMaterializable = 1; 416} 417 418class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 419 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 420 bits<21> addr; 421 let Inst{25-21} = addr{20-16}; 422 let Inst{15-0} = addr{15-0}; 423 let DecoderMethod = "DecodeMem"; 424} 425 426// Memory Load/Store 427let canFoldAsLoad = 1 in 428class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 429 Operand MemOpnd, bit Pseudo>: 430 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 431 !strconcat(instr_asm, "\t$rt, $addr"), 432 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 433 let isPseudo = Pseudo; 434} 435 436class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 437 Operand MemOpnd, bit Pseudo>: 438 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 439 !strconcat(instr_asm, "\t$rt, $addr"), 440 [(OpNode RC:$rt, addr:$addr)], IIStore> { 441 let isPseudo = Pseudo; 442} 443 444// 32-bit load. 445multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 446 bit Pseudo = 0> { 447 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 448 Requires<[NotN64, HasStdEnc]>; 449 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 450 Requires<[IsN64, HasStdEnc]> { 451 let DecoderNamespace = "Mips64"; 452 let isCodeGenOnly = 1; 453 } 454} 455 456// 64-bit load. 457multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 458 bit Pseudo = 0> { 459 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 460 Requires<[NotN64, HasStdEnc]>; 461 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 462 Requires<[IsN64, HasStdEnc]> { 463 let DecoderNamespace = "Mips64"; 464 let isCodeGenOnly = 1; 465 } 466} 467 468// 32-bit store. 469multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 470 bit Pseudo = 0> { 471 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 472 Requires<[NotN64, HasStdEnc]>; 473 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 474 Requires<[IsN64, HasStdEnc]> { 475 let DecoderNamespace = "Mips64"; 476 let isCodeGenOnly = 1; 477 } 478} 479 480// 64-bit store. 481multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 482 bit Pseudo = 0> { 483 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 484 Requires<[NotN64, HasStdEnc]>; 485 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 486 Requires<[IsN64, HasStdEnc]> { 487 let DecoderNamespace = "Mips64"; 488 let isCodeGenOnly = 1; 489 } 490} 491 492// Load/Store Left/Right 493let canFoldAsLoad = 1 in 494class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 495 RegisterClass RC, Operand MemOpnd> : 496 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 497 !strconcat(instr_asm, "\t$rt, $addr"), 498 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 499 string Constraints = "$src = $rt"; 500} 501 502class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 503 RegisterClass RC, Operand MemOpnd>: 504 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 505 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 506 IIStore>; 507 508// 32-bit load left/right. 509multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 510 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 511 Requires<[NotN64, HasStdEnc]>; 512 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 513 Requires<[IsN64, HasStdEnc]> { 514 let DecoderNamespace = "Mips64"; 515 let isCodeGenOnly = 1; 516 } 517} 518 519// 64-bit load left/right. 520multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 521 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 522 Requires<[NotN64, HasStdEnc]>; 523 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 524 Requires<[IsN64, HasStdEnc]> { 525 let DecoderNamespace = "Mips64"; 526 let isCodeGenOnly = 1; 527 } 528} 529 530// 32-bit store left/right. 531multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 532 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 533 Requires<[NotN64, HasStdEnc]>; 534 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 535 Requires<[IsN64, HasStdEnc]> { 536 let DecoderNamespace = "Mips64"; 537 let isCodeGenOnly = 1; 538 } 539} 540 541// 64-bit store left/right. 542multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 543 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 544 Requires<[NotN64, HasStdEnc]>; 545 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 546 Requires<[IsN64, HasStdEnc]> { 547 let DecoderNamespace = "Mips64"; 548 let isCodeGenOnly = 1; 549 } 550} 551 552// Conditional Branch 553class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>: 554 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 555 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 556 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { 557 let isBranch = 1; 558 let isTerminator = 1; 559 let hasDelaySlot = 1; 560 let Defs = [AT]; 561} 562 563class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op, 564 RegisterClass RC>: 565 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16), 566 !strconcat(instr_asm, "\t$rs, $imm16"), 567 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { 568 let rt = _rt; 569 let isBranch = 1; 570 let isTerminator = 1; 571 let hasDelaySlot = 1; 572 let Defs = [AT]; 573} 574 575// SetCC 576class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 577 RegisterClass RC>: 578 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 579 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 580 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 581 IIAlu> { 582 let shamt = 0; 583} 584 585class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 586 PatLeaf imm_type, RegisterClass RC>: 587 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 588 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 589 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 590 IIAlu>; 591 592// Jump 593class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 594 SDPatternOperator operator, SDPatternOperator targetoperator>: 595 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 596 [(operator targetoperator:$target)], IIBranch> { 597 let isTerminator=1; 598 let isBarrier=1; 599 let hasDelaySlot = 1; 600 let DecoderMethod = "DecodeJumpTarget"; 601 let Defs = [AT]; 602} 603 604// Unconditional branch 605class UncondBranch<bits<6> op, string instr_asm>: 606 BranchBase<op, (outs), (ins brtarget:$imm16), 607 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 608 let rs = 0; 609 let rt = 0; 610 let isBranch = 1; 611 let isTerminator = 1; 612 let isBarrier = 1; 613 let hasDelaySlot = 1; 614 let Predicates = [RelocPIC, HasStdEnc]; 615 let Defs = [AT]; 616} 617 618// Base class for indirect branch and return instruction classes. 619let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 620class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 621 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 622 let rt = 0; 623 let rd = 0; 624 let shamt = 0; 625} 626 627// Indirect branch 628class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 629 let isBranch = 1; 630 let isIndirectBranch = 1; 631} 632 633// Return instruction 634class RetBase<RegisterClass RC>: JumpFR<RC> { 635 let isReturn = 1; 636 let isCodeGenOnly = 1; 637 let hasCtrlDep = 1; 638 let hasExtraSrcRegAllocReq = 1; 639} 640 641// Jump and Link (Call) 642let isCall=1, hasDelaySlot=1, Defs = [RA] in { 643 class JumpLink<bits<6> op, string instr_asm>: 644 FJ<op, (outs), (ins calltarget:$target), 645 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 646 IIBranch> { 647 let DecoderMethod = "DecodeJumpTarget"; 648 } 649 650 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 651 RegisterClass RC>: 652 FR<op, func, (outs), (ins RC:$rs), 653 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 654 let rt = 0; 655 let rd = 31; 656 let shamt = 0; 657 } 658 659 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 660 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 661 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 662 let rt = _rt; 663 } 664} 665 666// Mul, Div 667class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 668 RegisterClass RC, list<Register> DefRegs>: 669 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 670 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 671 let rd = 0; 672 let shamt = 0; 673 let isCommutable = 1; 674 let Defs = DefRegs; 675 let neverHasSideEffects = 1; 676} 677 678class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 679 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 680 681class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 682 RegisterClass RC, list<Register> DefRegs>: 683 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 684 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 685 [(op RC:$rs, RC:$rt)], itin> { 686 let rd = 0; 687 let shamt = 0; 688 let Defs = DefRegs; 689} 690 691class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 692 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 693 694// Move from Hi/Lo 695class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 696 list<Register> UseRegs>: 697 FR<0x00, func, (outs RC:$rd), (ins), 698 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 699 let rs = 0; 700 let rt = 0; 701 let shamt = 0; 702 let Uses = UseRegs; 703 let neverHasSideEffects = 1; 704} 705 706class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 707 list<Register> DefRegs>: 708 FR<0x00, func, (outs), (ins RC:$rs), 709 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 710 let rt = 0; 711 let rd = 0; 712 let shamt = 0; 713 let Defs = DefRegs; 714 let neverHasSideEffects = 1; 715} 716 717class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 718 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 719 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 720 let isCodeGenOnly = 1; 721} 722 723// Count Leading Ones/Zeros in Word 724class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 725 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 726 !strconcat(instr_asm, "\t$rd, $rs"), 727 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 728 Requires<[HasBitCount, HasStdEnc]> { 729 let shamt = 0; 730 let rt = rd; 731} 732 733class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 734 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 735 !strconcat(instr_asm, "\t$rd, $rs"), 736 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 737 Requires<[HasBitCount, HasStdEnc]> { 738 let shamt = 0; 739 let rt = rd; 740} 741 742// Sign Extend in Register. 743class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 744 RegisterClass RC>: 745 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 746 !strconcat(instr_asm, "\t$rd, $rt"), 747 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 748 let rs = 0; 749 let shamt = sa; 750 let Predicates = [HasSEInReg, HasStdEnc]; 751} 752 753// Subword Swap 754class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 755 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 756 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 757 let rs = 0; 758 let shamt = sa; 759 let Predicates = [HasSwap, HasStdEnc]; 760 let neverHasSideEffects = 1; 761} 762 763// Read Hardware 764class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 765 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 766 "rdhwr\t$rt, $rd", [], IIAlu> { 767 let rs = 0; 768 let shamt = 0; 769} 770 771// Ext and Ins 772class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 773 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 774 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 775 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 776 bits<5> pos; 777 bits<5> sz; 778 let rd = sz; 779 let shamt = pos; 780 let Predicates = [HasMips32r2, HasStdEnc]; 781} 782 783class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 784 FR<0x1f, _funct, (outs RC:$rt), 785 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 786 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 787 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 788 NoItinerary> { 789 bits<5> pos; 790 bits<5> sz; 791 let rd = sz; 792 let shamt = pos; 793 let Predicates = [HasMips32r2, HasStdEnc]; 794 let Constraints = "$src = $rt"; 795} 796 797// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 798class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 799 RegisterClass PRC> : 800 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 801 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 802 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 803 804multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 805 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 806 Requires<[NotN64, HasStdEnc]>; 807 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 808 Requires<[IsN64, HasStdEnc]> { 809 let DecoderNamespace = "Mips64"; 810 } 811} 812 813// Atomic Compare & Swap. 814class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 815 RegisterClass PRC> : 816 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 817 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 818 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 819 820multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 821 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 822 Requires<[NotN64, HasStdEnc]>; 823 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 824 Requires<[IsN64, HasStdEnc]> { 825 let DecoderNamespace = "Mips64"; 826 } 827} 828 829class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 830 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 831 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 832 let mayLoad = 1; 833} 834 835class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 836 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 837 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 838 let mayStore = 1; 839 let Constraints = "$rt = $dst"; 840} 841 842//===----------------------------------------------------------------------===// 843// Pseudo instructions 844//===----------------------------------------------------------------------===// 845 846// Return RA. 847let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 848def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 849 850let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 851def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 852 "!ADJCALLSTACKDOWN $amt", 853 [(callseq_start timm:$amt)]>; 854def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 855 "!ADJCALLSTACKUP $amt1", 856 [(callseq_end timm:$amt1, timm:$amt2)]>; 857} 858 859// When handling PIC code the assembler needs .cpload and .cprestore 860// directives. If the real instructions corresponding these directives 861// are used, we have the same behavior, but get also a bunch of warnings 862// from the assembler. 863let neverHasSideEffects = 1 in 864def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 865 ".cprestore\t$loc", []>; 866 867let usesCustomInserter = 1 in { 868 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 869 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 870 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 871 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 872 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 873 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 874 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 875 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 876 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 877 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 878 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 879 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 880 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 881 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 882 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 883 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 884 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 885 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 886 887 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 888 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 889 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 890 891 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 892 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 893 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 894} 895 896//===----------------------------------------------------------------------===// 897// Instruction definition 898//===----------------------------------------------------------------------===// 899 900class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 901 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 902 !strconcat(instr_asm, "\t$rt, $imm32")> ; 903def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 904 905class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 906 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 907 !strconcat(instr_asm, "\t$rt, $addr")> ; 908def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 909 910class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 911 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 912 !strconcat(instr_asm, "\t$rt, $imm32")> ; 913def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 914 915//===----------------------------------------------------------------------===// 916// MipsI Instructions 917//===----------------------------------------------------------------------===// 918 919/// Arithmetic Instructions (ALU Immediate) 920def ADDiu : ArithLogicI<"addiu", simm16, immSExt16, CPURegs, add>, 921 ADDI_FM<0x9>, IsAsCheapAsAMove; 922def ADDi : ArithLogicI<"addi", simm16, immSExt16, CPURegs>, ADDI_FM<0x8>; 923def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 924def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 925def ANDi : ArithLogicI<"andi", uimm16, immZExt16, CPURegs, and>, ADDI_FM<0xc>; 926def ORi : ArithLogicI<"ori", uimm16, immZExt16, CPURegs, or>, ADDI_FM<0xd>; 927def XORi : ArithLogicI<"xori", uimm16, immZExt16, CPURegs, xor>, ADDI_FM<0xe>; 928def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 929 930/// Arithmetic Instructions (3-Operand, R-Type) 931def ADDu : ArithLogicR<"addu", IIAlu, CPURegs, 1, add>, ADD_FM<0, 0x21>; 932def SUBu : ArithLogicR<"subu", IIAlu, CPURegs, 0, sub>, ADD_FM<0, 0x23>; 933def ADD : ArithLogicR<"add", IIAlu, CPURegs, 1>, ADD_FM<0, 0x20>; 934def SUB : ArithLogicR<"sub", IIAlu, CPURegs, 0>, ADD_FM<0, 0x22>; 935def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 936def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 937def AND : ArithLogicR<"and", IIAlu, CPURegs, 1, and>, ADD_FM<0, 0x24>; 938def OR : ArithLogicR<"or", IIAlu, CPURegs, 1, or>, ADD_FM<0, 0x25>; 939def XOR : ArithLogicR<"xor", IIAlu, CPURegs, 1, xor>, ADD_FM<0, 0x26>; 940def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 941 942/// Shift Instructions 943def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; 944def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>; 945def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>; 946def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>; 947def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>; 948def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>; 949 950// Rotate Instructions 951let Predicates = [HasMips32r2, HasStdEnc] in { 952 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>; 953 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>; 954} 955 956/// Load and Store Instructions 957/// aligned 958defm LB : LoadM32<0x20, "lb", sextloadi8>; 959defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 960defm LH : LoadM32<0x21, "lh", sextloadi16>; 961defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 962defm LW : LoadM32<0x23, "lw", load>; 963defm SB : StoreM32<0x28, "sb", truncstorei8>; 964defm SH : StoreM32<0x29, "sh", truncstorei16>; 965defm SW : StoreM32<0x2b, "sw", store>; 966 967/// load/store left/right 968defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 969defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 970defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 971defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 972 973let hasSideEffects = 1 in 974def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 975 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 976{ 977 bits<5> stype; 978 let Opcode = 0; 979 let Inst{25-11} = 0; 980 let Inst{10-6} = stype; 981 let Inst{5-0} = 15; 982} 983 984/// Load-linked, Store-conditional 985def LL : LLBase<0x30, "ll", CPURegs, mem>, 986 Requires<[NotN64, HasStdEnc]>; 987def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 988 Requires<[IsN64, HasStdEnc]> { 989 let DecoderNamespace = "Mips64"; 990} 991 992def SC : SCBase<0x38, "sc", CPURegs, mem>, 993 Requires<[NotN64, HasStdEnc]>; 994def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 995 Requires<[IsN64, HasStdEnc]> { 996 let DecoderNamespace = "Mips64"; 997} 998 999/// Jump and Branch Instructions 1000def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 1001 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 1002def JR : IndirectBranch<CPURegs>; 1003def B : UncondBranch<0x04, "b">; 1004def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; 1005def BNE : CBranch<0x05, "bne", setne, CPURegs>; 1006def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; 1007def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 1008def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; 1009def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; 1010 1011let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 1012 hasDelaySlot = 1, Defs = [RA] in 1013def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 1014 1015def JAL : JumpLink<0x03, "jal">; 1016def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 1017def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 1018def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 1019def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 1020def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 1021 1022def RET : RetBase<CPURegs>; 1023 1024/// Multiply and Divide Instructions. 1025def MULT : Mult32<0x18, "mult", IIImul>; 1026def MULTu : Mult32<0x19, "multu", IIImul>; 1027def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 1028def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 1029 1030def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1031def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1032def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1033def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1034 1035/// Sign Ext In Register Instructions. 1036def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1037def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1038 1039/// Count Leading 1040def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1041def CLO : CountLeading1<0x21, "clo", CPURegs>; 1042 1043/// Word Swap Bytes Within Halfwords 1044def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1045 1046/// No operation 1047let addr=0 in 1048 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1049 1050// FrameIndexes are legalized when they are operands from load/store 1051// instructions. The same not happens for stack address copies, so an 1052// add op with mem ComplexPattern is used and the stack address copy 1053// can be matched. It's similar to Sparc LEA_ADDRi 1054def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1055 1056// MADD*/MSUB* 1057def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1058def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1059def MSUB : MArithR<4, "msub", MipsMSub>; 1060def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1061 1062// MUL is a assembly macro in the current used ISAs. In recent ISA's 1063// it is a real instruction. 1064def MUL : ArithLogicR<"mul", IIImul, CPURegs, 1, mul>, ADD_FM<0x1c, 0x02>; 1065 1066def RDHWR : ReadHardware<CPURegs, HWRegs>; 1067 1068def EXT : ExtBase<0, "ext", CPURegs>; 1069def INS : InsBase<4, "ins", CPURegs>; 1070 1071//===----------------------------------------------------------------------===// 1072// Instruction aliases 1073//===----------------------------------------------------------------------===// 1074def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1075def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1076def : InstAlias<"addu $rs,$rt,$imm", 1077 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1078def : InstAlias<"add $rs,$rt,$imm", 1079 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1080def : InstAlias<"and $rs,$rt,$imm", 1081 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1082def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1083def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1084def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1085def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1086def : InstAlias<"slt $rs,$rt,$imm", 1087 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1088def : InstAlias<"xor $rs,$rt,$imm", 1089 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1090 1091//===----------------------------------------------------------------------===// 1092// Arbitrary patterns that map to one or more instructions 1093//===----------------------------------------------------------------------===// 1094 1095// Small immediates 1096def : MipsPat<(i32 immSExt16:$in), 1097 (ADDiu ZERO, imm:$in)>; 1098def : MipsPat<(i32 immZExt16:$in), 1099 (ORi ZERO, imm:$in)>; 1100def : MipsPat<(i32 immLow16Zero:$in), 1101 (LUi (HI16 imm:$in))>; 1102 1103// Arbitrary immediates 1104def : MipsPat<(i32 imm:$imm), 1105 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1106 1107// Carry MipsPatterns 1108def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1109 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1110def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1111 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1112def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1113 (ADDiu CPURegs:$src, imm:$imm)>; 1114 1115// Call 1116def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1117 (JAL tglobaladdr:$dst)>; 1118def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1119 (JAL texternalsym:$dst)>; 1120//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1121// (JALR CPURegs:$dst)>; 1122 1123// Tail call 1124def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1125 (TAILCALL tglobaladdr:$dst)>; 1126def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1127 (TAILCALL texternalsym:$dst)>; 1128// hi/lo relocs 1129def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1130def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1131def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1132def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1133def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1134def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1135 1136def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1137def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1138def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1139def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1140def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1141def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1142 1143def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1144 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1145def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1146 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1147def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1148 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1149def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1150 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1151def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1152 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1153 1154// gp_rel relocs 1155def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1156 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1157def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1158 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1159 1160// wrapper_pic 1161class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1162 MipsPat<(MipsWrapper RC:$gp, node:$in), 1163 (ADDiuOp RC:$gp, node:$in)>; 1164 1165def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1166def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1167def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1168def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1169def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1170def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1171 1172// Mips does not have "not", so we expand our way 1173def : MipsPat<(not CPURegs:$in), 1174 (NOR CPURegs:$in, ZERO)>; 1175 1176// extended loads 1177let Predicates = [NotN64, HasStdEnc] in { 1178 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1179 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1180 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1181} 1182let Predicates = [IsN64, HasStdEnc] in { 1183 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1184 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1185 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1186} 1187 1188// peepholes 1189let Predicates = [NotN64, HasStdEnc] in { 1190 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1191} 1192let Predicates = [IsN64, HasStdEnc] in { 1193 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1194} 1195 1196// brcond patterns 1197multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1198 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1199 Instruction SLTiuOp, Register ZEROReg> { 1200def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1201 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1202def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1203 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1204 1205def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1206 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1207def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1208 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1209def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1210 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1211def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1212 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1213 1214def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1215 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1216def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1217 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1218 1219def : MipsPat<(brcond RC:$cond, bb:$dst), 1220 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1221} 1222 1223defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1224 1225// setcc patterns 1226multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1227 Instruction SLTuOp, Register ZEROReg> { 1228 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1229 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1230 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1231 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1232} 1233 1234multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1235 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1236 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1237 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1238 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1239} 1240 1241multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1242 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1243 (SLTOp RC:$rhs, RC:$lhs)>; 1244 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1245 (SLTuOp RC:$rhs, RC:$lhs)>; 1246} 1247 1248multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1249 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1250 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1251 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1252 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1253} 1254 1255multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1256 Instruction SLTiuOp> { 1257 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1258 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1259 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1260 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1261} 1262 1263defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1264defm : SetlePats<CPURegs, SLT, SLTu>; 1265defm : SetgtPats<CPURegs, SLT, SLTu>; 1266defm : SetgePats<CPURegs, SLT, SLTu>; 1267defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1268 1269// bswap pattern 1270def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1271 1272//===----------------------------------------------------------------------===// 1273// Floating Point Support 1274//===----------------------------------------------------------------------===// 1275 1276include "MipsInstrFPU.td" 1277include "Mips64InstrInfo.td" 1278include "MipsCondMov.td" 1279 1280// 1281// Mips16 1282 1283include "Mips16InstrFormats.td" 1284include "Mips16InstrInfo.td" 1285 1286// DSP 1287include "MipsDSPInstrFormats.td" 1288include "MipsDSPInstrInfo.td" 1289 1290