MipsInstrInfo.td revision ab9705f8fa48f1f00f159746139509faab919ee2
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, 37 SDTCisSameAs<0, 1>]>; 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Tail call 56def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 58 59// Hi and Lo nodes are used to handle global addresses. Used on 60// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 61// static model. (nothing to do with Mips Registers Hi and Lo) 62def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 63def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 64def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 65 66// TlsGd node is used to handle General Dynamic TLS 67def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 68 69// TprelHi and TprelLo nodes are used to handle Local Exec TLS 70def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 71def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 72 73// Thread pointer 74def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 75 76// Return 77def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 78 79// These are target-independent nodes, but have target-specific formats. 80def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 81 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 82def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 83 [SDNPHasChain, SDNPSideEffect, 84 SDNPOptInGlue, SDNPOutGlue]>; 85 86// MAdd*/MSub* nodes 87def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 94 [SDNPOptInGlue, SDNPOutGlue]>; 95 96// DivRem(u) nodes 97def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 100 [SDNPOutGlue]>; 101 102// Target constant nodes that are not part of any isel patterns and remain 103// unchanged can cause instructions with illegal operands to be emitted. 104// Wrapper node patterns give the instruction selector a chance to replace 105// target constant nodes that would otherwise remain unchanged with ADDiu 106// nodes. Without these wrapper node patterns, the following conditional move 107// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 108// compiled: 109// movn %got(d)($gp), %got(c)($gp), $4 110// This instruction is illegal since movn can take only register operands. 111 112def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 113 114// Pointer to dynamically allocated stack area. 115def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, 116 [SDNPHasChain, SDNPInGlue]>; 117 118def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 119 120def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 121def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 122 123def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 124 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 125def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 128 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 129def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 133def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 134 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 135def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 137def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 138 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 139 140//===----------------------------------------------------------------------===// 141// Mips Instruction Predicate Definitions. 142//===----------------------------------------------------------------------===// 143def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 144 AssemblerPredicate<"FeatureSEInReg">; 145def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 146 AssemblerPredicate<"FeatureBitCount">; 147def HasSwap : Predicate<"Subtarget.hasSwap()">, 148 AssemblerPredicate<"FeatureSwap">; 149def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 150 AssemblerPredicate<"FeatureCondMov">; 151def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 152 AssemblerPredicate<"FeatureFPIdx">; 153def HasMips32 : Predicate<"Subtarget.hasMips32()">, 154 AssemblerPredicate<"FeatureMips32">; 155def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 156 AssemblerPredicate<"FeatureMips32r2">; 157def HasMips64 : Predicate<"Subtarget.hasMips64()">, 158 AssemblerPredicate<"FeatureMips64">; 159def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 160 AssemblerPredicate<"!FeatureMips64">; 161def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 162 AssemblerPredicate<"FeatureMips64r2">; 163def IsN64 : Predicate<"Subtarget.isABI_N64()">, 164 AssemblerPredicate<"FeatureN64">; 165def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 166 AssemblerPredicate<"!FeatureN64">; 167def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 168 AssemblerPredicate<"FeatureMips16">; 169def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 170 AssemblerPredicate<"FeatureMips32">; 171def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 172 AssemblerPredicate<"FeatureMips32">; 173def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 174 AssemblerPredicate<"FeatureMips32">; 175def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">, 176 AssemblerPredicate<"!FeatureMips16">; 177 178class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 179 let Predicates = [HasStandardEncoding]; 180} 181 182class IsBranch { 183 bit isBranch = 1; 184} 185 186class IsReturn { 187 bit isReturn = 1; 188} 189 190class IsCall { 191 bit isCall = 1; 192} 193 194class IsTailCall { 195 bit isCall = 1; 196 bit isTerminator = 1; 197 bit isReturn = 1; 198 bit isBarrier = 1; 199 bit hasExtraSrcRegAllocReq = 1; 200 bit isCodeGenOnly = 1; 201} 202 203class IsAsCheapAsAMove { 204 bit isAsCheapAsAMove = 1; 205} 206 207class NeverHasSideEffects { 208 bit neverHasSideEffects = 1; 209} 210 211//===----------------------------------------------------------------------===// 212// Instruction format superclass 213//===----------------------------------------------------------------------===// 214 215include "MipsInstrFormats.td" 216 217//===----------------------------------------------------------------------===// 218// Mips Operand, Complex Patterns and Transformations Definitions. 219//===----------------------------------------------------------------------===// 220 221// Instruction operand types 222def jmptarget : Operand<OtherVT> { 223 let EncoderMethod = "getJumpTargetOpValue"; 224} 225def brtarget : Operand<OtherVT> { 226 let EncoderMethod = "getBranchTargetOpValue"; 227 let OperandType = "OPERAND_PCREL"; 228 let DecoderMethod = "DecodeBranchTarget"; 229} 230def calltarget : Operand<iPTR> { 231 let EncoderMethod = "getJumpTargetOpValue"; 232} 233def calltarget64: Operand<i64>; 234def simm16 : Operand<i32> { 235 let DecoderMethod= "DecodeSimm16"; 236} 237def simm16_64 : Operand<i64>; 238def shamt : Operand<i32>; 239 240// Unsigned Operand 241def uimm16 : Operand<i32> { 242 let PrintMethod = "printUnsignedImm"; 243} 244 245def MipsMemAsmOperand : AsmOperandClass { 246 let Name = "Mem"; 247 let ParserMethod = "parseMemOperand"; 248} 249 250// Address operand 251def mem : Operand<i32> { 252 let PrintMethod = "printMemOperand"; 253 let MIOperandInfo = (ops CPURegs, simm16); 254 let EncoderMethod = "getMemEncoding"; 255 let ParserMatchClass = MipsMemAsmOperand; 256} 257 258def mem64 : Operand<i64> { 259 let PrintMethod = "printMemOperand"; 260 let MIOperandInfo = (ops CPU64Regs, simm16_64); 261 let EncoderMethod = "getMemEncoding"; 262 let ParserMatchClass = MipsMemAsmOperand; 263} 264 265def mem_ea : Operand<i32> { 266 let PrintMethod = "printMemOperandEA"; 267 let MIOperandInfo = (ops CPURegs, simm16); 268 let EncoderMethod = "getMemEncoding"; 269} 270 271def mem_ea_64 : Operand<i64> { 272 let PrintMethod = "printMemOperandEA"; 273 let MIOperandInfo = (ops CPU64Regs, simm16_64); 274 let EncoderMethod = "getMemEncoding"; 275} 276 277// size operand of ext instruction 278def size_ext : Operand<i32> { 279 let EncoderMethod = "getSizeExtEncoding"; 280 let DecoderMethod = "DecodeExtSize"; 281} 282 283// size operand of ins instruction 284def size_ins : Operand<i32> { 285 let EncoderMethod = "getSizeInsEncoding"; 286 let DecoderMethod = "DecodeInsSize"; 287} 288 289// Transformation Function - get the lower 16 bits. 290def LO16 : SDNodeXForm<imm, [{ 291 return getImm(N, N->getZExtValue() & 0xFFFF); 292}]>; 293 294// Transformation Function - get the higher 16 bits. 295def HI16 : SDNodeXForm<imm, [{ 296 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 297}]>; 298 299// Node immediate fits as 16-bit sign extended on target immediate. 300// e.g. addi, andi 301def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 302 303// Node immediate fits as 16-bit zero extended on target immediate. 304// The LO16 param means that only the lower 16 bits of the node 305// immediate are caught. 306// e.g. addiu, sltiu 307def immZExt16 : PatLeaf<(imm), [{ 308 if (N->getValueType(0) == MVT::i32) 309 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 310 else 311 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 312}], LO16>; 313 314// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 315def immLow16Zero : PatLeaf<(imm), [{ 316 int64_t Val = N->getSExtValue(); 317 return isInt<32>(Val) && !(Val & 0xffff); 318}]>; 319 320// shamt field must fit in 5 bits. 321def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 322 323// Mips Address Mode! SDNode frameindex could possibily be a match 324// since load and store instructions from stack used it. 325def addr : 326 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 327 328//===----------------------------------------------------------------------===// 329// Instructions specific format 330//===----------------------------------------------------------------------===// 331 332/// Move Control Registers From/To CPU Registers 333def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 334 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 335def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 336 337def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 338 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 339def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 340 341def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 342 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 343def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 344 345def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 346 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 347def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 348 349// Arithmetic and logical instructions with 3 register operands. 350class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, 351 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 352 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 353 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 354 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> { 355 let shamt = 0; 356 let isCommutable = isComm; 357 let isReMaterializable = 1; 358} 359 360class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm, 361 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 362 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 363 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> { 364 let shamt = 0; 365 let isCommutable = isComm; 366} 367 368// Arithmetic and logical instructions with 2 register operands. 369class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode, 370 Operand Od, PatLeaf imm_type, RegisterClass RC> : 371 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 372 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 373 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> { 374 let isReMaterializable = 1; 375} 376 377class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode, 378 Operand Od, PatLeaf imm_type, RegisterClass RC> : 379 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 380 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>; 381 382// Arithmetic Multiply ADD/SUB 383let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 384class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 385 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 386 !strconcat(instr_asm, "\t$rs, $rt"), 387 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 388 let rd = 0; 389 let shamt = 0; 390 let isCommutable = isComm; 391} 392 393// Logical 394class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 395 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 396 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 397 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 398 let shamt = 0; 399 let isCommutable = 1; 400} 401 402// Shifts 403class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm, 404 SDNode OpNode, PatFrag PF, Operand ImmOpnd, 405 RegisterClass RC>: 406 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 407 !strconcat(instr_asm, "\t$rd, $rt, $shamt"), 408 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> { 409 let rs = isRotate; 410} 411 412// 32-bit shift instructions. 413class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm, 414 SDNode OpNode>: 415 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>; 416 417class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, 418 SDNode OpNode, RegisterClass RC>: 419 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 420 !strconcat(instr_asm, "\t$rd, $rt, $rs"), 421 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { 422 let shamt = isRotate; 423} 424 425// Load Upper Imediate 426class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 427 FI<op, (outs RC:$rt), (ins Imm:$imm16), 428 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { 429 let rs = 0; 430 let neverHasSideEffects = 1; 431 let isReMaterializable = 1; 432} 433 434class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 435 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 436 bits<21> addr; 437 let Inst{25-21} = addr{20-16}; 438 let Inst{15-0} = addr{15-0}; 439 let DecoderMethod = "DecodeMem"; 440} 441 442// Memory Load/Store 443let canFoldAsLoad = 1 in 444class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 445 Operand MemOpnd, bit Pseudo>: 446 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 447 !strconcat(instr_asm, "\t$rt, $addr"), 448 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 449 let isPseudo = Pseudo; 450} 451 452class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 453 Operand MemOpnd, bit Pseudo>: 454 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 455 !strconcat(instr_asm, "\t$rt, $addr"), 456 [(OpNode RC:$rt, addr:$addr)], IIStore> { 457 let isPseudo = Pseudo; 458} 459 460// 32-bit load. 461multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 462 bit Pseudo = 0> { 463 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 464 Requires<[NotN64, HasStandardEncoding]>; 465 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 466 Requires<[IsN64, HasStandardEncoding]> { 467 let DecoderNamespace = "Mips64"; 468 let isCodeGenOnly = 1; 469 } 470} 471 472// 64-bit load. 473multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 474 bit Pseudo = 0> { 475 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 476 Requires<[NotN64, HasStandardEncoding]>; 477 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 478 Requires<[IsN64, HasStandardEncoding]> { 479 let DecoderNamespace = "Mips64"; 480 let isCodeGenOnly = 1; 481 } 482} 483 484// 32-bit store. 485multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 486 bit Pseudo = 0> { 487 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 488 Requires<[NotN64, HasStandardEncoding]>; 489 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 490 Requires<[IsN64, HasStandardEncoding]> { 491 let DecoderNamespace = "Mips64"; 492 let isCodeGenOnly = 1; 493 } 494} 495 496// 64-bit store. 497multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 498 bit Pseudo = 0> { 499 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 500 Requires<[NotN64, HasStandardEncoding]>; 501 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 502 Requires<[IsN64, HasStandardEncoding]> { 503 let DecoderNamespace = "Mips64"; 504 let isCodeGenOnly = 1; 505 } 506} 507 508// Load/Store Left/Right 509let canFoldAsLoad = 1 in 510class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 511 RegisterClass RC, Operand MemOpnd> : 512 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 513 !strconcat(instr_asm, "\t$rt, $addr"), 514 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 515 string Constraints = "$src = $rt"; 516} 517 518class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 519 RegisterClass RC, Operand MemOpnd>: 520 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 521 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 522 IIStore>; 523 524// 32-bit load left/right. 525multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 526 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 527 Requires<[NotN64, HasStandardEncoding]>; 528 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 529 Requires<[IsN64, HasStandardEncoding]> { 530 let DecoderNamespace = "Mips64"; 531 let isCodeGenOnly = 1; 532 } 533} 534 535// 64-bit load left/right. 536multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 537 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 538 Requires<[NotN64, HasStandardEncoding]>; 539 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 540 Requires<[IsN64, HasStandardEncoding]> { 541 let DecoderNamespace = "Mips64"; 542 let isCodeGenOnly = 1; 543 } 544} 545 546// 32-bit store left/right. 547multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 548 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 549 Requires<[NotN64, HasStandardEncoding]>; 550 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 551 Requires<[IsN64, HasStandardEncoding]> { 552 let DecoderNamespace = "Mips64"; 553 let isCodeGenOnly = 1; 554 } 555} 556 557// 64-bit store left/right. 558multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 559 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 560 Requires<[NotN64, HasStandardEncoding]>; 561 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 562 Requires<[IsN64, HasStandardEncoding]> { 563 let DecoderNamespace = "Mips64"; 564 let isCodeGenOnly = 1; 565 } 566} 567 568// Conditional Branch 569class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>: 570 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 571 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 572 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { 573 let isBranch = 1; 574 let isTerminator = 1; 575 let hasDelaySlot = 1; 576 let Defs = [AT]; 577} 578 579class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op, 580 RegisterClass RC>: 581 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16), 582 !strconcat(instr_asm, "\t$rs, $imm16"), 583 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { 584 let rt = _rt; 585 let isBranch = 1; 586 let isTerminator = 1; 587 let hasDelaySlot = 1; 588 let Defs = [AT]; 589} 590 591// SetCC 592class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 593 RegisterClass RC>: 594 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 595 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 596 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 597 IIAlu> { 598 let shamt = 0; 599} 600 601class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 602 PatLeaf imm_type, RegisterClass RC>: 603 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 604 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 605 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 606 IIAlu>; 607 608// Jump 609class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 610 SDPatternOperator operator, SDPatternOperator targetoperator>: 611 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 612 [(operator targetoperator:$target)], IIBranch> { 613 let isTerminator=1; 614 let isBarrier=1; 615 let hasDelaySlot = 1; 616 let DecoderMethod = "DecodeJumpTarget"; 617 let Defs = [AT]; 618} 619 620// Unconditional branch 621class UncondBranch<bits<6> op, string instr_asm>: 622 BranchBase<op, (outs), (ins brtarget:$imm16), 623 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 624 let rs = 0; 625 let rt = 0; 626 let isBranch = 1; 627 let isTerminator = 1; 628 let isBarrier = 1; 629 let hasDelaySlot = 1; 630 let Predicates = [RelocPIC, HasStandardEncoding]; 631 let Defs = [AT]; 632} 633 634// Base class for indirect branch and return instruction classes. 635let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 636class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 637 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 638 let rt = 0; 639 let rd = 0; 640 let shamt = 0; 641} 642 643// Indirect branch 644class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 645 let isBranch = 1; 646 let isIndirectBranch = 1; 647} 648 649// Return instruction 650class RetBase<RegisterClass RC>: JumpFR<RC> { 651 let isReturn = 1; 652 let isCodeGenOnly = 1; 653 let hasCtrlDep = 1; 654 let hasExtraSrcRegAllocReq = 1; 655} 656 657// Jump and Link (Call) 658let isCall=1, hasDelaySlot=1, Defs = [RA] in { 659 class JumpLink<bits<6> op, string instr_asm>: 660 FJ<op, (outs), (ins calltarget:$target), 661 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 662 IIBranch> { 663 let DecoderMethod = "DecodeJumpTarget"; 664 } 665 666 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 667 RegisterClass RC>: 668 FR<op, func, (outs), (ins RC:$rs), 669 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 670 let rt = 0; 671 let rd = 31; 672 let shamt = 0; 673 } 674 675 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 676 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 677 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 678 let rt = _rt; 679 } 680} 681 682// Mul, Div 683class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 684 RegisterClass RC, list<Register> DefRegs>: 685 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 686 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 687 let rd = 0; 688 let shamt = 0; 689 let isCommutable = 1; 690 let Defs = DefRegs; 691 let neverHasSideEffects = 1; 692} 693 694class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 695 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 696 697class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 698 RegisterClass RC, list<Register> DefRegs>: 699 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 700 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 701 [(op RC:$rs, RC:$rt)], itin> { 702 let rd = 0; 703 let shamt = 0; 704 let Defs = DefRegs; 705} 706 707class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 708 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 709 710// Move from Hi/Lo 711class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 712 list<Register> UseRegs>: 713 FR<0x00, func, (outs RC:$rd), (ins), 714 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 715 let rs = 0; 716 let rt = 0; 717 let shamt = 0; 718 let Uses = UseRegs; 719 let neverHasSideEffects = 1; 720} 721 722class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 723 list<Register> DefRegs>: 724 FR<0x00, func, (outs), (ins RC:$rs), 725 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 726 let rt = 0; 727 let rd = 0; 728 let shamt = 0; 729 let Defs = DefRegs; 730 let neverHasSideEffects = 1; 731} 732 733class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 734 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 735 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 736 let isCodeGenOnly = 1; 737} 738 739// Count Leading Ones/Zeros in Word 740class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 741 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 742 !strconcat(instr_asm, "\t$rd, $rs"), 743 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 744 Requires<[HasBitCount, HasStandardEncoding]> { 745 let shamt = 0; 746 let rt = rd; 747} 748 749class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 750 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 751 !strconcat(instr_asm, "\t$rd, $rs"), 752 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 753 Requires<[HasBitCount, HasStandardEncoding]> { 754 let shamt = 0; 755 let rt = rd; 756} 757 758// Sign Extend in Register. 759class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 760 RegisterClass RC>: 761 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 762 !strconcat(instr_asm, "\t$rd, $rt"), 763 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 764 let rs = 0; 765 let shamt = sa; 766 let Predicates = [HasSEInReg, HasStandardEncoding]; 767} 768 769// Subword Swap 770class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 771 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 772 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 773 let rs = 0; 774 let shamt = sa; 775 let Predicates = [HasSwap, HasStandardEncoding]; 776 let neverHasSideEffects = 1; 777} 778 779// Read Hardware 780class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 781 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 782 "rdhwr\t$rt, $rd", [], IIAlu> { 783 let rs = 0; 784 let shamt = 0; 785} 786 787// Ext and Ins 788class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 789 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 790 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 791 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 792 bits<5> pos; 793 bits<5> sz; 794 let rd = sz; 795 let shamt = pos; 796 let Predicates = [HasMips32r2, HasStandardEncoding]; 797} 798 799class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 800 FR<0x1f, _funct, (outs RC:$rt), 801 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 802 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 803 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 804 NoItinerary> { 805 bits<5> pos; 806 bits<5> sz; 807 let rd = sz; 808 let shamt = pos; 809 let Predicates = [HasMips32r2, HasStandardEncoding]; 810 let Constraints = "$src = $rt"; 811} 812 813// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 814class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 815 RegisterClass PRC> : 816 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 817 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 818 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 819 820multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 821 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 822 Requires<[NotN64, HasStandardEncoding]>; 823 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 824 Requires<[IsN64, HasStandardEncoding]> { 825 let DecoderNamespace = "Mips64"; 826 } 827} 828 829// Atomic Compare & Swap. 830class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 831 RegisterClass PRC> : 832 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 833 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 834 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 835 836multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 837 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 838 Requires<[NotN64, HasStandardEncoding]>; 839 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 840 Requires<[IsN64, HasStandardEncoding]> { 841 let DecoderNamespace = "Mips64"; 842 } 843} 844 845class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 846 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 847 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 848 let mayLoad = 1; 849} 850 851class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 852 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 853 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 854 let mayStore = 1; 855 let Constraints = "$rt = $dst"; 856} 857 858//===----------------------------------------------------------------------===// 859// Pseudo instructions 860//===----------------------------------------------------------------------===// 861 862// Return RA. 863let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 864def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 865 866let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 867def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 868 "!ADJCALLSTACKDOWN $amt", 869 [(callseq_start timm:$amt)]>; 870def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 871 "!ADJCALLSTACKUP $amt1", 872 [(callseq_end timm:$amt1, timm:$amt2)]>; 873} 874 875// When handling PIC code the assembler needs .cpload and .cprestore 876// directives. If the real instructions corresponding these directives 877// are used, we have the same behavior, but get also a bunch of warnings 878// from the assembler. 879let neverHasSideEffects = 1 in 880def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 881 ".cprestore\t$loc", []>; 882 883let usesCustomInserter = 1 in { 884 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 885 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 886 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 887 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 888 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 889 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 890 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 891 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 892 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 893 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 894 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 895 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 896 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 897 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 898 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 899 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 900 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 901 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 902 903 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 904 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 905 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 906 907 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 908 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 909 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 910} 911 912//===----------------------------------------------------------------------===// 913// Instruction definition 914//===----------------------------------------------------------------------===// 915 916class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 917 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 918 !strconcat(instr_asm, "\t$rt, $imm32")> ; 919def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 920 921class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 922 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 923 !strconcat(instr_asm, "\t$rt, $addr")> ; 924def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 925 926class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 927 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 928 !strconcat(instr_asm, "\t$rt, $imm32")> ; 929def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 930 931//===----------------------------------------------------------------------===// 932// MipsI Instructions 933//===----------------------------------------------------------------------===// 934 935/// Arithmetic Instructions (ALU Immediate) 936def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>, 937 IsAsCheapAsAMove; 938def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; 939def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 940def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 941def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; 942def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; 943def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; 944def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 945 946/// Arithmetic Instructions (3-Operand, R-Type) 947def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; 948def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>; 949def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; 950def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>; 951def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 952def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 953def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; 954def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; 955def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; 956def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 957 958/// Shift Instructions 959def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; 960def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>; 961def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>; 962def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>; 963def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>; 964def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>; 965 966// Rotate Instructions 967let Predicates = [HasMips32r2, HasStandardEncoding] in { 968 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>; 969 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>; 970} 971 972/// Load and Store Instructions 973/// aligned 974defm LB : LoadM32<0x20, "lb", sextloadi8>; 975defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 976defm LH : LoadM32<0x21, "lh", sextloadi16>; 977defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 978defm LW : LoadM32<0x23, "lw", load>; 979defm SB : StoreM32<0x28, "sb", truncstorei8>; 980defm SH : StoreM32<0x29, "sh", truncstorei16>; 981defm SW : StoreM32<0x2b, "sw", store>; 982 983/// load/store left/right 984defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 985defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 986defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 987defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 988 989let hasSideEffects = 1 in 990def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 991 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 992{ 993 bits<5> stype; 994 let Opcode = 0; 995 let Inst{25-11} = 0; 996 let Inst{10-6} = stype; 997 let Inst{5-0} = 15; 998} 999 1000/// Load-linked, Store-conditional 1001def LL : LLBase<0x30, "ll", CPURegs, mem>, 1002 Requires<[NotN64, HasStandardEncoding]>; 1003def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 1004 Requires<[IsN64, HasStandardEncoding]> { 1005 let DecoderNamespace = "Mips64"; 1006} 1007 1008def SC : SCBase<0x38, "sc", CPURegs, mem>, 1009 Requires<[NotN64, HasStandardEncoding]>; 1010def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 1011 Requires<[IsN64, HasStandardEncoding]> { 1012 let DecoderNamespace = "Mips64"; 1013} 1014 1015/// Jump and Branch Instructions 1016def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 1017 Requires<[RelocStatic, HasStandardEncoding]>, IsBranch; 1018def JR : IndirectBranch<CPURegs>; 1019def B : UncondBranch<0x04, "b">; 1020def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; 1021def BNE : CBranch<0x05, "bne", setne, CPURegs>; 1022def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; 1023def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 1024def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; 1025def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; 1026 1027let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 1028 hasDelaySlot = 1, Defs = [RA] in 1029def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 1030 1031def JAL : JumpLink<0x03, "jal">; 1032def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 1033def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 1034def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 1035def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 1036def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 1037 1038def RET : RetBase<CPURegs>; 1039 1040/// Multiply and Divide Instructions. 1041def MULT : Mult32<0x18, "mult", IIImul>; 1042def MULTu : Mult32<0x19, "multu", IIImul>; 1043def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 1044def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 1045 1046def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1047def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1048def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1049def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1050 1051/// Sign Ext In Register Instructions. 1052def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1053def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1054 1055/// Count Leading 1056def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1057def CLO : CountLeading1<0x21, "clo", CPURegs>; 1058 1059/// Word Swap Bytes Within Halfwords 1060def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1061 1062/// No operation 1063let addr=0 in 1064 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1065 1066// FrameIndexes are legalized when they are operands from load/store 1067// instructions. The same not happens for stack address copies, so an 1068// add op with mem ComplexPattern is used and the stack address copy 1069// can be matched. It's similar to Sparc LEA_ADDRi 1070def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1071 1072// DynAlloc node points to dynamically allocated stack space. 1073// $sp is added to the list of implicitly used registers to prevent dead code 1074// elimination from removing instructions that modify $sp. 1075let Uses = [SP] in 1076def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1077 1078// MADD*/MSUB* 1079def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1080def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1081def MSUB : MArithR<4, "msub", MipsMSub>; 1082def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1083 1084// MUL is a assembly macro in the current used ISAs. In recent ISA's 1085// it is a real instruction. 1086def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, 1087 Requires<[HasStandardEncoding]>; 1088 1089def RDHWR : ReadHardware<CPURegs, HWRegs>; 1090 1091def EXT : ExtBase<0, "ext", CPURegs>; 1092def INS : InsBase<4, "ins", CPURegs>; 1093 1094//===----------------------------------------------------------------------===// 1095// Instruction aliases 1096//===----------------------------------------------------------------------===// 1097def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1098def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1099def : InstAlias<"addu $rs,$rt,$imm", 1100 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1101def : InstAlias<"add $rs,$rt,$imm", 1102 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1103def : InstAlias<"and $rs,$rt,$imm", 1104 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1105def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1106def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1107def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1108def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1109def : InstAlias<"slt $rs,$rt,$imm", 1110 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1111def : InstAlias<"xor $rs,$rt,$imm", 1112 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1113 1114//===----------------------------------------------------------------------===// 1115// Arbitrary patterns that map to one or more instructions 1116//===----------------------------------------------------------------------===// 1117 1118// Small immediates 1119def : MipsPat<(i32 immSExt16:$in), 1120 (ADDiu ZERO, imm:$in)>; 1121def : MipsPat<(i32 immZExt16:$in), 1122 (ORi ZERO, imm:$in)>; 1123def : MipsPat<(i32 immLow16Zero:$in), 1124 (LUi (HI16 imm:$in))>; 1125 1126// Arbitrary immediates 1127def : MipsPat<(i32 imm:$imm), 1128 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1129 1130// Carry MipsPatterns 1131def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1132 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1133def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1134 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1135def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1136 (ADDiu CPURegs:$src, imm:$imm)>; 1137 1138// Call 1139def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1140 (JAL tglobaladdr:$dst)>; 1141def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1142 (JAL texternalsym:$dst)>; 1143//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1144// (JALR CPURegs:$dst)>; 1145 1146// Tail call 1147def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1148 (TAILCALL tglobaladdr:$dst)>; 1149def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1150 (TAILCALL texternalsym:$dst)>; 1151// hi/lo relocs 1152def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1153def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1154def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1155def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1156def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1157def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1158 1159def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1160def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1161def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1162def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1163def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1164def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1165 1166def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1167 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1168def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1169 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1170def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1171 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1172def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1173 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1174def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1175 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1176 1177// gp_rel relocs 1178def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1179 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1180def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1181 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1182 1183// wrapper_pic 1184class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1185 MipsPat<(MipsWrapper RC:$gp, node:$in), 1186 (ADDiuOp RC:$gp, node:$in)>; 1187 1188def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1189def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1190def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1191def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1192def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1193def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1194 1195// Mips does not have "not", so we expand our way 1196def : MipsPat<(not CPURegs:$in), 1197 (NOR CPURegs:$in, ZERO)>; 1198 1199// extended loads 1200let Predicates = [NotN64, HasStandardEncoding] in { 1201 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1202 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1203 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1204} 1205let Predicates = [IsN64, HasStandardEncoding] in { 1206 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1207 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1208 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1209} 1210 1211// peepholes 1212let Predicates = [NotN64, HasStandardEncoding] in { 1213 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1214} 1215let Predicates = [IsN64, HasStandardEncoding] in { 1216 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1217} 1218 1219// brcond patterns 1220multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1221 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1222 Instruction SLTiuOp, Register ZEROReg> { 1223def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1224 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1225def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1226 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1227 1228def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1229 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1230def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1231 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1232def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1233 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1234def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1235 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1236 1237def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1238 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1239def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1240 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1241 1242def : MipsPat<(brcond RC:$cond, bb:$dst), 1243 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1244} 1245 1246defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1247 1248// setcc patterns 1249multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1250 Instruction SLTuOp, Register ZEROReg> { 1251 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1252 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1253 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1254 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1255} 1256 1257multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1258 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1259 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1260 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1261 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1262} 1263 1264multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1265 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1266 (SLTOp RC:$rhs, RC:$lhs)>; 1267 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1268 (SLTuOp RC:$rhs, RC:$lhs)>; 1269} 1270 1271multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1272 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1273 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1274 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1275 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1276} 1277 1278multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1279 Instruction SLTiuOp> { 1280 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1281 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1282 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1283 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1284} 1285 1286defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1287defm : SetlePats<CPURegs, SLT, SLTu>; 1288defm : SetgtPats<CPURegs, SLT, SLTu>; 1289defm : SetgePats<CPURegs, SLT, SLTu>; 1290defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1291 1292// select MipsDynAlloc 1293def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; 1294 1295// bswap pattern 1296def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1297 1298//===----------------------------------------------------------------------===// 1299// Floating Point Support 1300//===----------------------------------------------------------------------===// 1301 1302include "MipsInstrFPU.td" 1303include "Mips64InstrInfo.td" 1304include "MipsCondMov.td" 1305 1306// 1307// Mips16 1308 1309include "Mips16InstrFormats.td" 1310include "Mips16InstrInfo.td" 1311 1312// DSP 1313include "MipsDSPInstrFormats.td" 1314include "MipsDSPInstrInfo.td" 1315 1316