MipsInstrInfo.td revision b637b9f89e88e8c1ffe147634c1b2b297fb6edeb
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 30def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 31 SDTCisSameAs<1, 2>]>; 32def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 33 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 34 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 35def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 36 37def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 38 39def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 40 41def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 43def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 45 SDTCisSameAs<0, 4>]>; 46 47def SDTMipsLoadLR : SDTypeProfile<1, 2, 48 [SDTCisInt<0>, SDTCisPtrTy<1>, 49 SDTCisSameAs<0, 2>]>; 50 51// Call 52def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 53 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 54 SDNPVariadic]>; 55 56// Tail call 57def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 58 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 59 60// Hi and Lo nodes are used to handle global addresses. Used on 61// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 62// static model. (nothing to do with Mips Registers Hi and Lo) 63def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 64def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 65def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 66 67// TlsGd node is used to handle General Dynamic TLS 68def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 69 70// TprelHi and TprelLo nodes are used to handle Local Exec TLS 71def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 72def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 73 74// Thread pointer 75def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 76 77// Return 78def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 79 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 80 81// These are target-independent nodes, but have target-specific formats. 82def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 83 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 84def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 85 [SDNPHasChain, SDNPSideEffect, 86 SDNPOptInGlue, SDNPOutGlue]>; 87 88// Node used to extract integer from LO/HI register. 89def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 90 91// Node used to insert 32-bit integers to LOHI register pair. 92def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 93 94// Mult nodes. 95def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 97 98// MAdd*/MSub* nodes 99def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 101def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 103 104// DivRem(u) nodes 105def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 106def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 107def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, [SDNPOutGlue]>; 108def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110 111// Target constant nodes that are not part of any isel patterns and remain 112// unchanged can cause instructions with illegal operands to be emitted. 113// Wrapper node patterns give the instruction selector a chance to replace 114// target constant nodes that would otherwise remain unchanged with ADDiu 115// nodes. Without these wrapper node patterns, the following conditional move 116// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 117// compiled: 118// movn %got(d)($gp), %got(c)($gp), $4 119// This instruction is illegal since movn can take only register operands. 120 121def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 122 123def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 124 125def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 126def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 127 128def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 137 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 138def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 141 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 142def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144 145//===----------------------------------------------------------------------===// 146// Mips Instruction Predicate Definitions. 147//===----------------------------------------------------------------------===// 148def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 149 AssemblerPredicate<"FeatureSEInReg">; 150def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 151 AssemblerPredicate<"FeatureBitCount">; 152def HasSwap : Predicate<"Subtarget.hasSwap()">, 153 AssemblerPredicate<"FeatureSwap">; 154def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 155 AssemblerPredicate<"FeatureCondMov">; 156def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 157 AssemblerPredicate<"FeatureFPIdx">; 158def HasMips32 : Predicate<"Subtarget.hasMips32()">, 159 AssemblerPredicate<"FeatureMips32">; 160def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 161 AssemblerPredicate<"FeatureMips32r2">; 162def HasMips64 : Predicate<"Subtarget.hasMips64()">, 163 AssemblerPredicate<"FeatureMips64">; 164def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 165 AssemblerPredicate<"!FeatureMips64">; 166def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 167 AssemblerPredicate<"FeatureMips64r2">; 168def IsN64 : Predicate<"Subtarget.isABI_N64()">, 169 AssemblerPredicate<"FeatureN64">; 170def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 171 AssemblerPredicate<"!FeatureN64">; 172def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 173 AssemblerPredicate<"FeatureMips16">; 174def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 175 AssemblerPredicate<"FeatureMips32">; 176def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 177 AssemblerPredicate<"FeatureMips32">; 178def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 179 AssemblerPredicate<"FeatureMips32">; 180def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 181 AssemblerPredicate<"!FeatureMips16">; 182def NotDSP : Predicate<"!Subtarget.hasDSP()">; 183 184class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 185 let Predicates = [HasStdEnc]; 186} 187 188class IsCommutable { 189 bit isCommutable = 1; 190} 191 192class IsBranch { 193 bit isBranch = 1; 194} 195 196class IsReturn { 197 bit isReturn = 1; 198} 199 200class IsCall { 201 bit isCall = 1; 202} 203 204class IsTailCall { 205 bit isCall = 1; 206 bit isTerminator = 1; 207 bit isReturn = 1; 208 bit isBarrier = 1; 209 bit hasExtraSrcRegAllocReq = 1; 210 bit isCodeGenOnly = 1; 211} 212 213class IsAsCheapAsAMove { 214 bit isAsCheapAsAMove = 1; 215} 216 217class NeverHasSideEffects { 218 bit neverHasSideEffects = 1; 219} 220 221//===----------------------------------------------------------------------===// 222// Instruction format superclass 223//===----------------------------------------------------------------------===// 224 225include "MipsInstrFormats.td" 226 227//===----------------------------------------------------------------------===// 228// Mips Operand, Complex Patterns and Transformations Definitions. 229//===----------------------------------------------------------------------===// 230 231// Instruction operand types 232def jmptarget : Operand<OtherVT> { 233 let EncoderMethod = "getJumpTargetOpValue"; 234} 235def brtarget : Operand<OtherVT> { 236 let EncoderMethod = "getBranchTargetOpValue"; 237 let OperandType = "OPERAND_PCREL"; 238 let DecoderMethod = "DecodeBranchTarget"; 239} 240def calltarget : Operand<iPTR> { 241 let EncoderMethod = "getJumpTargetOpValue"; 242} 243def calltarget64: Operand<i64>; 244def simm16 : Operand<i32> { 245 let DecoderMethod= "DecodeSimm16"; 246} 247 248def simm20 : Operand<i32> { 249} 250 251def simm16_64 : Operand<i64>; 252def shamt : Operand<i32>; 253 254// Unsigned Operand 255def uimm16 : Operand<i32> { 256 let PrintMethod = "printUnsignedImm"; 257} 258 259def MipsMemAsmOperand : AsmOperandClass { 260 let Name = "Mem"; 261 let ParserMethod = "parseMemOperand"; 262} 263 264// Address operand 265def mem : Operand<i32> { 266 let PrintMethod = "printMemOperand"; 267 let MIOperandInfo = (ops CPURegs, simm16); 268 let EncoderMethod = "getMemEncoding"; 269 let ParserMatchClass = MipsMemAsmOperand; 270 let OperandType = "OPERAND_MEMORY"; 271} 272 273def mem64 : Operand<i64> { 274 let PrintMethod = "printMemOperand"; 275 let MIOperandInfo = (ops CPU64Regs, simm16_64); 276 let EncoderMethod = "getMemEncoding"; 277 let ParserMatchClass = MipsMemAsmOperand; 278 let OperandType = "OPERAND_MEMORY"; 279} 280 281def mem_ea : Operand<i32> { 282 let PrintMethod = "printMemOperandEA"; 283 let MIOperandInfo = (ops CPURegs, simm16); 284 let EncoderMethod = "getMemEncoding"; 285 let OperandType = "OPERAND_MEMORY"; 286} 287 288def mem_ea_64 : Operand<i64> { 289 let PrintMethod = "printMemOperandEA"; 290 let MIOperandInfo = (ops CPU64Regs, simm16_64); 291 let EncoderMethod = "getMemEncoding"; 292 let OperandType = "OPERAND_MEMORY"; 293} 294 295// size operand of ext instruction 296def size_ext : Operand<i32> { 297 let EncoderMethod = "getSizeExtEncoding"; 298 let DecoderMethod = "DecodeExtSize"; 299} 300 301// size operand of ins instruction 302def size_ins : Operand<i32> { 303 let EncoderMethod = "getSizeInsEncoding"; 304 let DecoderMethod = "DecodeInsSize"; 305} 306 307// Transformation Function - get the lower 16 bits. 308def LO16 : SDNodeXForm<imm, [{ 309 return getImm(N, N->getZExtValue() & 0xFFFF); 310}]>; 311 312// Transformation Function - get the higher 16 bits. 313def HI16 : SDNodeXForm<imm, [{ 314 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 315}]>; 316 317// Plus 1. 318def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 319 320// Node immediate fits as 16-bit sign extended on target immediate. 321// e.g. addi, andi 322def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 323 324// Node immediate fits as 16-bit sign extended on target immediate. 325// e.g. addi, andi 326def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 327 328// Node immediate fits as 15-bit sign extended on target immediate. 329// e.g. addi, andi 330def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 331 332// Node immediate fits as 16-bit zero extended on target immediate. 333// The LO16 param means that only the lower 16 bits of the node 334// immediate are caught. 335// e.g. addiu, sltiu 336def immZExt16 : PatLeaf<(imm), [{ 337 if (N->getValueType(0) == MVT::i32) 338 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 339 else 340 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 341}], LO16>; 342 343// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 344def immLow16Zero : PatLeaf<(imm), [{ 345 int64_t Val = N->getSExtValue(); 346 return isInt<32>(Val) && !(Val & 0xffff); 347}]>; 348 349// shamt field must fit in 5 bits. 350def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 351 352// True if (N + 1) fits in 16-bit field. 353def immSExt16Plus1 : PatLeaf<(imm), [{ 354 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 355}]>; 356 357// Mips Address Mode! SDNode frameindex could possibily be a match 358// since load and store instructions from stack used it. 359def addr : 360 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 361 362def addrRegImm : 363 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 364 365def addrDefault : 366 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 367 368//===----------------------------------------------------------------------===// 369// Instructions specific format 370//===----------------------------------------------------------------------===// 371 372// Arithmetic and logical instructions with 3 register operands. 373class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 374 InstrItinClass Itin = NoItinerary, 375 SDPatternOperator OpNode = null_frag>: 376 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 377 !strconcat(opstr, "\t$rd, $rs, $rt"), 378 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 379 let isCommutable = isComm; 380 let isReMaterializable = 1; 381} 382 383// Arithmetic and logical instructions with 2 register operands. 384class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 385 SDPatternOperator imm_type = null_frag, 386 SDPatternOperator OpNode = null_frag> : 387 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 388 !strconcat(opstr, "\t$rt, $rs, $imm16"), 389 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 390 IIAlu, FrmI, opstr> { 391 let isReMaterializable = 1; 392} 393 394// Arithmetic Multiply ADD/SUB 395class MArithR<string opstr, bit isComm = 0> : 396 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 397 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> { 398 let Defs = [HI, LO]; 399 let Uses = [HI, LO]; 400 let isCommutable = isComm; 401} 402 403// Logical 404class LogicNOR<string opstr, RegisterOperand RC>: 405 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 406 !strconcat(opstr, "\t$rd, $rs, $rt"), 407 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> { 408 let isCommutable = 1; 409} 410 411// Shifts 412class shift_rotate_imm<string opstr, Operand ImmOpnd, 413 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 414 SDPatternOperator PF = null_frag> : 415 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 416 !strconcat(opstr, "\t$rd, $rt, $shamt"), 417 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>; 418 419class shift_rotate_reg<string opstr, RegisterOperand RC, 420 SDPatternOperator OpNode = null_frag>: 421 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 422 !strconcat(opstr, "\t$rd, $rt, $rs"), 423 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>; 424 425// Load Upper Imediate 426class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 427 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 428 [], IIAlu, FrmI>, IsAsCheapAsAMove { 429 let neverHasSideEffects = 1; 430 let isReMaterializable = 1; 431} 432 433class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 434 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 435 bits<21> addr; 436 let Inst{25-21} = addr{20-16}; 437 let Inst{15-0} = addr{15-0}; 438 let DecoderMethod = "DecodeMem"; 439} 440 441// Memory Load/Store 442class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 443 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> : 444 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 445 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, 446 !strconcat(opstr, ofsuffix)> { 447 let DecoderMethod = "DecodeMem"; 448 let canFoldAsLoad = 1; 449 let mayLoad = 1; 450} 451 452class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 453 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> : 454 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 455 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI, 456 !strconcat(opstr, ofsuffix)> { 457 let DecoderMethod = "DecodeMem"; 458 let mayStore = 1; 459} 460 461multiclass LoadM<string opstr, RegisterClass RC, 462 SDPatternOperator OpNode = null_frag, 463 ComplexPattern Addr = addr> { 464 def NAME : Load<opstr, OpNode, RC, mem, Addr, "">, 465 Requires<[NotN64, HasStdEnc]>; 466 def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">, 467 Requires<[IsN64, HasStdEnc]> { 468 let DecoderNamespace = "Mips64"; 469 let isCodeGenOnly = 1; 470 } 471} 472 473multiclass StoreM<string opstr, RegisterClass RC, 474 SDPatternOperator OpNode = null_frag, 475 ComplexPattern Addr = addr> { 476 def NAME : Store<opstr, OpNode, RC, mem, Addr, "">, 477 Requires<[NotN64, HasStdEnc]>; 478 def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">, 479 Requires<[IsN64, HasStdEnc]> { 480 let DecoderNamespace = "Mips64"; 481 let isCodeGenOnly = 1; 482 } 483} 484 485// Load/Store Left/Right 486let canFoldAsLoad = 1 in 487class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 488 Operand MemOpnd> : 489 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 490 !strconcat(opstr, "\t$rt, $addr"), 491 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 492 let DecoderMethod = "DecodeMem"; 493 string Constraints = "$src = $rt"; 494} 495 496class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 497 Operand MemOpnd>: 498 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 499 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 500 let DecoderMethod = "DecodeMem"; 501} 502 503multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 504 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 505 Requires<[NotN64, HasStdEnc]>; 506 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 507 Requires<[IsN64, HasStdEnc]> { 508 let DecoderNamespace = "Mips64"; 509 let isCodeGenOnly = 1; 510 } 511} 512 513multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 514 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 515 Requires<[NotN64, HasStdEnc]>; 516 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 517 Requires<[IsN64, HasStdEnc]> { 518 let DecoderNamespace = "Mips64"; 519 let isCodeGenOnly = 1; 520 } 521} 522 523// Conditional Branch 524class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 525 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 526 !strconcat(opstr, "\t$rs, $rt, $offset"), 527 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 528 FrmI> { 529 let isBranch = 1; 530 let isTerminator = 1; 531 let hasDelaySlot = 1; 532 let Defs = [AT]; 533} 534 535class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 536 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 537 !strconcat(opstr, "\t$rs, $offset"), 538 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 539 let isBranch = 1; 540 let isTerminator = 1; 541 let hasDelaySlot = 1; 542 let Defs = [AT]; 543} 544 545// SetCC 546class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 547 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 548 !strconcat(opstr, "\t$rd, $rs, $rt"), 549 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], 550 IIAlu, FrmR, opstr>; 551 552class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 553 RegisterClass RC>: 554 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 555 !strconcat(opstr, "\t$rt, $rs, $imm16"), 556 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 557 IIAlu, FrmI, opstr>; 558 559// Jump 560class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 561 SDPatternOperator targetoperator> : 562 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 563 [(operator targetoperator:$target)], IIBranch, FrmJ> { 564 let isTerminator=1; 565 let isBarrier=1; 566 let hasDelaySlot = 1; 567 let DecoderMethod = "DecodeJumpTarget"; 568 let Defs = [AT]; 569} 570 571// Unconditional branch 572class UncondBranch<string opstr> : 573 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 574 [(br bb:$offset)], IIBranch, FrmI> { 575 let isBranch = 1; 576 let isTerminator = 1; 577 let isBarrier = 1; 578 let hasDelaySlot = 1; 579 let Predicates = [RelocPIC, HasStdEnc]; 580 let Defs = [AT]; 581} 582 583// Base class for indirect branch and return instruction classes. 584let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 585class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 586 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 587 588// Indirect branch 589class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 590 let isBranch = 1; 591 let isIndirectBranch = 1; 592} 593 594// Return instruction 595class RetBase<RegisterClass RC>: JumpFR<RC> { 596 let isReturn = 1; 597 let isCodeGenOnly = 1; 598 let hasCtrlDep = 1; 599 let hasExtraSrcRegAllocReq = 1; 600} 601 602// Jump and Link (Call) 603let isCall=1, hasDelaySlot=1, Defs = [RA] in { 604 class JumpLink<string opstr> : 605 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 606 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 607 let DecoderMethod = "DecodeJumpTarget"; 608 } 609 610 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 611 Register RetReg>: 612 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 613 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 614 615 class JumpLinkReg<string opstr, RegisterClass RC>: 616 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 617 [], IIBranch, FrmR>; 618 619 class BGEZAL_FT<string opstr, RegisterOperand RO> : 620 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 621 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 622 623} 624 625class BAL_FT : 626 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 627 let isBranch = 1; 628 let isTerminator = 1; 629 let isBarrier = 1; 630 let hasDelaySlot = 1; 631 let Defs = [RA]; 632} 633 634// Sync 635let hasSideEffects = 1 in 636class SYNC_FT : 637 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 638 NoItinerary, FrmOther>; 639 640// Mul, Div 641class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 642 list<Register> DefRegs> : 643 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 644 itin, FrmR, opstr> { 645 let isCommutable = 1; 646 let Defs = DefRegs; 647 let neverHasSideEffects = 1; 648} 649 650// Pseudo multiply/divide instruction with explicit accumulator register 651// operands. 652class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 653 SDPatternOperator OpNode, InstrItinClass Itin, 654 bit IsComm = 1, bit HasSideEffects = 0> : 655 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 656 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 657 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 658 let isCommutable = IsComm; 659 let hasSideEffects = HasSideEffects; 660} 661 662// Pseudo multiply add/sub instruction with explicit accumulator register 663// operands. 664class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 665 : PseudoSE<(outs ACRegs:$ac), 666 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin), 667 [(set ACRegs:$ac, 668 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))], 669 IIImul>, 670 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> { 671 string Constraints = "$acin = $ac"; 672} 673 674class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 675 list<Register> DefRegs> : 676 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 677 [], itin, FrmR> { 678 let Defs = DefRegs; 679} 680 681// Move from Hi/Lo 682class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 683 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 684 let Uses = UseRegs; 685 let neverHasSideEffects = 1; 686} 687 688class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 689 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 690 let Defs = DefRegs; 691 let neverHasSideEffects = 1; 692} 693 694class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 695 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 696 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 697 let isCodeGenOnly = 1; 698 let DecoderMethod = "DecodeMem"; 699} 700 701// Count Leading Ones/Zeros in Word 702class CountLeading0<string opstr, RegisterOperand RO>: 703 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 704 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 705 Requires<[HasBitCount, HasStdEnc]>; 706 707class CountLeading1<string opstr, RegisterOperand RO>: 708 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 709 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 710 Requires<[HasBitCount, HasStdEnc]>; 711 712 713// Sign Extend in Register. 714class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 715 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 716 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 717 let Predicates = [HasSEInReg, HasStdEnc]; 718} 719 720// Subword Swap 721class SubwordSwap<string opstr, RegisterOperand RO>: 722 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 723 NoItinerary, FrmR> { 724 let Predicates = [HasSwap, HasStdEnc]; 725 let neverHasSideEffects = 1; 726} 727 728// Read Hardware 729class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 730 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 731 IIAlu, FrmR>; 732 733// Ext and Ins 734class ExtBase<string opstr, RegisterOperand RO>: 735 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 736 !strconcat(opstr, " $rt, $rs, $pos, $size"), 737 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 738 FrmR> { 739 let Predicates = [HasMips32r2, HasStdEnc]; 740} 741 742class InsBase<string opstr, RegisterOperand RO>: 743 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 744 !strconcat(opstr, " $rt, $rs, $pos, $size"), 745 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 746 NoItinerary, FrmR> { 747 let Predicates = [HasMips32r2, HasStdEnc]; 748 let Constraints = "$src = $rt"; 749} 750 751// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 752class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 753 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 754 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 755 756multiclass Atomic2Ops32<PatFrag Op> { 757 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 758 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 759 Requires<[IsN64, HasStdEnc]> { 760 let DecoderNamespace = "Mips64"; 761 } 762} 763 764// Atomic Compare & Swap. 765class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 766 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 767 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 768 769multiclass AtomicCmpSwap32<PatFrag Op> { 770 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 771 Requires<[NotN64, HasStdEnc]>; 772 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 773 Requires<[IsN64, HasStdEnc]> { 774 let DecoderNamespace = "Mips64"; 775 } 776} 777 778class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 779 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 780 [], NoItinerary, FrmI> { 781 let DecoderMethod = "DecodeMem"; 782 let mayLoad = 1; 783} 784 785class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 786 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 787 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 788 let DecoderMethod = "DecodeMem"; 789 let mayStore = 1; 790 let Constraints = "$rt = $dst"; 791} 792 793class MFC3OP<dag outs, dag ins, string asmstr> : 794 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 795 796//===----------------------------------------------------------------------===// 797// Pseudo instructions 798//===----------------------------------------------------------------------===// 799 800// Return RA. 801let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 802def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 803 804let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 805def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 806 [(callseq_start timm:$amt)]>; 807def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 808 [(callseq_end timm:$amt1, timm:$amt2)]>; 809} 810 811let usesCustomInserter = 1 in { 812 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 813 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 814 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 815 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 816 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 817 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 818 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 819 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 820 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 821 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 822 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 823 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 824 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 825 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 826 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 827 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 828 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 829 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 830 831 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 832 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 833 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 834 835 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 836 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 837 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 838} 839 840/// Pseudo instructions for loading and storing accumulator registers. 841let isPseudo = 1 in { 842 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>; 843 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>; 844} 845 846//===----------------------------------------------------------------------===// 847// Instruction definition 848//===----------------------------------------------------------------------===// 849//===----------------------------------------------------------------------===// 850// MipsI Instructions 851//===----------------------------------------------------------------------===// 852 853/// Arithmetic Instructions (ALU Immediate) 854def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 855 ADDI_FM<0x9>, IsAsCheapAsAMove; 856def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 857def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, 858 SLTI_FM<0xa>; 859def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, 860 SLTI_FM<0xb>; 861def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 862 ADDI_FM<0xc>; 863def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 864 ADDI_FM<0xd>; 865def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 866 ADDI_FM<0xe>; 867def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 868 869/// Arithmetic Instructions (3-Operand, R-Type) 870def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, 871 ADD_FM<0, 0x21>; 872def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, 873 ADD_FM<0, 0x23>; 874def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, 875 ADD_FM<0x1c, 2>; 876def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 877def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 878def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 879def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 880def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, 881 ADD_FM<0, 0x24>; 882def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, 883 ADD_FM<0, 0x25>; 884def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, 885 ADD_FM<0, 0x26>; 886def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 887 888/// Shift Instructions 889def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 890 SRA_FM<0, 0>; 891def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 892 SRA_FM<2, 0>; 893def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 894 SRA_FM<3, 0>; 895def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 896def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 897def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 898 899// Rotate Instructions 900let Predicates = [HasMips32r2, HasStdEnc] in { 901 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, 902 immZExt5>, 903 SRA_FM<2, 1>; 904 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, 905 SRLV_FM<6, 1>; 906} 907 908/// Load and Store Instructions 909/// aligned 910defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>; 911defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>; 912defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>; 913defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>; 914defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>; 915defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>; 916defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>; 917defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>; 918 919/// load/store left/right 920defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 921defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 922defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 923defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 924 925def SYNC : SYNC_FT, SYNC_FM; 926 927/// Load-linked, Store-conditional 928let Predicates = [NotN64, HasStdEnc] in { 929 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 930 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 931} 932 933let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 934 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 935 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 936} 937 938/// Jump and Branch Instructions 939def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 940 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 941def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 942def B : UncondBranch<"b">, B_FM; 943def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 944def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 945def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 946def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 947def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 948def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 949 950def BAL_BR: BAL_FT, BAL_FM; 951 952def JAL : JumpLink<"jal">, FJ<3>; 953def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 954def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 955def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 956def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 957def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 958def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 959 960def RET : RetBase<CPURegs>, MTLO_FM<8>; 961 962// Exception handling related node and instructions. 963// The conversion sequence is: 964// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 965// MIPSeh_return -> (stack change + indirect branch) 966// 967// MIPSeh_return takes the place of regular return instruction 968// but takes two arguments (V1, V0) which are used for storing 969// the offset and return address respectively. 970def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 971 972def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 973 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 974 975let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 976 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 977 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 978 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 979 CPU64Regs:$dst), 980 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 981} 982 983/// Multiply and Divide Instructions. 984def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, 985 MULT_FM<0, 0x18>; 986def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, 987 MULT_FM<0, 0x19>; 988def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>; 989def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>; 990def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>; 991def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>; 992def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 0>; 993def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv, 994 0>; 995 996def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 997def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 998def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 999def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 1000 1001/// Sign Ext In Register Instructions. 1002def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 1003def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 1004 1005/// Count Leading 1006def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 1007def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 1008 1009/// Word Swap Bytes Within Halfwords 1010def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 1011 1012/// No operation. 1013def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1014 1015// FrameIndexes are legalized when they are operands from load/store 1016// instructions. The same not happens for stack address copies, so an 1017// add op with mem ComplexPattern is used and the stack address copy 1018// can be matched. It's similar to Sparc LEA_ADDRi 1019def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 1020 1021// MADD*/MSUB* 1022def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1023def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1024def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1025def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1026def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1027def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1028def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1029def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1030 1031def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 1032 1033def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 1034def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 1035 1036/// Move Control Registers From/To CPU Registers 1037def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1038 (ins CPURegsOpnd:$rd, uimm16:$sel), 1039 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 1040 1041def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1042 (ins CPURegsOpnd:$rt), 1043 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 1044 1045def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1046 (ins CPURegsOpnd:$rd, uimm16:$sel), 1047 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 1048 1049def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1050 (ins CPURegsOpnd:$rt), 1051 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 1052 1053//===----------------------------------------------------------------------===// 1054// Instruction aliases 1055//===----------------------------------------------------------------------===// 1056def : InstAlias<"move $dst, $src", 1057 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1058 Requires<[NotMips64]>; 1059def : InstAlias<"move $dst, $src", 1060 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1061 Requires<[NotMips64]>; 1062def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 1063def : InstAlias<"addu $rs, $rt, $imm", 1064 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1065def : InstAlias<"add $rs, $rt, $imm", 1066 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1067def : InstAlias<"and $rs, $rt, $imm", 1068 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1069def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1070 Requires<[NotMips64]>; 1071def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1072def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1073def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1074 Requires<[NotMips64]>; 1075def : InstAlias<"not $rt, $rs", 1076 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1077def : InstAlias<"neg $rt, $rs", 1078 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1079def : InstAlias<"negu $rt, $rs", 1080 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1081def : InstAlias<"slt $rs, $rt, $imm", 1082 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1083def : InstAlias<"xor $rs, $rt, $imm", 1084 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1085 Requires<[NotMips64]>; 1086def : InstAlias<"or $rs, $rt, $imm", 1087 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1088 Requires<[NotMips64]>; 1089def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1090def : InstAlias<"mfc0 $rt, $rd", 1091 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1092def : InstAlias<"mtc0 $rt, $rd", 1093 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1094def : InstAlias<"mfc2 $rt, $rd", 1095 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1096def : InstAlias<"mtc2 $rt, $rd", 1097 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1098 1099//===----------------------------------------------------------------------===// 1100// Assembler Pseudo Instructions 1101//===----------------------------------------------------------------------===// 1102 1103class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1104 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1105 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1106def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1107 1108class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1109 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1110 !strconcat(instr_asm, "\t$rt, $addr")> ; 1111def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1112 1113class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1114 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1115 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1116def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1117 1118 1119 1120//===----------------------------------------------------------------------===// 1121// Arbitrary patterns that map to one or more instructions 1122//===----------------------------------------------------------------------===// 1123 1124// Load/store pattern templates. 1125class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1126 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1127 1128class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1129 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1130 1131// Small immediates 1132def : MipsPat<(i32 immSExt16:$in), 1133 (ADDiu ZERO, imm:$in)>; 1134def : MipsPat<(i32 immZExt16:$in), 1135 (ORi ZERO, imm:$in)>; 1136def : MipsPat<(i32 immLow16Zero:$in), 1137 (LUi (HI16 imm:$in))>; 1138 1139// Arbitrary immediates 1140def : MipsPat<(i32 imm:$imm), 1141 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1142 1143// Carry MipsPatterns 1144def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1145 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1146let Predicates = [HasStdEnc, NotDSP] in { 1147 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1148 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1149 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1150 (ADDiu CPURegs:$src, imm:$imm)>; 1151} 1152 1153// Call 1154def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1155 (JAL tglobaladdr:$dst)>; 1156def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1157 (JAL texternalsym:$dst)>; 1158//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1159// (JALR CPURegs:$dst)>; 1160 1161// Tail call 1162def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1163 (TAILCALL tglobaladdr:$dst)>; 1164def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1165 (TAILCALL texternalsym:$dst)>; 1166// hi/lo relocs 1167def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1168def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1169def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1170def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1171def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1172def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1173 1174def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1175def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1176def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1177def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1178def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1179def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1180 1181def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1182 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1183def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1184 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1185def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1186 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1187def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1188 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1189def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1190 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1191 1192// gp_rel relocs 1193def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1194 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1195def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1196 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1197 1198// wrapper_pic 1199class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1200 MipsPat<(MipsWrapper RC:$gp, node:$in), 1201 (ADDiuOp RC:$gp, node:$in)>; 1202 1203def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1204def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1205def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1206def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1207def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1208def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1209 1210// Mips does not have "not", so we expand our way 1211def : MipsPat<(not CPURegs:$in), 1212 (NOR CPURegsOpnd:$in, ZERO)>; 1213 1214// extended loads 1215let Predicates = [NotN64, HasStdEnc] in { 1216 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1217 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1218 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1219} 1220let Predicates = [IsN64, HasStdEnc] in { 1221 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1222 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1223 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1224} 1225 1226// peepholes 1227let Predicates = [NotN64, HasStdEnc] in { 1228 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1229} 1230let Predicates = [IsN64, HasStdEnc] in { 1231 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1232} 1233 1234// brcond patterns 1235multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1236 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1237 Instruction SLTiuOp, Register ZEROReg> { 1238def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1239 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1240def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1241 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1242 1243def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1244 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1245def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1246 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1247def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1248 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1249def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1250 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1251 1252def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1253 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1254def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1255 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1256 1257def : MipsPat<(brcond RC:$cond, bb:$dst), 1258 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1259} 1260 1261defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1262 1263// setcc patterns 1264multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1265 Instruction SLTuOp, Register ZEROReg> { 1266 def : MipsPat<(seteq RC:$lhs, 0), 1267 (SLTiuOp RC:$lhs, 1)>; 1268 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1269 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1270 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1271 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1272} 1273 1274multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1275 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1276 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1277 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1278 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1279} 1280 1281multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1282 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1283 (SLTOp RC:$rhs, RC:$lhs)>; 1284 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1285 (SLTuOp RC:$rhs, RC:$lhs)>; 1286} 1287 1288multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1289 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1290 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1291 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1292 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1293} 1294 1295multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1296 Instruction SLTiuOp> { 1297 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1298 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1299 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1300 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1301} 1302 1303defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1304defm : SetlePats<CPURegs, SLT, SLTu>; 1305defm : SetgtPats<CPURegs, SLT, SLTu>; 1306defm : SetgePats<CPURegs, SLT, SLTu>; 1307defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1308 1309// bswap pattern 1310def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1311 1312// mflo/hi patterns. 1313def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)), 1314 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>; 1315 1316// Load halfword/word patterns. 1317let AddedComplexity = 40 in { 1318 let Predicates = [NotN64, HasStdEnc] in { 1319 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1320 def : LoadRegImmPat<LH, i32, sextloadi16>; 1321 def : LoadRegImmPat<LW, i32, load>; 1322 } 1323 let Predicates = [IsN64, HasStdEnc] in { 1324 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>; 1325 def : LoadRegImmPat<LH_P8, i32, sextloadi16>; 1326 def : LoadRegImmPat<LW_P8, i32, load>; 1327 } 1328} 1329 1330//===----------------------------------------------------------------------===// 1331// Floating Point Support 1332//===----------------------------------------------------------------------===// 1333 1334include "MipsInstrFPU.td" 1335include "Mips64InstrInfo.td" 1336include "MipsCondMov.td" 1337 1338// 1339// Mips16 1340 1341include "Mips16InstrFormats.td" 1342include "Mips16InstrInfo.td" 1343 1344// DSP 1345include "MipsDSPInstrFormats.td" 1346include "MipsDSPInstrInfo.td" 1347 1348// Micromips 1349include "MicroMipsInstrFormats.td" 1350include "MicroMipsInstrInfo.td" 1351