MipsInstrInfo.td revision bf19dba2d4c7927832d3037c15e0101afb730415
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 36def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 37 38def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 39 40def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 41 42def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 44def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 46 SDTCisSameAs<0, 4>]>; 47 48def SDTMipsLoadLR : SDTypeProfile<1, 2, 49 [SDTCisInt<0>, SDTCisPtrTy<1>, 50 SDTCisSameAs<0, 2>]>; 51 52// Call 53def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 55 SDNPVariadic]>; 56 57// Tail call 58def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 60 61// Hi and Lo nodes are used to handle global addresses. Used on 62// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 63// static model. (nothing to do with Mips Registers Hi and Lo) 64def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 65def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 66def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 67 68// TlsGd node is used to handle General Dynamic TLS 69def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 70 71// TprelHi and TprelLo nodes are used to handle Local Exec TLS 72def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 73def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 74 75// Thread pointer 76def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 77 78// Return 79def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 81 82// These are target-independent nodes, but have target-specific formats. 83def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 85def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 86 [SDNPHasChain, SDNPSideEffect, 87 SDNPOptInGlue, SDNPOutGlue]>; 88 89// Node used to extract integer from LO/HI register. 90def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, 186 AssemblerPredicate<"FeatureMicroMips">; 187def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, 188 AssemblerPredicate<"!FeatureMicroMips">; 189def IsLE : Predicate<"Subtarget.isLittle()">; 190def IsBE : Predicate<"!Subtarget.isLittle()">; 191 192class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 193 let Predicates = [HasStdEnc]; 194} 195 196class IsCommutable { 197 bit isCommutable = 1; 198} 199 200class IsBranch { 201 bit isBranch = 1; 202} 203 204class IsReturn { 205 bit isReturn = 1; 206} 207 208class IsCall { 209 bit isCall = 1; 210} 211 212class IsTailCall { 213 bit isCall = 1; 214 bit isTerminator = 1; 215 bit isReturn = 1; 216 bit isBarrier = 1; 217 bit hasExtraSrcRegAllocReq = 1; 218 bit isCodeGenOnly = 1; 219} 220 221class IsAsCheapAsAMove { 222 bit isAsCheapAsAMove = 1; 223} 224 225class NeverHasSideEffects { 226 bit neverHasSideEffects = 1; 227} 228 229//===----------------------------------------------------------------------===// 230// Instruction format superclass 231//===----------------------------------------------------------------------===// 232 233include "MipsInstrFormats.td" 234 235//===----------------------------------------------------------------------===// 236// Mips Operand, Complex Patterns and Transformations Definitions. 237//===----------------------------------------------------------------------===// 238 239// Instruction operand types 240def jmptarget : Operand<OtherVT> { 241 let EncoderMethod = "getJumpTargetOpValue"; 242} 243def brtarget : Operand<OtherVT> { 244 let EncoderMethod = "getBranchTargetOpValue"; 245 let OperandType = "OPERAND_PCREL"; 246 let DecoderMethod = "DecodeBranchTarget"; 247} 248def calltarget : Operand<iPTR> { 249 let EncoderMethod = "getJumpTargetOpValue"; 250} 251def calltarget64: Operand<i64>; 252def simm16 : Operand<i32> { 253 let DecoderMethod= "DecodeSimm16"; 254} 255 256def simm20 : Operand<i32> { 257} 258 259def uimm20 : Operand<i32> { 260} 261 262def uimm10 : Operand<i32> { 263} 264 265def simm16_64 : Operand<i64>; 266def shamt : Operand<i32>; 267 268// Unsigned Operand 269def uimm5 : Operand<i32> { 270 let PrintMethod = "printUnsignedImm"; 271} 272 273def uimm16 : Operand<i32> { 274 let PrintMethod = "printUnsignedImm"; 275} 276 277def MipsMemAsmOperand : AsmOperandClass { 278 let Name = "Mem"; 279 let ParserMethod = "parseMemOperand"; 280} 281 282// Address operand 283def mem : Operand<iPTR> { 284 let PrintMethod = "printMemOperand"; 285 let MIOperandInfo = (ops ptr_rc, simm16); 286 let EncoderMethod = "getMemEncoding"; 287 let ParserMatchClass = MipsMemAsmOperand; 288 let OperandType = "OPERAND_MEMORY"; 289} 290 291def mem_ea : Operand<iPTR> { 292 let PrintMethod = "printMemOperandEA"; 293 let MIOperandInfo = (ops ptr_rc, simm16); 294 let EncoderMethod = "getMemEncoding"; 295 let OperandType = "OPERAND_MEMORY"; 296} 297 298def PtrRC : Operand<iPTR> { 299 let MIOperandInfo = (ops ptr_rc); 300} 301 302// size operand of ext instruction 303def size_ext : Operand<i32> { 304 let EncoderMethod = "getSizeExtEncoding"; 305 let DecoderMethod = "DecodeExtSize"; 306} 307 308// size operand of ins instruction 309def size_ins : Operand<i32> { 310 let EncoderMethod = "getSizeInsEncoding"; 311 let DecoderMethod = "DecodeInsSize"; 312} 313 314// Transformation Function - get the lower 16 bits. 315def LO16 : SDNodeXForm<imm, [{ 316 return getImm(N, N->getZExtValue() & 0xFFFF); 317}]>; 318 319// Transformation Function - get the higher 16 bits. 320def HI16 : SDNodeXForm<imm, [{ 321 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 322}]>; 323 324// Plus 1. 325def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 326 327// Node immediate fits as 16-bit sign extended on target immediate. 328// e.g. addi, andi 329def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 330 331// Node immediate fits as 16-bit sign extended on target immediate. 332// e.g. addi, andi 333def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 334 335// Node immediate fits as 15-bit sign extended on target immediate. 336// e.g. addi, andi 337def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 338 339// Node immediate fits as 16-bit zero extended on target immediate. 340// The LO16 param means that only the lower 16 bits of the node 341// immediate are caught. 342// e.g. addiu, sltiu 343def immZExt16 : PatLeaf<(imm), [{ 344 if (N->getValueType(0) == MVT::i32) 345 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 346 else 347 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 348}], LO16>; 349 350// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 351def immLow16Zero : PatLeaf<(imm), [{ 352 int64_t Val = N->getSExtValue(); 353 return isInt<32>(Val) && !(Val & 0xffff); 354}]>; 355 356// shamt field must fit in 5 bits. 357def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 358 359// True if (N + 1) fits in 16-bit field. 360def immSExt16Plus1 : PatLeaf<(imm), [{ 361 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 362}]>; 363 364// Mips Address Mode! SDNode frameindex could possibily be a match 365// since load and store instructions from stack used it. 366def addr : 367 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 368 369def addrRegImm : 370 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 371 372def addrDefault : 373 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 374 375//===----------------------------------------------------------------------===// 376// Instructions specific format 377//===----------------------------------------------------------------------===// 378 379// Arithmetic and logical instructions with 3 register operands. 380class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 381 InstrItinClass Itin = NoItinerary, 382 SDPatternOperator OpNode = null_frag>: 383 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 384 !strconcat(opstr, "\t$rd, $rs, $rt"), 385 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 386 let isCommutable = isComm; 387 let isReMaterializable = 1; 388} 389 390// Arithmetic and logical instructions with 2 register operands. 391class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 392 InstrItinClass Itin = NoItinerary, 393 SDPatternOperator imm_type = null_frag, 394 SDPatternOperator OpNode = null_frag> : 395 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 396 !strconcat(opstr, "\t$rt, $rs, $imm16"), 397 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 398 Itin, FrmI, opstr> { 399 let isReMaterializable = 1; 400 let TwoOperandAliasConstraint = "$rs = $rt"; 401} 402 403// Arithmetic Multiply ADD/SUB 404class MArithR<string opstr, bit isComm = 0> : 405 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 406 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> { 407 let Defs = [HI0, LO0]; 408 let Uses = [HI0, LO0]; 409 let isCommutable = isComm; 410} 411 412// Logical 413class LogicNOR<string opstr, RegisterOperand RO>: 414 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 415 !strconcat(opstr, "\t$rd, $rs, $rt"), 416 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> { 417 let isCommutable = 1; 418} 419 420// Shifts 421class shift_rotate_imm<string opstr, Operand ImmOpnd, 422 RegisterOperand RO, SDPatternOperator OpNode = null_frag, 423 SDPatternOperator PF = null_frag> : 424 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 425 !strconcat(opstr, "\t$rd, $rt, $shamt"), 426 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>; 427 428class shift_rotate_reg<string opstr, RegisterOperand RO, 429 SDPatternOperator OpNode = null_frag>: 430 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 431 !strconcat(opstr, "\t$rd, $rt, $rs"), 432 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>; 433 434// Load Upper Imediate 435class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 436 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 437 [], IIArith, FrmI>, IsAsCheapAsAMove { 438 let neverHasSideEffects = 1; 439 let isReMaterializable = 1; 440} 441 442class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 443 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 444 bits<21> addr; 445 let Inst{25-21} = addr{20-16}; 446 let Inst{15-0} = addr{15-0}; 447 let DecoderMethod = "DecodeMem"; 448} 449 450// Memory Load/Store 451class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 452 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 453 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 454 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, opstr> { 455 let DecoderMethod = "DecodeMem"; 456 let canFoldAsLoad = 1; 457 let mayLoad = 1; 458} 459 460class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 461 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 462 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 463 [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI, opstr> { 464 let DecoderMethod = "DecodeMem"; 465 let mayStore = 1; 466} 467 468// Load/Store Left/Right 469let canFoldAsLoad = 1 in 470class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> : 471 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 472 !strconcat(opstr, "\t$rt, $addr"), 473 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> { 474 let DecoderMethod = "DecodeMem"; 475 string Constraints = "$src = $rt"; 476} 477 478class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> : 479 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 480 [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> { 481 let DecoderMethod = "DecodeMem"; 482} 483 484// Conditional Branch 485class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> : 486 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset), 487 !strconcat(opstr, "\t$rs, $rt, $offset"), 488 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 489 FrmI> { 490 let isBranch = 1; 491 let isTerminator = 1; 492 let hasDelaySlot = 1; 493 let Defs = [AT]; 494} 495 496class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> : 497 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 498 !strconcat(opstr, "\t$rs, $offset"), 499 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 500 let isBranch = 1; 501 let isTerminator = 1; 502 let hasDelaySlot = 1; 503 let Defs = [AT]; 504} 505 506// SetCC 507class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 508 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 509 !strconcat(opstr, "\t$rd, $rs, $rt"), 510 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 511 IIslt, FrmR, opstr>; 512 513class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 514 RegisterOperand RO>: 515 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 516 !strconcat(opstr, "\t$rt, $rs, $imm16"), 517 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 518 IIslt, FrmI, opstr>; 519 520// Jump 521class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 522 SDPatternOperator targetoperator> : 523 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 524 [(operator targetoperator:$target)], IIBranch, FrmJ> { 525 let isTerminator=1; 526 let isBarrier=1; 527 let hasDelaySlot = 1; 528 let DecoderMethod = "DecodeJumpTarget"; 529 let Defs = [AT]; 530} 531 532// Unconditional branch 533class UncondBranch<string opstr> : 534 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 535 [(br bb:$offset)], IIBranch, FrmI> { 536 let isBranch = 1; 537 let isTerminator = 1; 538 let isBarrier = 1; 539 let hasDelaySlot = 1; 540 let Predicates = [RelocPIC, HasStdEnc]; 541 let Defs = [AT]; 542} 543 544// Base class for indirect branch and return instruction classes. 545let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 546class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>: 547 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>; 548 549// Indirect branch 550class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> { 551 let isBranch = 1; 552 let isIndirectBranch = 1; 553} 554 555// Return instruction 556class RetBase<RegisterOperand RO>: JumpFR<RO> { 557 let isReturn = 1; 558 let isCodeGenOnly = 1; 559 let hasCtrlDep = 1; 560 let hasExtraSrcRegAllocReq = 1; 561} 562 563// Jump and Link (Call) 564let isCall=1, hasDelaySlot=1, Defs = [RA] in { 565 class JumpLink<string opstr> : 566 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 567 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 568 let DecoderMethod = "DecodeJumpTarget"; 569 } 570 571 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 572 Register RetReg, RegisterOperand ResRO = RO>: 573 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 574 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 575 576 class JumpLinkReg<string opstr, RegisterOperand RO>: 577 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 578 [], IIBranch, FrmR>; 579 580 class BGEZAL_FT<string opstr, RegisterOperand RO> : 581 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 582 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 583 584} 585 586class BAL_BR_Pseudo<Instruction RealInst> : 587 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 588 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 589 let isBranch = 1; 590 let isTerminator = 1; 591 let isBarrier = 1; 592 let hasDelaySlot = 1; 593 let Defs = [RA]; 594} 595 596// Syscall 597class SYS_FT<string opstr> : 598 InstSE<(outs), (ins uimm20:$code_), 599 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; 600// Break 601class BRK_FT<string opstr> : 602 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 603 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; 604 605// (D)Eret 606class ER_FT<string opstr> : 607 InstSE<(outs), (ins), 608 opstr, [], NoItinerary, FrmOther>; 609 610// Interrupts 611class DEI_FT<string opstr, RegisterOperand RO> : 612 InstSE<(outs RO:$rt), (ins), 613 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>; 614 615// Wait 616class WAIT_FT<string opstr> : 617 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> { 618 let Inst{31-26} = 0x10; 619 let Inst{25} = 1; 620 let Inst{24-6} = 0; 621 let Inst{5-0} = 0x20; 622} 623 624// Sync 625let hasSideEffects = 1 in 626class SYNC_FT : 627 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 628 NoItinerary, FrmOther>; 629 630let hasSideEffects = 1 in 631class TEQ_FT<string opstr, RegisterOperand RO> : 632 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 633 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; 634 635class TEQI_FT<string opstr, RegisterOperand RO> : 636 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 637 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>; 638// Mul, Div 639class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 640 list<Register> DefRegs> : 641 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 642 itin, FrmR, opstr> { 643 let isCommutable = 1; 644 let Defs = DefRegs; 645 let neverHasSideEffects = 1; 646} 647 648// Pseudo multiply/divide instruction with explicit accumulator register 649// operands. 650class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 651 SDPatternOperator OpNode, InstrItinClass Itin, 652 bit IsComm = 1, bit HasSideEffects = 0, 653 bit UsesCustomInserter = 0> : 654 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 655 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 656 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 657 let isCommutable = IsComm; 658 let hasSideEffects = HasSideEffects; 659 let usesCustomInserter = UsesCustomInserter; 660} 661 662// Pseudo multiply add/sub instruction with explicit accumulator register 663// operands. 664class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 665 : PseudoSE<(outs ACC64:$ac), 666 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 667 [(set ACC64:$ac, 668 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 669 IIImult>, 670 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 671 string Constraints = "$acin = $ac"; 672} 673 674class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 675 list<Register> DefRegs> : 676 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 677 [], itin, FrmR> { 678 let Defs = DefRegs; 679} 680 681// Move from Hi/Lo 682class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>: 683 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 684 let Uses = UseRegs; 685 let neverHasSideEffects = 1; 686} 687 688class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 689 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 690 let Defs = DefRegs; 691 let neverHasSideEffects = 1; 692} 693 694class EffectiveAddress<string opstr, RegisterOperand RO> : 695 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 696 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> { 697 let isCodeGenOnly = 1; 698 let DecoderMethod = "DecodeMem"; 699} 700 701// Count Leading Ones/Zeros in Word 702class CountLeading0<string opstr, RegisterOperand RO>: 703 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 704 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>, 705 Requires<[HasBitCount, HasStdEnc]>; 706 707class CountLeading1<string opstr, RegisterOperand RO>: 708 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 709 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>, 710 Requires<[HasBitCount, HasStdEnc]>; 711 712 713// Sign Extend in Register. 714class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> : 715 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 716 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> { 717 let Predicates = [HasSEInReg, HasStdEnc]; 718} 719 720// Subword Swap 721class SubwordSwap<string opstr, RegisterOperand RO>: 722 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 723 NoItinerary, FrmR> { 724 let Predicates = [HasSwap, HasStdEnc]; 725 let neverHasSideEffects = 1; 726} 727 728// Read Hardware 729class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 730 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 731 IIArith, FrmR>; 732 733// Ext and Ins 734class ExtBase<string opstr, RegisterOperand RO>: 735 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 736 !strconcat(opstr, " $rt, $rs, $pos, $size"), 737 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 738 FrmR> { 739 let Predicates = [HasMips32r2, HasStdEnc]; 740} 741 742class InsBase<string opstr, RegisterOperand RO>: 743 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 744 !strconcat(opstr, " $rt, $rs, $pos, $size"), 745 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 746 NoItinerary, FrmR> { 747 let Predicates = [HasMips32r2, HasStdEnc]; 748 let Constraints = "$src = $rt"; 749} 750 751// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 752class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 753 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 754 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 755 756// Atomic Compare & Swap. 757class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 758 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 759 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 760 761class LLBase<string opstr, RegisterOperand RO> : 762 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 763 [], NoItinerary, FrmI> { 764 let DecoderMethod = "DecodeMem"; 765 let mayLoad = 1; 766} 767 768class SCBase<string opstr, RegisterOperand RO> : 769 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 770 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 771 let DecoderMethod = "DecodeMem"; 772 let mayStore = 1; 773 let Constraints = "$rt = $dst"; 774} 775 776class MFC3OP<string asmstr, RegisterOperand RO> : 777 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 778 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 779 780let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in 781def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> { 782 let Inst = 0x0000000d; 783} 784 785//===----------------------------------------------------------------------===// 786// Pseudo instructions 787//===----------------------------------------------------------------------===// 788 789// Return RA. 790let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 791def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 792 793let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 794def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 795 [(callseq_start timm:$amt)]>; 796def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 797 [(callseq_end timm:$amt1, timm:$amt2)]>; 798} 799 800let usesCustomInserter = 1 in { 801 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 802 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 803 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 804 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 805 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 806 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 807 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 808 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 809 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 810 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 811 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 812 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 813 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 814 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 815 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 816 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 817 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 818 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 819 820 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 821 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 822 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 823 824 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 825 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 826 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 827} 828 829/// Pseudo instructions for loading and storing accumulator registers. 830let isPseudo = 1, isCodeGenOnly = 1 in { 831 def LOAD_ACC64 : Load<"", ACC64>; 832 def STORE_ACC64 : Store<"", ACC64>; 833} 834 835//===----------------------------------------------------------------------===// 836// Instruction definition 837//===----------------------------------------------------------------------===// 838//===----------------------------------------------------------------------===// 839// MipsI Instructions 840//===----------------------------------------------------------------------===// 841 842/// Arithmetic Instructions (ALU Immediate) 843def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16, 844 add>, 845 ADDI_FM<0x9>, IsAsCheapAsAMove; 846def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>; 847def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 848 SLTI_FM<0xa>; 849def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 850 SLTI_FM<0xb>; 851def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16, 852 and>, 853 ADDI_FM<0xc>; 854def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16, 855 or>, 856 ADDI_FM<0xd>; 857def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16, 858 xor>, 859 ADDI_FM<0xe>; 860def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 861 862/// Arithmetic Instructions (3-Operand, R-Type) 863def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>, 864 ADD_FM<0, 0x21>; 865def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>, 866 ADD_FM<0, 0x23>; 867def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>, 868 ADD_FM<0x1c, 2>; 869def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 870def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 871def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 872def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 873def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>, 874 ADD_FM<0, 0x24>; 875def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>, 876 ADD_FM<0, 0x25>; 877def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>, 878 ADD_FM<0, 0x26>; 879def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 880 881/// Shift Instructions 882def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>, 883 SRA_FM<0, 0>; 884def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>, 885 SRA_FM<2, 0>; 886def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>, 887 SRA_FM<3, 0>; 888def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>; 889def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>; 890def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>; 891 892// Rotate Instructions 893let Predicates = [HasMips32r2, HasStdEnc] in { 894 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr, 895 immZExt5>, 896 SRA_FM<2, 1>; 897 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>, 898 SRLV_FM<6, 1>; 899} 900 901/// Load and Store Instructions 902/// aligned 903def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>; 904def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel, 905 LW_FM<0x24>; 906def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel, 907 LW_FM<0x21>; 908def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; 909def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, 910 LW_FM<0x23>; 911def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; 912def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; 913def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; 914 915/// load/store left/right 916def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>; 917def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>; 918def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>; 919def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>; 920 921def SYNC : SYNC_FT, SYNC_FM; 922def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 923def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; 924def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; 925def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; 926def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; 927def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; 928 929def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>; 930def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>; 931def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>; 932def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>; 933def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>; 934def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>; 935 936def BREAK : BRK_FT<"break">, BRK_FM<0xd>; 937def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; 938 939def ERET : ER_FT<"eret">, ER_FM<0x18>; 940def DERET : ER_FT<"deret">, ER_FM<0x1f>; 941 942def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; 943def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>; 944 945def WAIT : WAIT_FT<"wait">; 946 947/// Load-linked, Store-conditional 948def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>; 949def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>; 950 951/// Jump and Branch Instructions 952def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 953 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 954def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>; 955def B : UncondBranch<"b">, B_FM; 956def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>; 957def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>; 958def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>; 959def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>; 960def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>; 961def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>; 962 963def JAL : JumpLink<"jal">, FJ<3>; 964def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 965def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 966def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>; 967def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>; 968def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 969def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 970def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall; 971 972def RET : RetBase<GPR32Opnd>, MTLO_FM<8>; 973 974// Exception handling related node and instructions. 975// The conversion sequence is: 976// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 977// MIPSeh_return -> (stack change + indirect branch) 978// 979// MIPSeh_return takes the place of regular return instruction 980// but takes two arguments (V1, V0) which are used for storing 981// the offset and return address respectively. 982def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 983 984def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 985 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 986 987let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 988 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 989 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 990 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 991 GPR64:$dst), 992 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 993} 994 995/// Multiply and Divide Instructions. 996def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>, 997 MULT_FM<0, 0x18>; 998def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>, 999 MULT_FM<0, 0x19>; 1000def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; 1001def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; 1002def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>; 1003def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>; 1004def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, 1005 0, 1, 1>; 1006def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, 1007 0, 1, 1>; 1008 1009def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; 1010def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; 1011def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>; 1012def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>; 1013 1014/// Sign Ext In Register Instructions. 1015def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; 1016def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; 1017 1018/// Count Leading 1019def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; 1020def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; 1021 1022/// Word Swap Bytes Within Halfwords 1023def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; 1024 1025/// No operation. 1026def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1027 1028// FrameIndexes are legalized when they are operands from load/store 1029// instructions. The same not happens for stack address copies, so an 1030// add op with mem ComplexPattern is used and the stack address copy 1031// can be matched. It's similar to Sparc LEA_ADDRi 1032def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1033 1034// MADD*/MSUB* 1035def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1036def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1037def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1038def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1039def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1040def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1041def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1042def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1043 1044def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1045 1046def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>; 1047def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>; 1048 1049/// Move Control Registers From/To CPU Registers 1050def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>; 1051def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>; 1052def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1053def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1054 1055//===----------------------------------------------------------------------===// 1056// Instruction aliases 1057//===----------------------------------------------------------------------===// 1058def : InstAlias<"move $dst, $src", 1059 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1060 Requires<[NotMips64]>; 1061def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; 1062def : InstAlias<"addu $rs, $rt, $imm", 1063 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1064def : InstAlias<"add $rs, $rt, $imm", 1065 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1066def : InstAlias<"and $rs, $rt, $imm", 1067 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1068def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1069def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1070def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1071def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1072def : InstAlias<"not $rt, $rs", 1073 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1074def : InstAlias<"neg $rt, $rs", 1075 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1076def : InstAlias<"negu $rt, $rs", 1077 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1078def : InstAlias<"slt $rs, $rt, $imm", 1079 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1080def : InstAlias<"xor $rs, $rt, $imm", 1081 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1082def : InstAlias<"or $rs, $rt, $imm", 1083 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1084def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1085def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1086def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1087def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1088def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1089def : InstAlias<"bnez $rs,$offset", 1090 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1091def : InstAlias<"beqz $rs,$offset", 1092 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1093def : InstAlias<"syscall", (SYSCALL 0), 1>; 1094 1095def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1096def : InstAlias<"break", (BREAK 0, 0), 1>; 1097def : InstAlias<"ei", (EI ZERO), 1>; 1098def : InstAlias<"di", (DI ZERO), 1>; 1099 1100def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1101def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1102def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1103def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1104def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1105def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1106//===----------------------------------------------------------------------===// 1107// Assembler Pseudo Instructions 1108//===----------------------------------------------------------------------===// 1109 1110class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1111 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1112 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1113def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>; 1114 1115class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1116 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1117 !strconcat(instr_asm, "\t$rt, $addr")> ; 1118def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1119 1120class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1121 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1122 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1123def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>; 1124 1125 1126 1127//===----------------------------------------------------------------------===// 1128// Arbitrary patterns that map to one or more instructions 1129//===----------------------------------------------------------------------===// 1130 1131// Load/store pattern templates. 1132class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1133 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1134 1135class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1136 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1137 1138// Small immediates 1139def : MipsPat<(i32 immSExt16:$in), 1140 (ADDiu ZERO, imm:$in)>; 1141def : MipsPat<(i32 immZExt16:$in), 1142 (ORi ZERO, imm:$in)>; 1143def : MipsPat<(i32 immLow16Zero:$in), 1144 (LUi (HI16 imm:$in))>; 1145 1146// Arbitrary immediates 1147def : MipsPat<(i32 imm:$imm), 1148 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1149 1150// Carry MipsPatterns 1151def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1152 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1153let Predicates = [HasStdEnc, NotDSP] in { 1154 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1155 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1156 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1157 (ADDiu GPR32:$src, imm:$imm)>; 1158} 1159 1160// Call 1161def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1162 (JAL tglobaladdr:$dst)>; 1163def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1164 (JAL texternalsym:$dst)>; 1165//def : MipsPat<(MipsJmpLink GPR32:$dst), 1166// (JALR GPR32:$dst)>; 1167 1168// Tail call 1169def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1170 (TAILCALL tglobaladdr:$dst)>; 1171def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1172 (TAILCALL texternalsym:$dst)>; 1173// hi/lo relocs 1174def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1175def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1176def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1177def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1178def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1179def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1180 1181def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1182def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1183def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1184def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1185def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1186def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1187 1188def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1189 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1190def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1191 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1192def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1193 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1194def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1195 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1196def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1197 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1198 1199// gp_rel relocs 1200def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1201 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1202def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1203 (ADDiu GPR32:$gp, tconstpool:$in)>; 1204 1205// wrapper_pic 1206class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1207 MipsPat<(MipsWrapper RC:$gp, node:$in), 1208 (ADDiuOp RC:$gp, node:$in)>; 1209 1210def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1211def : WrapperPat<tconstpool, ADDiu, GPR32>; 1212def : WrapperPat<texternalsym, ADDiu, GPR32>; 1213def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1214def : WrapperPat<tjumptable, ADDiu, GPR32>; 1215def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1216 1217// Mips does not have "not", so we expand our way 1218def : MipsPat<(not GPR32:$in), 1219 (NOR GPR32Opnd:$in, ZERO)>; 1220 1221// extended loads 1222let Predicates = [HasStdEnc] in { 1223 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1224 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1225 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1226} 1227 1228// peepholes 1229let Predicates = [HasStdEnc] in 1230def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1231 1232// brcond patterns 1233multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1234 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1235 Instruction SLTiuOp, Register ZEROReg> { 1236def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1237 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1238def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1239 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1240 1241def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1242 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1243def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1244 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1245def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1246 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1247def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1248 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1249def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1250 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1251def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1252 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1253 1254def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1255 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1256def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1257 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1258 1259def : MipsPat<(brcond RC:$cond, bb:$dst), 1260 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1261} 1262 1263defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1264 1265def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1266 (BLEZ i32:$lhs, bb:$dst)>; 1267def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1268 (BGEZ i32:$lhs, bb:$dst)>; 1269 1270// setcc patterns 1271multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1272 Instruction SLTuOp, Register ZEROReg> { 1273 def : MipsPat<(seteq RC:$lhs, 0), 1274 (SLTiuOp RC:$lhs, 1)>; 1275 def : MipsPat<(setne RC:$lhs, 0), 1276 (SLTuOp ZEROReg, RC:$lhs)>; 1277 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1278 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1279 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1280 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1281} 1282 1283multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1284 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1285 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1286 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1287 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1288} 1289 1290multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1291 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1292 (SLTOp RC:$rhs, RC:$lhs)>; 1293 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1294 (SLTuOp RC:$rhs, RC:$lhs)>; 1295} 1296 1297multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1298 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1299 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1300 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1301 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1302} 1303 1304multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1305 Instruction SLTiuOp> { 1306 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1307 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1308 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1309 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1310} 1311 1312defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1313defm : SetlePats<GPR32, SLT, SLTu>; 1314defm : SetgtPats<GPR32, SLT, SLTu>; 1315defm : SetgePats<GPR32, SLT, SLTu>; 1316defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1317 1318// bswap pattern 1319def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1320 1321// mflo/hi patterns. 1322def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)), 1323 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>; 1324 1325// Load halfword/word patterns. 1326let AddedComplexity = 40 in { 1327 let Predicates = [HasStdEnc] in { 1328 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1329 def : LoadRegImmPat<LH, i32, sextloadi16>; 1330 def : LoadRegImmPat<LW, i32, load>; 1331 } 1332} 1333 1334//===----------------------------------------------------------------------===// 1335// Floating Point Support 1336//===----------------------------------------------------------------------===// 1337 1338include "MipsInstrFPU.td" 1339include "Mips64InstrInfo.td" 1340include "MipsCondMov.td" 1341 1342// 1343// Mips16 1344 1345include "Mips16InstrFormats.td" 1346include "Mips16InstrInfo.td" 1347 1348// DSP 1349include "MipsDSPInstrFormats.td" 1350include "MipsDSPInstrInfo.td" 1351 1352// MSA 1353include "MipsMSAInstrFormats.td" 1354include "MipsMSAInstrInfo.td" 1355 1356// Micromips 1357include "MicroMipsInstrFormats.td" 1358include "MicroMipsInstrInfo.td" 1359