MipsInstrInfo.td revision cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 16-bit zero extended on target immediate. 302// The LO16 param means that only the lower 16 bits of the node 303// immediate are caught. 304// e.g. addiu, sltiu 305def immZExt16 : PatLeaf<(imm), [{ 306 if (N->getValueType(0) == MVT::i32) 307 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 308 else 309 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 310}], LO16>; 311 312// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 313def immLow16Zero : PatLeaf<(imm), [{ 314 int64_t Val = N->getSExtValue(); 315 return isInt<32>(Val) && !(Val & 0xffff); 316}]>; 317 318// shamt field must fit in 5 bits. 319def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 320 321// Mips Address Mode! SDNode frameindex could possibily be a match 322// since load and store instructions from stack used it. 323def addr : 324 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 325 326//===----------------------------------------------------------------------===// 327// Instructions specific format 328//===----------------------------------------------------------------------===// 329 330/// Move Control Registers From/To CPU Registers 331def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 332 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 333def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 334 335def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 336 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 337def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 338 339def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 340 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 341def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 342 343def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 344 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 345def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 346 347// Arithmetic and logical instructions with 3 register operands. 348class ArithLogicR<string opstr, InstrItinClass Itin, RegisterClass RC, 349 bit isComm = 0, SDPatternOperator OpNode = null_frag>: 350 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 351 !strconcat(opstr, "\t$rd, $rs, $rt"), 352 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 353 let isCommutable = isComm; 354 let isReMaterializable = 1; 355} 356 357// Arithmetic and logical instructions with 2 register operands. 358class ArithLogicI<string opstr, Operand Od, PatLeaf imm_type, 359 RegisterClass RC, SDPatternOperator OpNode = null_frag> : 360 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 361 !strconcat(opstr, "\t$rt, $rs, $imm16"), 362 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 363 let isReMaterializable = 1; 364} 365 366// Arithmetic Multiply ADD/SUB 367let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 368class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 369 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 370 !strconcat(instr_asm, "\t$rs, $rt"), 371 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 372 let rd = 0; 373 let shamt = 0; 374 let isCommutable = isComm; 375} 376 377// Logical 378class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 379 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 380 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 381 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 382 let shamt = 0; 383 let isCommutable = 1; 384} 385 386// Shifts 387class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd, 388 RegisterClass RC, SDPatternOperator OpNode> : 389 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 390 !strconcat(opstr, "\t$rd, $rt, $shamt"), 391 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 392 393// 32-bit shift instructions. 394class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> : 395 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>; 396 397class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>: 398 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 399 !strconcat(opstr, "\t$rd, $rt, $rs"), 400 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; 401 402// Load Upper Imediate 403class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 404 FI<op, (outs RC:$rt), (ins Imm:$imm16), 405 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { 406 let rs = 0; 407 let neverHasSideEffects = 1; 408 let isReMaterializable = 1; 409} 410 411class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 412 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 413 bits<21> addr; 414 let Inst{25-21} = addr{20-16}; 415 let Inst{15-0} = addr{15-0}; 416 let DecoderMethod = "DecodeMem"; 417} 418 419// Memory Load/Store 420let canFoldAsLoad = 1 in 421class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 422 Operand MemOpnd, bit Pseudo>: 423 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 424 !strconcat(instr_asm, "\t$rt, $addr"), 425 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 426 let isPseudo = Pseudo; 427} 428 429class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 430 Operand MemOpnd, bit Pseudo>: 431 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 432 !strconcat(instr_asm, "\t$rt, $addr"), 433 [(OpNode RC:$rt, addr:$addr)], IIStore> { 434 let isPseudo = Pseudo; 435} 436 437// 32-bit load. 438multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 439 bit Pseudo = 0> { 440 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 441 Requires<[NotN64, HasStdEnc]>; 442 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 443 Requires<[IsN64, HasStdEnc]> { 444 let DecoderNamespace = "Mips64"; 445 let isCodeGenOnly = 1; 446 } 447} 448 449// 64-bit load. 450multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 451 bit Pseudo = 0> { 452 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 453 Requires<[NotN64, HasStdEnc]>; 454 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 455 Requires<[IsN64, HasStdEnc]> { 456 let DecoderNamespace = "Mips64"; 457 let isCodeGenOnly = 1; 458 } 459} 460 461// 32-bit store. 462multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 463 bit Pseudo = 0> { 464 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 465 Requires<[NotN64, HasStdEnc]>; 466 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 467 Requires<[IsN64, HasStdEnc]> { 468 let DecoderNamespace = "Mips64"; 469 let isCodeGenOnly = 1; 470 } 471} 472 473// 64-bit store. 474multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 475 bit Pseudo = 0> { 476 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 477 Requires<[NotN64, HasStdEnc]>; 478 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 479 Requires<[IsN64, HasStdEnc]> { 480 let DecoderNamespace = "Mips64"; 481 let isCodeGenOnly = 1; 482 } 483} 484 485// Load/Store Left/Right 486let canFoldAsLoad = 1 in 487class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 488 RegisterClass RC, Operand MemOpnd> : 489 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 490 !strconcat(instr_asm, "\t$rt, $addr"), 491 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 492 string Constraints = "$src = $rt"; 493} 494 495class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 496 RegisterClass RC, Operand MemOpnd>: 497 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 498 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 499 IIStore>; 500 501// 32-bit load left/right. 502multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 503 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 504 Requires<[NotN64, HasStdEnc]>; 505 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 506 Requires<[IsN64, HasStdEnc]> { 507 let DecoderNamespace = "Mips64"; 508 let isCodeGenOnly = 1; 509 } 510} 511 512// 64-bit load left/right. 513multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 514 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 515 Requires<[NotN64, HasStdEnc]>; 516 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 517 Requires<[IsN64, HasStdEnc]> { 518 let DecoderNamespace = "Mips64"; 519 let isCodeGenOnly = 1; 520 } 521} 522 523// 32-bit store left/right. 524multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 525 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 526 Requires<[NotN64, HasStdEnc]>; 527 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 528 Requires<[IsN64, HasStdEnc]> { 529 let DecoderNamespace = "Mips64"; 530 let isCodeGenOnly = 1; 531 } 532} 533 534// 64-bit store left/right. 535multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 536 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 537 Requires<[NotN64, HasStdEnc]>; 538 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 539 Requires<[IsN64, HasStdEnc]> { 540 let DecoderNamespace = "Mips64"; 541 let isCodeGenOnly = 1; 542 } 543} 544 545// Conditional Branch 546class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>: 547 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 548 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 549 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { 550 let isBranch = 1; 551 let isTerminator = 1; 552 let hasDelaySlot = 1; 553 let Defs = [AT]; 554} 555 556class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op, 557 RegisterClass RC>: 558 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16), 559 !strconcat(instr_asm, "\t$rs, $imm16"), 560 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { 561 let rt = _rt; 562 let isBranch = 1; 563 let isTerminator = 1; 564 let hasDelaySlot = 1; 565 let Defs = [AT]; 566} 567 568// SetCC 569class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 570 RegisterClass RC>: 571 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 572 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 573 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 574 IIAlu> { 575 let shamt = 0; 576} 577 578class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 579 PatLeaf imm_type, RegisterClass RC>: 580 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 581 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 582 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 583 IIAlu>; 584 585// Jump 586class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 587 SDPatternOperator operator, SDPatternOperator targetoperator>: 588 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 589 [(operator targetoperator:$target)], IIBranch> { 590 let isTerminator=1; 591 let isBarrier=1; 592 let hasDelaySlot = 1; 593 let DecoderMethod = "DecodeJumpTarget"; 594 let Defs = [AT]; 595} 596 597// Unconditional branch 598class UncondBranch<bits<6> op, string instr_asm>: 599 BranchBase<op, (outs), (ins brtarget:$imm16), 600 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 601 let rs = 0; 602 let rt = 0; 603 let isBranch = 1; 604 let isTerminator = 1; 605 let isBarrier = 1; 606 let hasDelaySlot = 1; 607 let Predicates = [RelocPIC, HasStdEnc]; 608 let Defs = [AT]; 609} 610 611// Base class for indirect branch and return instruction classes. 612let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 613class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 614 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 615 let rt = 0; 616 let rd = 0; 617 let shamt = 0; 618} 619 620// Indirect branch 621class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 622 let isBranch = 1; 623 let isIndirectBranch = 1; 624} 625 626// Return instruction 627class RetBase<RegisterClass RC>: JumpFR<RC> { 628 let isReturn = 1; 629 let isCodeGenOnly = 1; 630 let hasCtrlDep = 1; 631 let hasExtraSrcRegAllocReq = 1; 632} 633 634// Jump and Link (Call) 635let isCall=1, hasDelaySlot=1, Defs = [RA] in { 636 class JumpLink<bits<6> op, string instr_asm>: 637 FJ<op, (outs), (ins calltarget:$target), 638 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 639 IIBranch> { 640 let DecoderMethod = "DecodeJumpTarget"; 641 } 642 643 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 644 RegisterClass RC>: 645 FR<op, func, (outs), (ins RC:$rs), 646 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 647 let rt = 0; 648 let rd = 31; 649 let shamt = 0; 650 } 651 652 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 653 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 654 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 655 let rt = _rt; 656 } 657} 658 659// Mul, Div 660class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 661 RegisterClass RC, list<Register> DefRegs>: 662 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 663 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 664 let rd = 0; 665 let shamt = 0; 666 let isCommutable = 1; 667 let Defs = DefRegs; 668 let neverHasSideEffects = 1; 669} 670 671class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 672 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 673 674class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 675 RegisterClass RC, list<Register> DefRegs>: 676 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 677 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 678 [(op RC:$rs, RC:$rt)], itin> { 679 let rd = 0; 680 let shamt = 0; 681 let Defs = DefRegs; 682} 683 684class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 685 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 686 687// Move from Hi/Lo 688class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 689 list<Register> UseRegs>: 690 FR<0x00, func, (outs RC:$rd), (ins), 691 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 692 let rs = 0; 693 let rt = 0; 694 let shamt = 0; 695 let Uses = UseRegs; 696 let neverHasSideEffects = 1; 697} 698 699class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 700 list<Register> DefRegs>: 701 FR<0x00, func, (outs), (ins RC:$rs), 702 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 703 let rt = 0; 704 let rd = 0; 705 let shamt = 0; 706 let Defs = DefRegs; 707 let neverHasSideEffects = 1; 708} 709 710class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 711 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 712 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 713 let isCodeGenOnly = 1; 714} 715 716// Count Leading Ones/Zeros in Word 717class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 718 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 719 !strconcat(instr_asm, "\t$rd, $rs"), 720 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 721 Requires<[HasBitCount, HasStdEnc]> { 722 let shamt = 0; 723 let rt = rd; 724} 725 726class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 727 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 728 !strconcat(instr_asm, "\t$rd, $rs"), 729 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 730 Requires<[HasBitCount, HasStdEnc]> { 731 let shamt = 0; 732 let rt = rd; 733} 734 735// Sign Extend in Register. 736class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 737 RegisterClass RC>: 738 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 739 !strconcat(instr_asm, "\t$rd, $rt"), 740 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 741 let rs = 0; 742 let shamt = sa; 743 let Predicates = [HasSEInReg, HasStdEnc]; 744} 745 746// Subword Swap 747class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 748 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 749 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 750 let rs = 0; 751 let shamt = sa; 752 let Predicates = [HasSwap, HasStdEnc]; 753 let neverHasSideEffects = 1; 754} 755 756// Read Hardware 757class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 758 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 759 "rdhwr\t$rt, $rd", [], IIAlu> { 760 let rs = 0; 761 let shamt = 0; 762} 763 764// Ext and Ins 765class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 766 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 767 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 768 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 769 bits<5> pos; 770 bits<5> sz; 771 let rd = sz; 772 let shamt = pos; 773 let Predicates = [HasMips32r2, HasStdEnc]; 774} 775 776class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 777 FR<0x1f, _funct, (outs RC:$rt), 778 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 779 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 780 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 781 NoItinerary> { 782 bits<5> pos; 783 bits<5> sz; 784 let rd = sz; 785 let shamt = pos; 786 let Predicates = [HasMips32r2, HasStdEnc]; 787 let Constraints = "$src = $rt"; 788} 789 790// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 791class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 792 RegisterClass PRC> : 793 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 794 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 795 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 796 797multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 798 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 799 Requires<[NotN64, HasStdEnc]>; 800 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 801 Requires<[IsN64, HasStdEnc]> { 802 let DecoderNamespace = "Mips64"; 803 } 804} 805 806// Atomic Compare & Swap. 807class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 808 RegisterClass PRC> : 809 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 810 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 811 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 812 813multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 814 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 815 Requires<[NotN64, HasStdEnc]>; 816 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 817 Requires<[IsN64, HasStdEnc]> { 818 let DecoderNamespace = "Mips64"; 819 } 820} 821 822class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 823 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 824 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 825 let mayLoad = 1; 826} 827 828class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 829 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 830 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 831 let mayStore = 1; 832 let Constraints = "$rt = $dst"; 833} 834 835//===----------------------------------------------------------------------===// 836// Pseudo instructions 837//===----------------------------------------------------------------------===// 838 839// Return RA. 840let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 841def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 842 843let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 844def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 845 "!ADJCALLSTACKDOWN $amt", 846 [(callseq_start timm:$amt)]>; 847def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 848 "!ADJCALLSTACKUP $amt1", 849 [(callseq_end timm:$amt1, timm:$amt2)]>; 850} 851 852// When handling PIC code the assembler needs .cpload and .cprestore 853// directives. If the real instructions corresponding these directives 854// are used, we have the same behavior, but get also a bunch of warnings 855// from the assembler. 856let neverHasSideEffects = 1 in 857def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 858 ".cprestore\t$loc", []>; 859 860let usesCustomInserter = 1 in { 861 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 862 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 863 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 864 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 865 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 866 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 867 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 868 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 869 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 870 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 871 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 872 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 873 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 874 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 875 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 876 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 877 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 878 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 879 880 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 881 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 882 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 883 884 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 885 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 886 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 887} 888 889//===----------------------------------------------------------------------===// 890// Instruction definition 891//===----------------------------------------------------------------------===// 892 893class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 894 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 895 !strconcat(instr_asm, "\t$rt, $imm32")> ; 896def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 897 898class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 899 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 900 !strconcat(instr_asm, "\t$rt, $addr")> ; 901def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 902 903class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 904 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 905 !strconcat(instr_asm, "\t$rt, $imm32")> ; 906def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 907 908//===----------------------------------------------------------------------===// 909// MipsI Instructions 910//===----------------------------------------------------------------------===// 911 912/// Arithmetic Instructions (ALU Immediate) 913def ADDiu : ArithLogicI<"addiu", simm16, immSExt16, CPURegs, add>, 914 ADDI_FM<0x9>, IsAsCheapAsAMove; 915def ADDi : ArithLogicI<"addi", simm16, immSExt16, CPURegs>, ADDI_FM<0x8>; 916def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 917def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 918def ANDi : ArithLogicI<"andi", uimm16, immZExt16, CPURegs, and>, ADDI_FM<0xc>; 919def ORi : ArithLogicI<"ori", uimm16, immZExt16, CPURegs, or>, ADDI_FM<0xd>; 920def XORi : ArithLogicI<"xori", uimm16, immZExt16, CPURegs, xor>, ADDI_FM<0xe>; 921def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 922 923/// Arithmetic Instructions (3-Operand, R-Type) 924def ADDu : ArithLogicR<"addu", IIAlu, CPURegs, 1, add>, ADD_FM<0, 0x21>; 925def SUBu : ArithLogicR<"subu", IIAlu, CPURegs, 0, sub>, ADD_FM<0, 0x23>; 926def ADD : ArithLogicR<"add", IIAlu, CPURegs, 1>, ADD_FM<0, 0x20>; 927def SUB : ArithLogicR<"sub", IIAlu, CPURegs, 0>, ADD_FM<0, 0x22>; 928def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 929def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 930def AND : ArithLogicR<"and", IIAlu, CPURegs, 1, and>, ADD_FM<0, 0x24>; 931def OR : ArithLogicR<"or", IIAlu, CPURegs, 1, or>, ADD_FM<0, 0x25>; 932def XOR : ArithLogicR<"xor", IIAlu, CPURegs, 1, xor>, ADD_FM<0, 0x26>; 933def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 934 935/// Shift Instructions 936def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>; 937def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>; 938def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>; 939def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>; 940def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>; 941def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>; 942 943// Rotate Instructions 944let Predicates = [HasMips32r2, HasStdEnc] in { 945 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>; 946 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>; 947} 948 949/// Load and Store Instructions 950/// aligned 951defm LB : LoadM32<0x20, "lb", sextloadi8>; 952defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 953defm LH : LoadM32<0x21, "lh", sextloadi16>; 954defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 955defm LW : LoadM32<0x23, "lw", load>; 956defm SB : StoreM32<0x28, "sb", truncstorei8>; 957defm SH : StoreM32<0x29, "sh", truncstorei16>; 958defm SW : StoreM32<0x2b, "sw", store>; 959 960/// load/store left/right 961defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 962defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 963defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 964defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 965 966let hasSideEffects = 1 in 967def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 968 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 969{ 970 bits<5> stype; 971 let Opcode = 0; 972 let Inst{25-11} = 0; 973 let Inst{10-6} = stype; 974 let Inst{5-0} = 15; 975} 976 977/// Load-linked, Store-conditional 978def LL : LLBase<0x30, "ll", CPURegs, mem>, 979 Requires<[NotN64, HasStdEnc]>; 980def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 981 Requires<[IsN64, HasStdEnc]> { 982 let DecoderNamespace = "Mips64"; 983} 984 985def SC : SCBase<0x38, "sc", CPURegs, mem>, 986 Requires<[NotN64, HasStdEnc]>; 987def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 988 Requires<[IsN64, HasStdEnc]> { 989 let DecoderNamespace = "Mips64"; 990} 991 992/// Jump and Branch Instructions 993def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 994 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 995def JR : IndirectBranch<CPURegs>; 996def B : UncondBranch<0x04, "b">; 997def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; 998def BNE : CBranch<0x05, "bne", setne, CPURegs>; 999def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; 1000def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 1001def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; 1002def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; 1003 1004let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 1005 hasDelaySlot = 1, Defs = [RA] in 1006def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 1007 1008def JAL : JumpLink<0x03, "jal">; 1009def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 1010def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 1011def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 1012def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 1013def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 1014 1015def RET : RetBase<CPURegs>; 1016 1017/// Multiply and Divide Instructions. 1018def MULT : Mult32<0x18, "mult", IIImul>; 1019def MULTu : Mult32<0x19, "multu", IIImul>; 1020def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 1021def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 1022 1023def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1024def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1025def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1026def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1027 1028/// Sign Ext In Register Instructions. 1029def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1030def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1031 1032/// Count Leading 1033def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1034def CLO : CountLeading1<0x21, "clo", CPURegs>; 1035 1036/// Word Swap Bytes Within Halfwords 1037def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1038 1039/// No operation 1040let addr=0 in 1041 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1042 1043// FrameIndexes are legalized when they are operands from load/store 1044// instructions. The same not happens for stack address copies, so an 1045// add op with mem ComplexPattern is used and the stack address copy 1046// can be matched. It's similar to Sparc LEA_ADDRi 1047def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1048 1049// MADD*/MSUB* 1050def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1051def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1052def MSUB : MArithR<4, "msub", MipsMSub>; 1053def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1054 1055// MUL is a assembly macro in the current used ISAs. In recent ISA's 1056// it is a real instruction. 1057def MUL : ArithLogicR<"mul", IIImul, CPURegs, 1, mul>, ADD_FM<0x1c, 0x02>; 1058 1059def RDHWR : ReadHardware<CPURegs, HWRegs>; 1060 1061def EXT : ExtBase<0, "ext", CPURegs>; 1062def INS : InsBase<4, "ins", CPURegs>; 1063 1064//===----------------------------------------------------------------------===// 1065// Instruction aliases 1066//===----------------------------------------------------------------------===// 1067def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1068def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1069def : InstAlias<"addu $rs,$rt,$imm", 1070 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1071def : InstAlias<"add $rs,$rt,$imm", 1072 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1073def : InstAlias<"and $rs,$rt,$imm", 1074 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1075def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1076def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1077def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1078def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1079def : InstAlias<"slt $rs,$rt,$imm", 1080 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1081def : InstAlias<"xor $rs,$rt,$imm", 1082 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1083 1084//===----------------------------------------------------------------------===// 1085// Arbitrary patterns that map to one or more instructions 1086//===----------------------------------------------------------------------===// 1087 1088// Small immediates 1089def : MipsPat<(i32 immSExt16:$in), 1090 (ADDiu ZERO, imm:$in)>; 1091def : MipsPat<(i32 immZExt16:$in), 1092 (ORi ZERO, imm:$in)>; 1093def : MipsPat<(i32 immLow16Zero:$in), 1094 (LUi (HI16 imm:$in))>; 1095 1096// Arbitrary immediates 1097def : MipsPat<(i32 imm:$imm), 1098 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1099 1100// Carry MipsPatterns 1101def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1102 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1103def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1104 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1105def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1106 (ADDiu CPURegs:$src, imm:$imm)>; 1107 1108// Call 1109def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1110 (JAL tglobaladdr:$dst)>; 1111def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1112 (JAL texternalsym:$dst)>; 1113//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1114// (JALR CPURegs:$dst)>; 1115 1116// Tail call 1117def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1118 (TAILCALL tglobaladdr:$dst)>; 1119def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1120 (TAILCALL texternalsym:$dst)>; 1121// hi/lo relocs 1122def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1123def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1124def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1125def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1126def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1127def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1128 1129def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1130def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1131def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1132def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1133def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1134def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1135 1136def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1137 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1138def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1139 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1140def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1141 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1142def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1143 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1144def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1145 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1146 1147// gp_rel relocs 1148def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1149 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1150def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1151 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1152 1153// wrapper_pic 1154class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1155 MipsPat<(MipsWrapper RC:$gp, node:$in), 1156 (ADDiuOp RC:$gp, node:$in)>; 1157 1158def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1159def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1160def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1161def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1162def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1163def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1164 1165// Mips does not have "not", so we expand our way 1166def : MipsPat<(not CPURegs:$in), 1167 (NOR CPURegs:$in, ZERO)>; 1168 1169// extended loads 1170let Predicates = [NotN64, HasStdEnc] in { 1171 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1172 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1173 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1174} 1175let Predicates = [IsN64, HasStdEnc] in { 1176 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1177 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1178 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1179} 1180 1181// peepholes 1182let Predicates = [NotN64, HasStdEnc] in { 1183 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1184} 1185let Predicates = [IsN64, HasStdEnc] in { 1186 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1187} 1188 1189// brcond patterns 1190multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1191 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1192 Instruction SLTiuOp, Register ZEROReg> { 1193def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1194 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1195def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1196 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1197 1198def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1199 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1200def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1201 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1202def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1203 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1204def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1205 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1206 1207def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1208 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1209def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1210 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1211 1212def : MipsPat<(brcond RC:$cond, bb:$dst), 1213 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1214} 1215 1216defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1217 1218// setcc patterns 1219multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1220 Instruction SLTuOp, Register ZEROReg> { 1221 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1222 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1223 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1224 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1225} 1226 1227multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1228 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1229 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1230 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1231 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1232} 1233 1234multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1235 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1236 (SLTOp RC:$rhs, RC:$lhs)>; 1237 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1238 (SLTuOp RC:$rhs, RC:$lhs)>; 1239} 1240 1241multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1242 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1243 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1244 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1245 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1246} 1247 1248multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1249 Instruction SLTiuOp> { 1250 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1251 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1252 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1253 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1254} 1255 1256defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1257defm : SetlePats<CPURegs, SLT, SLTu>; 1258defm : SetgtPats<CPURegs, SLT, SLTu>; 1259defm : SetgePats<CPURegs, SLT, SLTu>; 1260defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1261 1262// bswap pattern 1263def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1264 1265//===----------------------------------------------------------------------===// 1266// Floating Point Support 1267//===----------------------------------------------------------------------===// 1268 1269include "MipsInstrFPU.td" 1270include "Mips64InstrInfo.td" 1271include "MipsCondMov.td" 1272 1273// 1274// Mips16 1275 1276include "Mips16InstrFormats.td" 1277include "Mips16InstrInfo.td" 1278 1279// DSP 1280include "MipsDSPInstrFormats.td" 1281include "MipsDSPInstrInfo.td" 1282 1283