MipsInstrInfo.td revision d761004bfd61c96ad650b82ab262e220530ea6d9
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 36def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 37 38def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 39 40def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 41 42def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 44def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 46 SDTCisSameAs<0, 4>]>; 47 48def SDTMipsLoadLR : SDTypeProfile<1, 2, 49 [SDTCisInt<0>, SDTCisPtrTy<1>, 50 SDTCisSameAs<0, 2>]>; 51 52// Call 53def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 55 SDNPVariadic]>; 56 57// Tail call 58def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 60 61// Hi and Lo nodes are used to handle global addresses. Used on 62// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 63// static model. (nothing to do with Mips Registers Hi and Lo) 64def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 65def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 66def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 67 68// TlsGd node is used to handle General Dynamic TLS 69def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 70 71// TprelHi and TprelLo nodes are used to handle Local Exec TLS 72def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 73def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 74 75// Thread pointer 76def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 77 78// Return 79def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 81 82// These are target-independent nodes, but have target-specific formats. 83def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 85def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 86 [SDNPHasChain, SDNPSideEffect, 87 SDNPOptInGlue, SDNPOutGlue]>; 88 89// Node used to extract integer from LO/HI register. 90def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185 186class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 187 let Predicates = [HasStdEnc]; 188} 189 190class IsCommutable { 191 bit isCommutable = 1; 192} 193 194class IsBranch { 195 bit isBranch = 1; 196} 197 198class IsReturn { 199 bit isReturn = 1; 200} 201 202class IsCall { 203 bit isCall = 1; 204} 205 206class IsTailCall { 207 bit isCall = 1; 208 bit isTerminator = 1; 209 bit isReturn = 1; 210 bit isBarrier = 1; 211 bit hasExtraSrcRegAllocReq = 1; 212 bit isCodeGenOnly = 1; 213} 214 215class IsAsCheapAsAMove { 216 bit isAsCheapAsAMove = 1; 217} 218 219class NeverHasSideEffects { 220 bit neverHasSideEffects = 1; 221} 222 223//===----------------------------------------------------------------------===// 224// Instruction format superclass 225//===----------------------------------------------------------------------===// 226 227include "MipsInstrFormats.td" 228 229//===----------------------------------------------------------------------===// 230// Mips Operand, Complex Patterns and Transformations Definitions. 231//===----------------------------------------------------------------------===// 232 233// Instruction operand types 234def jmptarget : Operand<OtherVT> { 235 let EncoderMethod = "getJumpTargetOpValue"; 236} 237def brtarget : Operand<OtherVT> { 238 let EncoderMethod = "getBranchTargetOpValue"; 239 let OperandType = "OPERAND_PCREL"; 240 let DecoderMethod = "DecodeBranchTarget"; 241} 242def calltarget : Operand<iPTR> { 243 let EncoderMethod = "getJumpTargetOpValue"; 244} 245def calltarget64: Operand<i64>; 246def simm16 : Operand<i32> { 247 let DecoderMethod= "DecodeSimm16"; 248} 249 250def simm20 : Operand<i32> { 251} 252 253def simm16_64 : Operand<i64>; 254def shamt : Operand<i32>; 255 256// Unsigned Operand 257def uimm16 : Operand<i32> { 258 let PrintMethod = "printUnsignedImm"; 259} 260 261def MipsMemAsmOperand : AsmOperandClass { 262 let Name = "Mem"; 263 let ParserMethod = "parseMemOperand"; 264} 265 266// Address operand 267def mem : Operand<i32> { 268 let PrintMethod = "printMemOperand"; 269 let MIOperandInfo = (ops CPURegs, simm16); 270 let EncoderMethod = "getMemEncoding"; 271 let ParserMatchClass = MipsMemAsmOperand; 272 let OperandType = "OPERAND_MEMORY"; 273} 274 275def mem64 : Operand<i64> { 276 let PrintMethod = "printMemOperand"; 277 let MIOperandInfo = (ops CPU64Regs, simm16_64); 278 let EncoderMethod = "getMemEncoding"; 279 let ParserMatchClass = MipsMemAsmOperand; 280 let OperandType = "OPERAND_MEMORY"; 281} 282 283def mem_ea : Operand<i32> { 284 let PrintMethod = "printMemOperandEA"; 285 let MIOperandInfo = (ops CPURegs, simm16); 286 let EncoderMethod = "getMemEncoding"; 287 let OperandType = "OPERAND_MEMORY"; 288} 289 290def mem_ea_64 : Operand<i64> { 291 let PrintMethod = "printMemOperandEA"; 292 let MIOperandInfo = (ops CPU64Regs, simm16_64); 293 let EncoderMethod = "getMemEncoding"; 294 let OperandType = "OPERAND_MEMORY"; 295} 296 297// size operand of ext instruction 298def size_ext : Operand<i32> { 299 let EncoderMethod = "getSizeExtEncoding"; 300 let DecoderMethod = "DecodeExtSize"; 301} 302 303// size operand of ins instruction 304def size_ins : Operand<i32> { 305 let EncoderMethod = "getSizeInsEncoding"; 306 let DecoderMethod = "DecodeInsSize"; 307} 308 309// Transformation Function - get the lower 16 bits. 310def LO16 : SDNodeXForm<imm, [{ 311 return getImm(N, N->getZExtValue() & 0xFFFF); 312}]>; 313 314// Transformation Function - get the higher 16 bits. 315def HI16 : SDNodeXForm<imm, [{ 316 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 317}]>; 318 319// Plus 1. 320def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 321 322// Node immediate fits as 16-bit sign extended on target immediate. 323// e.g. addi, andi 324def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 325 326// Node immediate fits as 16-bit sign extended on target immediate. 327// e.g. addi, andi 328def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 329 330// Node immediate fits as 15-bit sign extended on target immediate. 331// e.g. addi, andi 332def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 333 334// Node immediate fits as 16-bit zero extended on target immediate. 335// The LO16 param means that only the lower 16 bits of the node 336// immediate are caught. 337// e.g. addiu, sltiu 338def immZExt16 : PatLeaf<(imm), [{ 339 if (N->getValueType(0) == MVT::i32) 340 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 341 else 342 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 343}], LO16>; 344 345// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 346def immLow16Zero : PatLeaf<(imm), [{ 347 int64_t Val = N->getSExtValue(); 348 return isInt<32>(Val) && !(Val & 0xffff); 349}]>; 350 351// shamt field must fit in 5 bits. 352def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 353 354// True if (N + 1) fits in 16-bit field. 355def immSExt16Plus1 : PatLeaf<(imm), [{ 356 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 357}]>; 358 359// Mips Address Mode! SDNode frameindex could possibily be a match 360// since load and store instructions from stack used it. 361def addr : 362 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 363 364def addrRegImm : 365 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 366 367def addrDefault : 368 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 369 370//===----------------------------------------------------------------------===// 371// Instructions specific format 372//===----------------------------------------------------------------------===// 373 374// Arithmetic and logical instructions with 3 register operands. 375class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 376 InstrItinClass Itin = NoItinerary, 377 SDPatternOperator OpNode = null_frag>: 378 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 379 !strconcat(opstr, "\t$rd, $rs, $rt"), 380 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 381 let isCommutable = isComm; 382 let isReMaterializable = 1; 383} 384 385// Arithmetic and logical instructions with 2 register operands. 386class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 387 SDPatternOperator imm_type = null_frag, 388 SDPatternOperator OpNode = null_frag> : 389 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 390 !strconcat(opstr, "\t$rt, $rs, $imm16"), 391 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 392 IIAlu, FrmI, opstr> { 393 let isReMaterializable = 1; 394} 395 396// Arithmetic Multiply ADD/SUB 397class MArithR<string opstr, bit isComm = 0> : 398 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 399 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> { 400 let Defs = [HI, LO]; 401 let Uses = [HI, LO]; 402 let isCommutable = isComm; 403} 404 405// Logical 406class LogicNOR<string opstr, RegisterOperand RC>: 407 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 408 !strconcat(opstr, "\t$rd, $rs, $rt"), 409 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> { 410 let isCommutable = 1; 411} 412 413// Shifts 414class shift_rotate_imm<string opstr, Operand ImmOpnd, 415 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 416 SDPatternOperator PF = null_frag> : 417 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 418 !strconcat(opstr, "\t$rd, $rt, $shamt"), 419 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>; 420 421class shift_rotate_reg<string opstr, RegisterOperand RC, 422 SDPatternOperator OpNode = null_frag>: 423 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 424 !strconcat(opstr, "\t$rd, $rt, $rs"), 425 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>; 426 427// Load Upper Imediate 428class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 429 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 430 [], IIAlu, FrmI>, IsAsCheapAsAMove { 431 let neverHasSideEffects = 1; 432 let isReMaterializable = 1; 433} 434 435class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 436 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 437 bits<21> addr; 438 let Inst{25-21} = addr{20-16}; 439 let Inst{15-0} = addr{15-0}; 440 let DecoderMethod = "DecodeMem"; 441} 442 443// Memory Load/Store 444class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 445 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> : 446 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 447 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, 448 !strconcat(opstr, ofsuffix)> { 449 let DecoderMethod = "DecodeMem"; 450 let canFoldAsLoad = 1; 451 let mayLoad = 1; 452} 453 454class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 455 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> : 456 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 457 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI, 458 !strconcat(opstr, ofsuffix)> { 459 let DecoderMethod = "DecodeMem"; 460 let mayStore = 1; 461} 462 463multiclass LoadM<string opstr, RegisterClass RC, 464 SDPatternOperator OpNode = null_frag, 465 ComplexPattern Addr = addr> { 466 def NAME : Load<opstr, OpNode, RC, mem, Addr, "">, 467 Requires<[NotN64, HasStdEnc]>; 468 def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">, 469 Requires<[IsN64, HasStdEnc]> { 470 let DecoderNamespace = "Mips64"; 471 let isCodeGenOnly = 1; 472 } 473} 474 475multiclass StoreM<string opstr, RegisterClass RC, 476 SDPatternOperator OpNode = null_frag, 477 ComplexPattern Addr = addr> { 478 def NAME : Store<opstr, OpNode, RC, mem, Addr, "">, 479 Requires<[NotN64, HasStdEnc]>; 480 def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">, 481 Requires<[IsN64, HasStdEnc]> { 482 let DecoderNamespace = "Mips64"; 483 let isCodeGenOnly = 1; 484 } 485} 486 487// Load/Store Left/Right 488let canFoldAsLoad = 1 in 489class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 490 Operand MemOpnd> : 491 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 492 !strconcat(opstr, "\t$rt, $addr"), 493 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 494 let DecoderMethod = "DecodeMem"; 495 string Constraints = "$src = $rt"; 496} 497 498class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 499 Operand MemOpnd>: 500 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 501 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 502 let DecoderMethod = "DecodeMem"; 503} 504 505multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 506 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 507 Requires<[NotN64, HasStdEnc]>; 508 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 509 Requires<[IsN64, HasStdEnc]> { 510 let DecoderNamespace = "Mips64"; 511 let isCodeGenOnly = 1; 512 } 513} 514 515multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 516 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 517 Requires<[NotN64, HasStdEnc]>; 518 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 519 Requires<[IsN64, HasStdEnc]> { 520 let DecoderNamespace = "Mips64"; 521 let isCodeGenOnly = 1; 522 } 523} 524 525// Conditional Branch 526class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> : 527 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 528 !strconcat(opstr, "\t$rs, $rt, $offset"), 529 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 530 FrmI> { 531 let isBranch = 1; 532 let isTerminator = 1; 533 let hasDelaySlot = 1; 534 let Defs = [AT]; 535} 536 537class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> : 538 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 539 !strconcat(opstr, "\t$rs, $offset"), 540 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 541 let isBranch = 1; 542 let isTerminator = 1; 543 let hasDelaySlot = 1; 544 let Defs = [AT]; 545} 546 547// SetCC 548class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 549 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 550 !strconcat(opstr, "\t$rd, $rs, $rt"), 551 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], 552 IIAlu, FrmR, opstr>; 553 554class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 555 RegisterClass RC>: 556 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 557 !strconcat(opstr, "\t$rt, $rs, $imm16"), 558 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 559 IIAlu, FrmI, opstr>; 560 561// Jump 562class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 563 SDPatternOperator targetoperator> : 564 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 565 [(operator targetoperator:$target)], IIBranch, FrmJ> { 566 let isTerminator=1; 567 let isBarrier=1; 568 let hasDelaySlot = 1; 569 let DecoderMethod = "DecodeJumpTarget"; 570 let Defs = [AT]; 571} 572 573// Unconditional branch 574class UncondBranch<string opstr> : 575 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 576 [(br bb:$offset)], IIBranch, FrmI> { 577 let isBranch = 1; 578 let isTerminator = 1; 579 let isBarrier = 1; 580 let hasDelaySlot = 1; 581 let Predicates = [RelocPIC, HasStdEnc]; 582 let Defs = [AT]; 583} 584 585// Base class for indirect branch and return instruction classes. 586let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 587class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 588 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 589 590// Indirect branch 591class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 592 let isBranch = 1; 593 let isIndirectBranch = 1; 594} 595 596// Return instruction 597class RetBase<RegisterClass RC>: JumpFR<RC> { 598 let isReturn = 1; 599 let isCodeGenOnly = 1; 600 let hasCtrlDep = 1; 601 let hasExtraSrcRegAllocReq = 1; 602} 603 604// Jump and Link (Call) 605let isCall=1, hasDelaySlot=1, Defs = [RA] in { 606 class JumpLink<string opstr> : 607 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 608 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 609 let DecoderMethod = "DecodeJumpTarget"; 610 } 611 612 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 613 Register RetReg>: 614 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 615 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 616 617 class JumpLinkReg<string opstr, RegisterClass RC>: 618 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 619 [], IIBranch, FrmR>; 620 621 class BGEZAL_FT<string opstr, RegisterOperand RO> : 622 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 623 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 624 625} 626 627class BAL_FT : 628 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 629 let isBranch = 1; 630 let isTerminator = 1; 631 let isBarrier = 1; 632 let hasDelaySlot = 1; 633 let Defs = [RA]; 634} 635 636// Sync 637let hasSideEffects = 1 in 638class SYNC_FT : 639 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 640 NoItinerary, FrmOther>; 641 642// Mul, Div 643class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 644 list<Register> DefRegs> : 645 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 646 itin, FrmR, opstr> { 647 let isCommutable = 1; 648 let Defs = DefRegs; 649 let neverHasSideEffects = 1; 650} 651 652// Pseudo multiply/divide instruction with explicit accumulator register 653// operands. 654class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 655 SDPatternOperator OpNode, InstrItinClass Itin, 656 bit IsComm = 1, bit HasSideEffects = 0> : 657 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 658 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 659 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 660 let isCommutable = IsComm; 661 let hasSideEffects = HasSideEffects; 662} 663 664// Pseudo multiply add/sub instruction with explicit accumulator register 665// operands. 666class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 667 : PseudoSE<(outs ACRegs:$ac), 668 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin), 669 [(set ACRegs:$ac, 670 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))], 671 IIImul>, 672 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> { 673 string Constraints = "$acin = $ac"; 674} 675 676class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 677 list<Register> DefRegs> : 678 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 679 [], itin, FrmR> { 680 let Defs = DefRegs; 681} 682 683// Move from Hi/Lo 684class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 685 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 686 let Uses = UseRegs; 687 let neverHasSideEffects = 1; 688} 689 690class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 691 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 692 let Defs = DefRegs; 693 let neverHasSideEffects = 1; 694} 695 696class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 697 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 698 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 699 let isCodeGenOnly = 1; 700 let DecoderMethod = "DecodeMem"; 701} 702 703// Count Leading Ones/Zeros in Word 704class CountLeading0<string opstr, RegisterOperand RO>: 705 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 706 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 707 Requires<[HasBitCount, HasStdEnc]>; 708 709class CountLeading1<string opstr, RegisterOperand RO>: 710 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 711 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 712 Requires<[HasBitCount, HasStdEnc]>; 713 714 715// Sign Extend in Register. 716class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 717 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 718 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 719 let Predicates = [HasSEInReg, HasStdEnc]; 720} 721 722// Subword Swap 723class SubwordSwap<string opstr, RegisterOperand RO>: 724 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 725 NoItinerary, FrmR> { 726 let Predicates = [HasSwap, HasStdEnc]; 727 let neverHasSideEffects = 1; 728} 729 730// Read Hardware 731class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 732 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 733 IIAlu, FrmR>; 734 735// Ext and Ins 736class ExtBase<string opstr, RegisterOperand RO>: 737 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 738 !strconcat(opstr, " $rt, $rs, $pos, $size"), 739 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 740 FrmR> { 741 let Predicates = [HasMips32r2, HasStdEnc]; 742} 743 744class InsBase<string opstr, RegisterOperand RO>: 745 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 746 !strconcat(opstr, " $rt, $rs, $pos, $size"), 747 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 748 NoItinerary, FrmR> { 749 let Predicates = [HasMips32r2, HasStdEnc]; 750 let Constraints = "$src = $rt"; 751} 752 753// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 754class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 755 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 756 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 757 758multiclass Atomic2Ops32<PatFrag Op> { 759 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 760 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 761 Requires<[IsN64, HasStdEnc]> { 762 let DecoderNamespace = "Mips64"; 763 } 764} 765 766// Atomic Compare & Swap. 767class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 768 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 769 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 770 771multiclass AtomicCmpSwap32<PatFrag Op> { 772 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 773 Requires<[NotN64, HasStdEnc]>; 774 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 775 Requires<[IsN64, HasStdEnc]> { 776 let DecoderNamespace = "Mips64"; 777 } 778} 779 780class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 781 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 782 [], NoItinerary, FrmI> { 783 let DecoderMethod = "DecodeMem"; 784 let mayLoad = 1; 785} 786 787class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 788 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 789 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 790 let DecoderMethod = "DecodeMem"; 791 let mayStore = 1; 792 let Constraints = "$rt = $dst"; 793} 794 795class MFC3OP<dag outs, dag ins, string asmstr> : 796 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 797 798//===----------------------------------------------------------------------===// 799// Pseudo instructions 800//===----------------------------------------------------------------------===// 801 802// Return RA. 803let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 804def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 805 806let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 807def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 808 [(callseq_start timm:$amt)]>; 809def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 810 [(callseq_end timm:$amt1, timm:$amt2)]>; 811} 812 813let usesCustomInserter = 1 in { 814 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 815 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 816 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 817 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 818 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 819 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 820 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 821 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 822 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 823 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 824 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 825 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 826 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 827 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 828 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 829 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 830 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 831 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 832 833 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 834 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 835 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 836 837 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 838 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 839 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 840} 841 842/// Pseudo instructions for loading and storing accumulator registers. 843let isPseudo = 1 in { 844 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>; 845 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>; 846} 847 848//===----------------------------------------------------------------------===// 849// Instruction definition 850//===----------------------------------------------------------------------===// 851//===----------------------------------------------------------------------===// 852// MipsI Instructions 853//===----------------------------------------------------------------------===// 854 855/// Arithmetic Instructions (ALU Immediate) 856def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 857 ADDI_FM<0x9>, IsAsCheapAsAMove; 858def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 859def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, 860 SLTI_FM<0xa>; 861def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, 862 SLTI_FM<0xb>; 863def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 864 ADDI_FM<0xc>; 865def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 866 ADDI_FM<0xd>; 867def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 868 ADDI_FM<0xe>; 869def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 870 871/// Arithmetic Instructions (3-Operand, R-Type) 872def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, 873 ADD_FM<0, 0x21>; 874def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, 875 ADD_FM<0, 0x23>; 876def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, 877 ADD_FM<0x1c, 2>; 878def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 879def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 880def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 881def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 882def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, 883 ADD_FM<0, 0x24>; 884def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, 885 ADD_FM<0, 0x25>; 886def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, 887 ADD_FM<0, 0x26>; 888def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 889 890/// Shift Instructions 891def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 892 SRA_FM<0, 0>; 893def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 894 SRA_FM<2, 0>; 895def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 896 SRA_FM<3, 0>; 897def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 898def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 899def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 900 901// Rotate Instructions 902let Predicates = [HasMips32r2, HasStdEnc] in { 903 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, 904 immZExt5>, 905 SRA_FM<2, 1>; 906 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, 907 SRLV_FM<6, 1>; 908} 909 910/// Load and Store Instructions 911/// aligned 912defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>; 913defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>; 914defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>; 915defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>; 916defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>; 917defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>; 918defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>; 919defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>; 920 921/// load/store left/right 922defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 923defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 924defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 925defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 926 927def SYNC : SYNC_FT, SYNC_FM; 928 929/// Load-linked, Store-conditional 930let Predicates = [NotN64, HasStdEnc] in { 931 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 932 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 933} 934 935let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 936 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 937 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 938} 939 940/// Jump and Branch Instructions 941def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 942 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 943def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 944def B : UncondBranch<"b">, B_FM; 945def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>; 946def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>; 947def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>; 948def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>; 949def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>; 950def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>; 951 952def BAL_BR: BAL_FT, BAL_FM; 953 954def JAL : JumpLink<"jal">, FJ<3>; 955def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 956def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 957def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 958def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 959def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 960def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 961 962def RET : RetBase<CPURegs>, MTLO_FM<8>; 963 964// Exception handling related node and instructions. 965// The conversion sequence is: 966// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 967// MIPSeh_return -> (stack change + indirect branch) 968// 969// MIPSeh_return takes the place of regular return instruction 970// but takes two arguments (V1, V0) which are used for storing 971// the offset and return address respectively. 972def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 973 974def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 975 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 976 977let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 978 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 979 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 980 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 981 CPU64Regs:$dst), 982 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 983} 984 985/// Multiply and Divide Instructions. 986def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, 987 MULT_FM<0, 0x18>; 988def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, 989 MULT_FM<0, 0x19>; 990def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>; 991def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>; 992def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>; 993def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>; 994def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 995 0>; 996def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv, 997 0>; 998 999def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 1000def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 1001def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 1002def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 1003 1004/// Sign Ext In Register Instructions. 1005def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 1006def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 1007 1008/// Count Leading 1009def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 1010def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 1011 1012/// Word Swap Bytes Within Halfwords 1013def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 1014 1015/// No operation. 1016def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1017 1018// FrameIndexes are legalized when they are operands from load/store 1019// instructions. The same not happens for stack address copies, so an 1020// add op with mem ComplexPattern is used and the stack address copy 1021// can be matched. It's similar to Sparc LEA_ADDRi 1022def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 1023 1024// MADD*/MSUB* 1025def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1026def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1027def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1028def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1029def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1030def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1031def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1032def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1033 1034def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 1035 1036def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 1037def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 1038 1039/// Move Control Registers From/To CPU Registers 1040def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1041 (ins CPURegsOpnd:$rd, uimm16:$sel), 1042 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 1043 1044def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1045 (ins CPURegsOpnd:$rt), 1046 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 1047 1048def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1049 (ins CPURegsOpnd:$rd, uimm16:$sel), 1050 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 1051 1052def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1053 (ins CPURegsOpnd:$rt), 1054 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 1055 1056//===----------------------------------------------------------------------===// 1057// Instruction aliases 1058//===----------------------------------------------------------------------===// 1059def : InstAlias<"move $dst, $src", 1060 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1061 Requires<[NotMips64]>; 1062def : InstAlias<"move $dst, $src", 1063 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1064 Requires<[NotMips64]>; 1065def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 1066def : InstAlias<"addu $rs, $rt, $imm", 1067 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1068def : InstAlias<"add $rs, $rt, $imm", 1069 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1070def : InstAlias<"and $rs, $rt, $imm", 1071 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1072def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1073 Requires<[NotMips64]>; 1074def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1075def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1076def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1077 Requires<[NotMips64]>; 1078def : InstAlias<"not $rt, $rs", 1079 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1080def : InstAlias<"neg $rt, $rs", 1081 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1082def : InstAlias<"negu $rt, $rs", 1083 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1084def : InstAlias<"slt $rs, $rt, $imm", 1085 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1086def : InstAlias<"xor $rs, $rt, $imm", 1087 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1088 Requires<[NotMips64]>; 1089def : InstAlias<"or $rs, $rt, $imm", 1090 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1091 Requires<[NotMips64]>; 1092def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1093def : InstAlias<"mfc0 $rt, $rd", 1094 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1095def : InstAlias<"mtc0 $rt, $rd", 1096 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1097def : InstAlias<"mfc2 $rt, $rd", 1098 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1099def : InstAlias<"mtc2 $rt, $rd", 1100 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1101def : InstAlias<"addiu $rs, $imm", 1102 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rs, simm16:$imm), 0>; 1103def : InstAlias<"bnez $rs,$offset", 1104 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, 1105 Requires<[NotMips64]>; 1106def : InstAlias<"beqz $rs,$offset", 1107 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, 1108 Requires<[NotMips64]>; 1109//===----------------------------------------------------------------------===// 1110// Assembler Pseudo Instructions 1111//===----------------------------------------------------------------------===// 1112 1113class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1114 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1115 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1116def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1117 1118class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1119 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1120 !strconcat(instr_asm, "\t$rt, $addr")> ; 1121def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1122 1123class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1124 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1125 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1126def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1127 1128 1129 1130//===----------------------------------------------------------------------===// 1131// Arbitrary patterns that map to one or more instructions 1132//===----------------------------------------------------------------------===// 1133 1134// Load/store pattern templates. 1135class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1136 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1137 1138class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1139 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1140 1141// Small immediates 1142def : MipsPat<(i32 immSExt16:$in), 1143 (ADDiu ZERO, imm:$in)>; 1144def : MipsPat<(i32 immZExt16:$in), 1145 (ORi ZERO, imm:$in)>; 1146def : MipsPat<(i32 immLow16Zero:$in), 1147 (LUi (HI16 imm:$in))>; 1148 1149// Arbitrary immediates 1150def : MipsPat<(i32 imm:$imm), 1151 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1152 1153// Carry MipsPatterns 1154def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1155 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1156let Predicates = [HasStdEnc, NotDSP] in { 1157 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1158 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1159 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1160 (ADDiu CPURegs:$src, imm:$imm)>; 1161} 1162 1163// Call 1164def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1165 (JAL tglobaladdr:$dst)>; 1166def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1167 (JAL texternalsym:$dst)>; 1168//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1169// (JALR CPURegs:$dst)>; 1170 1171// Tail call 1172def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1173 (TAILCALL tglobaladdr:$dst)>; 1174def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1175 (TAILCALL texternalsym:$dst)>; 1176// hi/lo relocs 1177def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1178def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1179def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1180def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1181def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1182def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1183 1184def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1185def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1186def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1187def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1188def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1189def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1190 1191def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1192 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1193def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1194 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1195def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1196 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1197def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1198 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1199def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1200 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1201 1202// gp_rel relocs 1203def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1204 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1205def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1206 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1207 1208// wrapper_pic 1209class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1210 MipsPat<(MipsWrapper RC:$gp, node:$in), 1211 (ADDiuOp RC:$gp, node:$in)>; 1212 1213def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1214def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1215def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1216def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1217def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1218def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1219 1220// Mips does not have "not", so we expand our way 1221def : MipsPat<(not CPURegs:$in), 1222 (NOR CPURegsOpnd:$in, ZERO)>; 1223 1224// extended loads 1225let Predicates = [NotN64, HasStdEnc] in { 1226 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1227 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1228 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1229} 1230let Predicates = [IsN64, HasStdEnc] in { 1231 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1232 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1233 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1234} 1235 1236// peepholes 1237let Predicates = [NotN64, HasStdEnc] in { 1238 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1239} 1240let Predicates = [IsN64, HasStdEnc] in { 1241 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1242} 1243 1244// brcond patterns 1245multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1246 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1247 Instruction SLTiuOp, Register ZEROReg> { 1248def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1249 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1250def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1251 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1252 1253def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1254 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1255def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1256 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1257def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1258 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1259def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1260 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1261 1262def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1263 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1264def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1265 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1266 1267def : MipsPat<(brcond RC:$cond, bb:$dst), 1268 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1269} 1270 1271defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1272 1273// setcc patterns 1274multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1275 Instruction SLTuOp, Register ZEROReg> { 1276 def : MipsPat<(seteq RC:$lhs, 0), 1277 (SLTiuOp RC:$lhs, 1)>; 1278 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1279 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1280 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1281 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1282} 1283 1284multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1285 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1286 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1287 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1288 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1289} 1290 1291multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1292 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1293 (SLTOp RC:$rhs, RC:$lhs)>; 1294 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1295 (SLTuOp RC:$rhs, RC:$lhs)>; 1296} 1297 1298multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1299 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1300 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1301 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1302 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1303} 1304 1305multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1306 Instruction SLTiuOp> { 1307 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1308 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1309 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1310 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1311} 1312 1313defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1314defm : SetlePats<CPURegs, SLT, SLTu>; 1315defm : SetgtPats<CPURegs, SLT, SLTu>; 1316defm : SetgePats<CPURegs, SLT, SLTu>; 1317defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1318 1319// bswap pattern 1320def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1321 1322// mflo/hi patterns. 1323def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)), 1324 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>; 1325 1326// Load halfword/word patterns. 1327let AddedComplexity = 40 in { 1328 let Predicates = [NotN64, HasStdEnc] in { 1329 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1330 def : LoadRegImmPat<LH, i32, sextloadi16>; 1331 def : LoadRegImmPat<LW, i32, load>; 1332 } 1333 let Predicates = [IsN64, HasStdEnc] in { 1334 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>; 1335 def : LoadRegImmPat<LH_P8, i32, sextloadi16>; 1336 def : LoadRegImmPat<LW_P8, i32, load>; 1337 } 1338} 1339 1340//===----------------------------------------------------------------------===// 1341// Floating Point Support 1342//===----------------------------------------------------------------------===// 1343 1344include "MipsInstrFPU.td" 1345include "Mips64InstrInfo.td" 1346include "MipsCondMov.td" 1347 1348// 1349// Mips16 1350 1351include "Mips16InstrFormats.td" 1352include "Mips16InstrInfo.td" 1353 1354// DSP 1355include "MipsDSPInstrFormats.td" 1356include "MipsDSPInstrInfo.td" 1357 1358// Micromips 1359include "MicroMipsInstrFormats.td" 1360include "MicroMipsInstrInfo.td" 1361