MipsInstrInfo.td revision dbf51ee4596791d8cf38538b80805b2c3a577836
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 15-bit sign extended on target immediate. 302// e.g. addi, andi 303def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 304 305// Node immediate fits as 16-bit zero extended on target immediate. 306// The LO16 param means that only the lower 16 bits of the node 307// immediate are caught. 308// e.g. addiu, sltiu 309def immZExt16 : PatLeaf<(imm), [{ 310 if (N->getValueType(0) == MVT::i32) 311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 312 else 313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 314}], LO16>; 315 316// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 317def immLow16Zero : PatLeaf<(imm), [{ 318 int64_t Val = N->getSExtValue(); 319 return isInt<32>(Val) && !(Val & 0xffff); 320}]>; 321 322// shamt field must fit in 5 bits. 323def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 324 325// Mips Address Mode! SDNode frameindex could possibily be a match 326// since load and store instructions from stack used it. 327def addr : 328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 329 330//===----------------------------------------------------------------------===// 331// Instructions specific format 332//===----------------------------------------------------------------------===// 333 334// Arithmetic and logical instructions with 3 register operands. 335class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0, 336 InstrItinClass Itin = NoItinerary, 337 SDPatternOperator OpNode = null_frag>: 338 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 339 !strconcat(opstr, "\t$rd, $rs, $rt"), 340 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 341 let isCommutable = isComm; 342 let isReMaterializable = 1; 343} 344 345// Arithmetic and logical instructions with 2 register operands. 346class ArithLogicI<string opstr, Operand Od, RegisterClass RC, 347 SDPatternOperator imm_type = null_frag, 348 SDPatternOperator OpNode = null_frag> : 349 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 350 !strconcat(opstr, "\t$rt, $rs, $imm16"), 351 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 352 let isReMaterializable = 1; 353} 354 355// Arithmetic Multiply ADD/SUB 356class MArithR<string opstr, SDNode op, bit isComm = 0> : 357 InstSE<(outs), (ins CPURegs:$rs, CPURegs:$rt), 358 !strconcat(opstr, "\t$rs, $rt"), 359 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul, FrmR> { 360 let Defs = [HI, LO]; 361 let Uses = [HI, LO]; 362 let isCommutable = isComm; 363} 364 365// Logical 366class LogicNOR<string opstr, RegisterClass RC>: 367 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 368 !strconcat(opstr, "\t$rd, $rs, $rt"), 369 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 370 let isCommutable = 1; 371} 372 373// Shifts 374class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd, 375 RegisterClass RC, SDPatternOperator OpNode> : 376 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 377 !strconcat(opstr, "\t$rd, $rt, $shamt"), 378 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 379 380// 32-bit shift instructions. 381class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> : 382 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>; 383 384class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>: 385 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 386 !strconcat(opstr, "\t$rd, $rt, $rs"), 387 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; 388 389// Load Upper Imediate 390class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 391 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 392 [], IIAlu, FrmI>, IsAsCheapAsAMove { 393 let neverHasSideEffects = 1; 394 let isReMaterializable = 1; 395} 396 397class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 398 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 399 bits<21> addr; 400 let Inst{25-21} = addr{20-16}; 401 let Inst{15-0} = addr{15-0}; 402 let DecoderMethod = "DecodeMem"; 403} 404 405// Memory Load/Store 406class Load<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> : 407 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 408 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 409 let DecoderMethod = "DecodeMem"; 410 let canFoldAsLoad = 1; 411} 412 413class Store<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> : 414 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 415 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 416 let DecoderMethod = "DecodeMem"; 417} 418 419multiclass LoadM<string opstr, PatFrag OpNode, RegisterClass RC> { 420 def #NAME# : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 421 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 422 let DecoderNamespace = "Mips64"; 423 let isCodeGenOnly = 1; 424 } 425} 426 427multiclass StoreM<string opstr, PatFrag OpNode, RegisterClass RC> { 428 def #NAME# : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 429 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 430 let DecoderNamespace = "Mips64"; 431 let isCodeGenOnly = 1; 432 } 433} 434 435// Load/Store Left/Right 436let canFoldAsLoad = 1 in 437class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 438 Operand MemOpnd> : 439 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 440 !strconcat(opstr, "\t$rt, $addr"), 441 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 442 let DecoderMethod = "DecodeMem"; 443 string Constraints = "$src = $rt"; 444} 445 446class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 447 Operand MemOpnd>: 448 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 449 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 450 let DecoderMethod = "DecodeMem"; 451} 452 453multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 454 def #NAME# : LoadLeftRight<opstr, OpNode, RC, mem>, 455 Requires<[NotN64, HasStdEnc]>; 456 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 457 Requires<[IsN64, HasStdEnc]> { 458 let DecoderNamespace = "Mips64"; 459 let isCodeGenOnly = 1; 460 } 461} 462 463multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 464 def #NAME# : StoreLeftRight<opstr, OpNode, RC, mem>, 465 Requires<[NotN64, HasStdEnc]>; 466 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 467 Requires<[IsN64, HasStdEnc]> { 468 let DecoderNamespace = "Mips64"; 469 let isCodeGenOnly = 1; 470 } 471} 472 473// Conditional Branch 474class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 475 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 476 !strconcat(opstr, "\t$rs, $rt, $offset"), 477 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 478 FrmI> { 479 let isBranch = 1; 480 let isTerminator = 1; 481 let hasDelaySlot = 1; 482 let Defs = [AT]; 483} 484 485class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 486 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 487 !strconcat(opstr, "\t$rs, $offset"), 488 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 489 let isBranch = 1; 490 let isTerminator = 1; 491 let hasDelaySlot = 1; 492 let Defs = [AT]; 493} 494 495// SetCC 496class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 497 InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 498 !strconcat(opstr, "\t$rd, $rs, $rt"), 499 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 500 501class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 502 RegisterClass RC>: 503 InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 504 !strconcat(opstr, "\t$rt, $rs, $imm16"), 505 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>; 506 507// Jump 508class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 509 SDPatternOperator targetoperator> : 510 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 511 [(operator targetoperator:$target)], IIBranch, FrmJ> { 512 let isTerminator=1; 513 let isBarrier=1; 514 let hasDelaySlot = 1; 515 let DecoderMethod = "DecodeJumpTarget"; 516 let Defs = [AT]; 517} 518 519// Unconditional branch 520class UncondBranch<string opstr> : 521 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 522 [(br bb:$offset)], IIBranch, FrmI> { 523 let isBranch = 1; 524 let isTerminator = 1; 525 let isBarrier = 1; 526 let hasDelaySlot = 1; 527 let Predicates = [RelocPIC, HasStdEnc]; 528 let Defs = [AT]; 529} 530 531// Base class for indirect branch and return instruction classes. 532let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 533class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 534 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 535 536// Indirect branch 537class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 538 let isBranch = 1; 539 let isIndirectBranch = 1; 540} 541 542// Return instruction 543class RetBase<RegisterClass RC>: JumpFR<RC> { 544 let isReturn = 1; 545 let isCodeGenOnly = 1; 546 let hasCtrlDep = 1; 547 let hasExtraSrcRegAllocReq = 1; 548} 549 550// Jump and Link (Call) 551let isCall=1, hasDelaySlot=1, Defs = [RA] in { 552 class JumpLink<string opstr> : 553 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 554 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 555 let DecoderMethod = "DecodeJumpTarget"; 556 } 557 558 class JumpLinkReg<string opstr, RegisterClass RC>: 559 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), 560 [(MipsJmpLink RC:$rs)], IIBranch, FrmR>; 561 562 class BGEZAL_FT<string opstr, RegisterClass RC> : 563 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 564 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 565 566} 567 568class BAL_FT : 569 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 570 let isBranch = 1; 571 let isTerminator = 1; 572 let isBarrier = 1; 573 let hasDelaySlot = 1; 574 let Defs = [RA]; 575} 576 577// Sync 578let hasSideEffects = 1 in 579class SYNC_FT : 580 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 581 NoItinerary, FrmOther>; 582 583// Mul, Div 584class Mult<string opstr, InstrItinClass itin, RegisterClass RC, 585 list<Register> DefRegs> : 586 InstSE<(outs), (ins RC:$rs, RC:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 587 itin, FrmR> { 588 let isCommutable = 1; 589 let Defs = DefRegs; 590 let neverHasSideEffects = 1; 591} 592 593class Div<SDNode op, string opstr, InstrItinClass itin, RegisterClass RC, 594 list<Register> DefRegs> : 595 InstSE<(outs), (ins RC:$rs, RC:$rt), 596 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RC:$rs, RC:$rt)], itin, 597 FrmR> { 598 let Defs = DefRegs; 599} 600 601// Move from Hi/Lo 602class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 603 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 604 let Uses = UseRegs; 605 let neverHasSideEffects = 1; 606} 607 608class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 609 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 610 let Defs = DefRegs; 611 let neverHasSideEffects = 1; 612} 613 614class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 615 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 616 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 617 let isCodeGenOnly = 1; 618 let DecoderMethod = "DecodeMem"; 619} 620 621// Count Leading Ones/Zeros in Word 622class CountLeading0<string opstr, RegisterClass RC>: 623 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 624 [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>, 625 Requires<[HasBitCount, HasStdEnc]>; 626 627class CountLeading1<string opstr, RegisterClass RC>: 628 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 629 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>, 630 Requires<[HasBitCount, HasStdEnc]>; 631 632 633// Sign Extend in Register. 634class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 635 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 636 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 637 let Predicates = [HasSEInReg, HasStdEnc]; 638} 639 640// Subword Swap 641class SubwordSwap<string opstr, RegisterClass RC>: 642 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 643 NoItinerary, FrmR> { 644 let Predicates = [HasSwap, HasStdEnc]; 645 let neverHasSideEffects = 1; 646} 647 648// Read Hardware 649class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> : 650 InstSE<(outs CPURegClass:$rt), (ins HWRegClass:$rd), "rdhwr\t$rt, $rd", [], 651 IIAlu, FrmR>; 652 653// Ext and Ins 654class ExtBase<string opstr, RegisterClass RC>: 655 InstSE<(outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$size), 656 !strconcat(opstr, " $rt, $rs, $pos, $size"), 657 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$size))], NoItinerary, 658 FrmR> { 659 let Predicates = [HasMips32r2, HasStdEnc]; 660} 661 662class InsBase<string opstr, RegisterClass RC>: 663 InstSE<(outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ins:$size, RC:$src), 664 !strconcat(opstr, " $rt, $rs, $pos, $size"), 665 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$size, RC:$src))], 666 NoItinerary, FrmR> { 667 let Predicates = [HasMips32r2, HasStdEnc]; 668 let Constraints = "$src = $rt"; 669} 670 671// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 672class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 673 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 674 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 675 676multiclass Atomic2Ops32<PatFrag Op> { 677 def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 678 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 679 Requires<[IsN64, HasStdEnc]> { 680 let DecoderNamespace = "Mips64"; 681 } 682} 683 684// Atomic Compare & Swap. 685class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 686 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 687 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 688 689multiclass AtomicCmpSwap32<PatFrag Op> { 690 def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>, 691 Requires<[NotN64, HasStdEnc]>; 692 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 693 Requires<[IsN64, HasStdEnc]> { 694 let DecoderNamespace = "Mips64"; 695 } 696} 697 698class LLBase<string opstr, RegisterClass RC, Operand Mem> : 699 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 700 [], NoItinerary, FrmI> { 701 let DecoderMethod = "DecodeMem"; 702 let mayLoad = 1; 703} 704 705class SCBase<string opstr, RegisterClass RC, Operand Mem> : 706 InstSE<(outs RC:$dst), (ins RC:$rt, Mem:$addr), 707 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 708 let DecoderMethod = "DecodeMem"; 709 let mayStore = 1; 710 let Constraints = "$rt = $dst"; 711} 712 713//===----------------------------------------------------------------------===// 714// Pseudo instructions 715//===----------------------------------------------------------------------===// 716 717// Return RA. 718let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 719def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 720 721let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 722def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 723 [(callseq_start timm:$amt)]>; 724def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 725 [(callseq_end timm:$amt1, timm:$amt2)]>; 726} 727 728let usesCustomInserter = 1 in { 729 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 730 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 731 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 732 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 733 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 734 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 735 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 736 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 737 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 738 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 739 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 740 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 741 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 742 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 743 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 744 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 745 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 746 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 747 748 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 749 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 750 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 751 752 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 753 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 754 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 755} 756 757//===----------------------------------------------------------------------===// 758// Instruction definition 759//===----------------------------------------------------------------------===// 760//===----------------------------------------------------------------------===// 761// MipsI Instructions 762//===----------------------------------------------------------------------===// 763 764/// Arithmetic Instructions (ALU Immediate) 765def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, 766 ADDI_FM<0x9>, IsAsCheapAsAMove; 767def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; 768def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 769def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 770def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; 771def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; 772def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; 773def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 774 775/// Arithmetic Instructions (3-Operand, R-Type) 776def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; 777def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 778def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 779def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; 780def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; 781def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 782def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 783def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 784def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 785def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 786def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>; 787 788/// Shift Instructions 789def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>; 790def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>; 791def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>; 792def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>; 793def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>; 794def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>; 795 796// Rotate Instructions 797let Predicates = [HasMips32r2, HasStdEnc] in { 798 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>; 799 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>; 800} 801 802/// Load and Store Instructions 803/// aligned 804defm LB : LoadM<"lb", sextloadi8, CPURegs>, LW_FM<0x20>; 805defm LBu : LoadM<"lbu", zextloadi8, CPURegs>, LW_FM<0x24>; 806defm LH : LoadM<"lh", sextloadi16, CPURegs>, LW_FM<0x21>; 807defm LHu : LoadM<"lhu", zextloadi16, CPURegs>, LW_FM<0x25>; 808defm LW : LoadM<"lw", load, CPURegs>, LW_FM<0x23>; 809defm SB : StoreM<"sb", truncstorei8, CPURegs>, LW_FM<0x28>; 810defm SH : StoreM<"sh", truncstorei16, CPURegs>, LW_FM<0x29>; 811defm SW : StoreM<"sw", store, CPURegs>, LW_FM<0x2b>; 812 813/// load/store left/right 814defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 815defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 816defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 817defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 818 819def SYNC : SYNC_FT, SYNC_FM; 820 821/// Load-linked, Store-conditional 822let Predicates = [NotN64, HasStdEnc] in { 823 def LL : LLBase<"ll", CPURegs, mem>, LW_FM<0x30>; 824 def SC : SCBase<"sc", CPURegs, mem>, LW_FM<0x38>; 825} 826 827let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 828 def LL_P8 : LLBase<"ll", CPURegs, mem64>, LW_FM<0x30>; 829 def SC_P8 : SCBase<"sc", CPURegs, mem64>, LW_FM<0x38>; 830} 831 832/// Jump and Branch Instructions 833def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 834 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 835def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 836def B : UncondBranch<"b">, B_FM; 837def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 838def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 839def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 840def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 841def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 842def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 843 844def BAL_BR: BAL_FT, BAL_FM; 845 846def JAL : JumpLink<"jal">, FJ<3>; 847def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 848def BGEZAL : BGEZAL_FT<"bgezal", CPURegs>, BGEZAL_FM<0x11>; 849def BLTZAL : BGEZAL_FT<"bltzal", CPURegs>, BGEZAL_FM<0x10>; 850def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 851def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 852 853def RET : RetBase<CPURegs>, MTLO_FM<8>; 854 855/// Multiply and Divide Instructions. 856def MULT : Mult<"mult", IIImul, CPURegs, [HI, LO]>, MULT_FM<0, 0x18>; 857def MULTu : Mult<"multu", IIImul, CPURegs, [HI, LO]>, MULT_FM<0, 0x19>; 858def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegs, [HI, LO]>, MULT_FM<0, 0x1a>; 859def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegs, [HI, LO]>, 860 MULT_FM<0, 0x1b>; 861 862def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 863def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 864def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 865def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 866 867/// Sign Ext In Register Instructions. 868def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 869def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 870 871/// Count Leading 872def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>; 873def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>; 874 875/// Word Swap Bytes Within Halfwords 876def WSBH : SubwordSwap<"wsbh", CPURegs>, SEB_FM<2, 0x20>; 877 878/// No operation. 879/// FIXME: NOP should be an alias of "sll $0, $0, 0". 880def NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM; 881 882// FrameIndexes are legalized when they are operands from load/store 883// instructions. The same not happens for stack address copies, so an 884// add op with mem ComplexPattern is used and the stack address copy 885// can be matched. It's similar to Sparc LEA_ADDRi 886def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 887 888// MADD*/MSUB* 889def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; 890def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; 891def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; 892def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; 893 894def RDHWR : ReadHardware<CPURegs, HWRegs>, RDHWR_FM; 895 896def EXT : ExtBase<"ext", CPURegs>, EXT_FM<0>; 897def INS : InsBase<"ins", CPURegs>, EXT_FM<4>; 898 899/// Move Control Registers From/To CPU Registers 900def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 901 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 902def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 903 904def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 905 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 906def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 907 908def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 909 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 910def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 911 912def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 913 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 914def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 915 916//===----------------------------------------------------------------------===// 917// Instruction aliases 918//===----------------------------------------------------------------------===// 919def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 920def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 921def : InstAlias<"addu $rs,$rt,$imm", 922 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 923def : InstAlias<"add $rs,$rt,$imm", 924 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 925def : InstAlias<"and $rs,$rt,$imm", 926 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 927def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 928def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 929def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 930def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 931def : InstAlias<"slt $rs,$rt,$imm", 932 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 933def : InstAlias<"xor $rs,$rt,$imm", 934 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 935 936//===----------------------------------------------------------------------===// 937// Assembler Pseudo Instructions 938//===----------------------------------------------------------------------===// 939 940class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 941 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 942 !strconcat(instr_asm, "\t$rt, $imm32")> ; 943def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 944 945class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 946 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 947 !strconcat(instr_asm, "\t$rt, $addr")> ; 948def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 949 950class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 951 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 952 !strconcat(instr_asm, "\t$rt, $imm32")> ; 953def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 954 955 956 957//===----------------------------------------------------------------------===// 958// Arbitrary patterns that map to one or more instructions 959//===----------------------------------------------------------------------===// 960 961// Small immediates 962def : MipsPat<(i32 immSExt16:$in), 963 (ADDiu ZERO, imm:$in)>; 964def : MipsPat<(i32 immZExt16:$in), 965 (ORi ZERO, imm:$in)>; 966def : MipsPat<(i32 immLow16Zero:$in), 967 (LUi (HI16 imm:$in))>; 968 969// Arbitrary immediates 970def : MipsPat<(i32 imm:$imm), 971 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 972 973// Carry MipsPatterns 974def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 975 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 976def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 977 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 978def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 979 (ADDiu CPURegs:$src, imm:$imm)>; 980 981// Call 982def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 983 (JAL tglobaladdr:$dst)>; 984def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 985 (JAL texternalsym:$dst)>; 986//def : MipsPat<(MipsJmpLink CPURegs:$dst), 987// (JALR CPURegs:$dst)>; 988 989// Tail call 990def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 991 (TAILCALL tglobaladdr:$dst)>; 992def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 993 (TAILCALL texternalsym:$dst)>; 994// hi/lo relocs 995def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 996def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 997def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 998def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 999def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1000def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1001 1002def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1003def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1004def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1005def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1006def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1007def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1008 1009def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1010 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1011def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1012 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1013def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1014 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1015def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1016 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1017def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1018 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1019 1020// gp_rel relocs 1021def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1022 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1023def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1024 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1025 1026// wrapper_pic 1027class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1028 MipsPat<(MipsWrapper RC:$gp, node:$in), 1029 (ADDiuOp RC:$gp, node:$in)>; 1030 1031def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1032def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1033def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1034def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1035def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1036def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1037 1038// Mips does not have "not", so we expand our way 1039def : MipsPat<(not CPURegs:$in), 1040 (NOR CPURegs:$in, ZERO)>; 1041 1042// extended loads 1043let Predicates = [NotN64, HasStdEnc] in { 1044 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1045 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1046 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1047} 1048let Predicates = [IsN64, HasStdEnc] in { 1049 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1050 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1051 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1052} 1053 1054// peepholes 1055let Predicates = [NotN64, HasStdEnc] in { 1056 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1057} 1058let Predicates = [IsN64, HasStdEnc] in { 1059 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1060} 1061 1062// brcond patterns 1063multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1064 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1065 Instruction SLTiuOp, Register ZEROReg> { 1066def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1067 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1068def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1069 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1070 1071def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1072 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1073def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1074 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1075def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1076 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1077def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1078 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1079 1080def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1081 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1082def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1083 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1084 1085def : MipsPat<(brcond RC:$cond, bb:$dst), 1086 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1087} 1088 1089defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1090 1091// setcc patterns 1092multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1093 Instruction SLTuOp, Register ZEROReg> { 1094 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1095 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1096 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1097 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1098} 1099 1100multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1101 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1102 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1103 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1104 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1105} 1106 1107multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1108 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1109 (SLTOp RC:$rhs, RC:$lhs)>; 1110 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1111 (SLTuOp RC:$rhs, RC:$lhs)>; 1112} 1113 1114multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1115 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1116 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1117 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1118 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1119} 1120 1121multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1122 Instruction SLTiuOp> { 1123 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1124 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1125 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1126 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1127} 1128 1129defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1130defm : SetlePats<CPURegs, SLT, SLTu>; 1131defm : SetgtPats<CPURegs, SLT, SLTu>; 1132defm : SetgePats<CPURegs, SLT, SLTu>; 1133defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1134 1135// bswap pattern 1136def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1137 1138//===----------------------------------------------------------------------===// 1139// Floating Point Support 1140//===----------------------------------------------------------------------===// 1141 1142include "MipsInstrFPU.td" 1143include "Mips64InstrInfo.td" 1144include "MipsCondMov.td" 1145 1146// 1147// Mips16 1148 1149include "Mips16InstrFormats.td" 1150include "Mips16InstrInfo.td" 1151 1152// DSP 1153include "MipsDSPInstrFormats.td" 1154include "MipsDSPInstrInfo.td" 1155 1156