MipsInstrInfo.td revision dc2f79274021a590d6b72acd741117068c3e49bd
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 76 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 77 78// These are target-independent nodes, but have target-specific formats. 79def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 80 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 81def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 82 [SDNPHasChain, SDNPSideEffect, 83 SDNPOptInGlue, SDNPOutGlue]>; 84 85// MAdd*/MSub* nodes 86def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 87 [SDNPOptInGlue, SDNPOutGlue]>; 88def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 89 [SDNPOptInGlue, SDNPOutGlue]>; 90def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 91 [SDNPOptInGlue, SDNPOutGlue]>; 92def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 93 [SDNPOptInGlue, SDNPOutGlue]>; 94 95// DivRem(u) nodes 96def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 97 [SDNPOutGlue]>; 98def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 99 [SDNPOutGlue]>; 100 101// Target constant nodes that are not part of any isel patterns and remain 102// unchanged can cause instructions with illegal operands to be emitted. 103// Wrapper node patterns give the instruction selector a chance to replace 104// target constant nodes that would otherwise remain unchanged with ADDiu 105// nodes. Without these wrapper node patterns, the following conditional move 106// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 107// compiled: 108// movn %got(d)($gp), %got(c)($gp), $4 109// This instruction is illegal since movn can take only register operands. 110 111def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 112 113def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 114 115def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 116def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 117 118def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 120def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 122def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 124def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 126def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 128def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 132def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134 135//===----------------------------------------------------------------------===// 136// Mips Instruction Predicate Definitions. 137//===----------------------------------------------------------------------===// 138def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 139 AssemblerPredicate<"FeatureSEInReg">; 140def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 141 AssemblerPredicate<"FeatureBitCount">; 142def HasSwap : Predicate<"Subtarget.hasSwap()">, 143 AssemblerPredicate<"FeatureSwap">; 144def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 145 AssemblerPredicate<"FeatureCondMov">; 146def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 147 AssemblerPredicate<"FeatureFPIdx">; 148def HasMips32 : Predicate<"Subtarget.hasMips32()">, 149 AssemblerPredicate<"FeatureMips32">; 150def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 151 AssemblerPredicate<"FeatureMips32r2">; 152def HasMips64 : Predicate<"Subtarget.hasMips64()">, 153 AssemblerPredicate<"FeatureMips64">; 154def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 155 AssemblerPredicate<"!FeatureMips64">; 156def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 157 AssemblerPredicate<"FeatureMips64r2">; 158def IsN64 : Predicate<"Subtarget.isABI_N64()">, 159 AssemblerPredicate<"FeatureN64">; 160def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 161 AssemblerPredicate<"!FeatureN64">; 162def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 163 AssemblerPredicate<"FeatureMips16">; 164def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 165 AssemblerPredicate<"FeatureMips32">; 166def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 167 AssemblerPredicate<"FeatureMips32">; 168def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 169 AssemblerPredicate<"FeatureMips32">; 170def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 171 AssemblerPredicate<"!FeatureMips16">; 172 173class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 174 let Predicates = [HasStdEnc]; 175} 176 177class IsCommutable { 178 bit isCommutable = 1; 179} 180 181class IsBranch { 182 bit isBranch = 1; 183} 184 185class IsReturn { 186 bit isReturn = 1; 187} 188 189class IsCall { 190 bit isCall = 1; 191} 192 193class IsTailCall { 194 bit isCall = 1; 195 bit isTerminator = 1; 196 bit isReturn = 1; 197 bit isBarrier = 1; 198 bit hasExtraSrcRegAllocReq = 1; 199 bit isCodeGenOnly = 1; 200} 201 202class IsAsCheapAsAMove { 203 bit isAsCheapAsAMove = 1; 204} 205 206class NeverHasSideEffects { 207 bit neverHasSideEffects = 1; 208} 209 210//===----------------------------------------------------------------------===// 211// Instruction format superclass 212//===----------------------------------------------------------------------===// 213 214include "MipsInstrFormats.td" 215 216//===----------------------------------------------------------------------===// 217// Mips Operand, Complex Patterns and Transformations Definitions. 218//===----------------------------------------------------------------------===// 219 220// Instruction operand types 221def jmptarget : Operand<OtherVT> { 222 let EncoderMethod = "getJumpTargetOpValue"; 223} 224def brtarget : Operand<OtherVT> { 225 let EncoderMethod = "getBranchTargetOpValue"; 226 let OperandType = "OPERAND_PCREL"; 227 let DecoderMethod = "DecodeBranchTarget"; 228} 229def calltarget : Operand<iPTR> { 230 let EncoderMethod = "getJumpTargetOpValue"; 231} 232def calltarget64: Operand<i64>; 233def simm16 : Operand<i32> { 234 let DecoderMethod= "DecodeSimm16"; 235} 236 237def simm20 : Operand<i32> { 238} 239 240def simm16_64 : Operand<i64>; 241def shamt : Operand<i32>; 242 243// Unsigned Operand 244def uimm16 : Operand<i32> { 245 let PrintMethod = "printUnsignedImm"; 246} 247 248def MipsMemAsmOperand : AsmOperandClass { 249 let Name = "Mem"; 250 let ParserMethod = "parseMemOperand"; 251} 252 253// Address operand 254def mem : Operand<i32> { 255 let PrintMethod = "printMemOperand"; 256 let MIOperandInfo = (ops CPURegs, simm16); 257 let EncoderMethod = "getMemEncoding"; 258 let ParserMatchClass = MipsMemAsmOperand; 259} 260 261def mem64 : Operand<i64> { 262 let PrintMethod = "printMemOperand"; 263 let MIOperandInfo = (ops CPU64Regs, simm16_64); 264 let EncoderMethod = "getMemEncoding"; 265 let ParserMatchClass = MipsMemAsmOperand; 266} 267 268def mem_ea : Operand<i32> { 269 let PrintMethod = "printMemOperandEA"; 270 let MIOperandInfo = (ops CPURegs, simm16); 271 let EncoderMethod = "getMemEncoding"; 272} 273 274def mem_ea_64 : Operand<i64> { 275 let PrintMethod = "printMemOperandEA"; 276 let MIOperandInfo = (ops CPU64Regs, simm16_64); 277 let EncoderMethod = "getMemEncoding"; 278} 279 280// size operand of ext instruction 281def size_ext : Operand<i32> { 282 let EncoderMethod = "getSizeExtEncoding"; 283 let DecoderMethod = "DecodeExtSize"; 284} 285 286// size operand of ins instruction 287def size_ins : Operand<i32> { 288 let EncoderMethod = "getSizeInsEncoding"; 289 let DecoderMethod = "DecodeInsSize"; 290} 291 292// Transformation Function - get the lower 16 bits. 293def LO16 : SDNodeXForm<imm, [{ 294 return getImm(N, N->getZExtValue() & 0xFFFF); 295}]>; 296 297// Transformation Function - get the higher 16 bits. 298def HI16 : SDNodeXForm<imm, [{ 299 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 300}]>; 301 302// Node immediate fits as 16-bit sign extended on target immediate. 303// e.g. addi, andi 304def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 305 306// Node immediate fits as 16-bit sign extended on target immediate. 307// e.g. addi, andi 308def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 309 310// Node immediate fits as 15-bit sign extended on target immediate. 311// e.g. addi, andi 312def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 313 314// Node immediate fits as 16-bit zero extended on target immediate. 315// The LO16 param means that only the lower 16 bits of the node 316// immediate are caught. 317// e.g. addiu, sltiu 318def immZExt16 : PatLeaf<(imm), [{ 319 if (N->getValueType(0) == MVT::i32) 320 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 321 else 322 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 323}], LO16>; 324 325// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 326def immLow16Zero : PatLeaf<(imm), [{ 327 int64_t Val = N->getSExtValue(); 328 return isInt<32>(Val) && !(Val & 0xffff); 329}]>; 330 331// shamt field must fit in 5 bits. 332def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 333 334// Mips Address Mode! SDNode frameindex could possibily be a match 335// since load and store instructions from stack used it. 336def addr : 337 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex], [SDNPWantParent]>; 338 339def addrRegImm : 340 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex], [SDNPWantParent]>; 341 342def addrDefault : 343 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex], [SDNPWantParent]>; 344 345//===----------------------------------------------------------------------===// 346// Instructions specific format 347//===----------------------------------------------------------------------===// 348 349// Arithmetic and logical instructions with 3 register operands. 350class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 351 InstrItinClass Itin = NoItinerary, 352 SDPatternOperator OpNode = null_frag>: 353 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 354 !strconcat(opstr, "\t$rd, $rs, $rt"), 355 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { 356 let isCommutable = isComm; 357 let isReMaterializable = 1; 358 string BaseOpcode; 359 string Arch; 360} 361 362// Arithmetic and logical instructions with 2 register operands. 363class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 364 SDPatternOperator imm_type = null_frag, 365 SDPatternOperator OpNode = null_frag> : 366 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 367 !strconcat(opstr, "\t$rt, $rs, $imm16"), 368 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> { 369 let isReMaterializable = 1; 370} 371 372// Arithmetic Multiply ADD/SUB 373class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> : 374 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 375 !strconcat(opstr, "\t$rs, $rt"), 376 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> { 377 let Defs = [HI, LO]; 378 let Uses = [HI, LO]; 379 let isCommutable = isComm; 380} 381 382// Logical 383class LogicNOR<string opstr, RegisterOperand RC>: 384 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 385 !strconcat(opstr, "\t$rd, $rs, $rt"), 386 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 387 let isCommutable = 1; 388} 389 390// Shifts 391class shift_rotate_imm<string opstr, Operand ImmOpnd, 392 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 393 SDPatternOperator PF = null_frag> : 394 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 395 !strconcat(opstr, "\t$rd, $rt, $shamt"), 396 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 397 398class shift_rotate_reg<string opstr, RegisterOperand RC, 399 SDPatternOperator OpNode = null_frag>: 400 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 401 !strconcat(opstr, "\t$rd, $rt, $rs"), 402 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>; 403 404// Load Upper Imediate 405class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 406 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 407 [], IIAlu, FrmI>, IsAsCheapAsAMove { 408 let neverHasSideEffects = 1; 409 let isReMaterializable = 1; 410} 411 412class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 413 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 414 bits<21> addr; 415 let Inst{25-21} = addr{20-16}; 416 let Inst{15-0} = addr{15-0}; 417 let DecoderMethod = "DecodeMem"; 418} 419 420// Memory Load/Store 421class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 422 Operand MemOpnd> : 423 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 424 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 425 let DecoderMethod = "DecodeMem"; 426 let canFoldAsLoad = 1; 427} 428 429class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 430 Operand MemOpnd> : 431 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 432 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 433 let DecoderMethod = "DecodeMem"; 434} 435 436multiclass LoadM<string opstr, RegisterClass RC, 437 SDPatternOperator OpNode = null_frag> { 438 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 439 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 440 let DecoderNamespace = "Mips64"; 441 let isCodeGenOnly = 1; 442 } 443} 444 445multiclass StoreM<string opstr, RegisterClass RC, 446 SDPatternOperator OpNode = null_frag> { 447 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 448 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 449 let DecoderNamespace = "Mips64"; 450 let isCodeGenOnly = 1; 451 } 452} 453 454// Load/Store Left/Right 455let canFoldAsLoad = 1 in 456class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 457 Operand MemOpnd> : 458 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 459 !strconcat(opstr, "\t$rt, $addr"), 460 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 461 let DecoderMethod = "DecodeMem"; 462 string Constraints = "$src = $rt"; 463} 464 465class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 466 Operand MemOpnd>: 467 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 468 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 469 let DecoderMethod = "DecodeMem"; 470} 471 472multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 473 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 474 Requires<[NotN64, HasStdEnc]>; 475 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 476 Requires<[IsN64, HasStdEnc]> { 477 let DecoderNamespace = "Mips64"; 478 let isCodeGenOnly = 1; 479 } 480} 481 482multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 483 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 484 Requires<[NotN64, HasStdEnc]>; 485 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 486 Requires<[IsN64, HasStdEnc]> { 487 let DecoderNamespace = "Mips64"; 488 let isCodeGenOnly = 1; 489 } 490} 491 492// Conditional Branch 493class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 494 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 495 !strconcat(opstr, "\t$rs, $rt, $offset"), 496 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 497 FrmI> { 498 let isBranch = 1; 499 let isTerminator = 1; 500 let hasDelaySlot = 1; 501 let Defs = [AT]; 502} 503 504class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 505 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 506 !strconcat(opstr, "\t$rs, $offset"), 507 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 508 let isBranch = 1; 509 let isTerminator = 1; 510 let hasDelaySlot = 1; 511 let Defs = [AT]; 512} 513 514// SetCC 515class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 516 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 517 !strconcat(opstr, "\t$rd, $rs, $rt"), 518 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 519 520class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 521 RegisterClass RC>: 522 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 523 !strconcat(opstr, "\t$rt, $rs, $imm16"), 524 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 525 IIAlu, FrmI>; 526 527// Jump 528class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 529 SDPatternOperator targetoperator> : 530 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 531 [(operator targetoperator:$target)], IIBranch, FrmJ> { 532 let isTerminator=1; 533 let isBarrier=1; 534 let hasDelaySlot = 1; 535 let DecoderMethod = "DecodeJumpTarget"; 536 let Defs = [AT]; 537} 538 539// Unconditional branch 540class UncondBranch<string opstr> : 541 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 542 [(br bb:$offset)], IIBranch, FrmI> { 543 let isBranch = 1; 544 let isTerminator = 1; 545 let isBarrier = 1; 546 let hasDelaySlot = 1; 547 let Predicates = [RelocPIC, HasStdEnc]; 548 let Defs = [AT]; 549} 550 551// Base class for indirect branch and return instruction classes. 552let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 553class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 554 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 555 556// Indirect branch 557class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 558 let isBranch = 1; 559 let isIndirectBranch = 1; 560} 561 562// Return instruction 563class RetBase<RegisterClass RC>: JumpFR<RC> { 564 let isReturn = 1; 565 let isCodeGenOnly = 1; 566 let hasCtrlDep = 1; 567 let hasExtraSrcRegAllocReq = 1; 568} 569 570// Jump and Link (Call) 571let isCall=1, hasDelaySlot=1, Defs = [RA] in { 572 class JumpLink<string opstr> : 573 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 574 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 575 let DecoderMethod = "DecodeJumpTarget"; 576 } 577 578 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 579 Register RetReg>: 580 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 581 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 582 583 class JumpLinkReg<string opstr, RegisterClass RC>: 584 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 585 [], IIBranch, FrmR>; 586 587 class BGEZAL_FT<string opstr, RegisterOperand RO> : 588 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 589 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 590 591} 592 593class BAL_FT : 594 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 595 let isBranch = 1; 596 let isTerminator = 1; 597 let isBarrier = 1; 598 let hasDelaySlot = 1; 599 let Defs = [RA]; 600} 601 602// Sync 603let hasSideEffects = 1 in 604class SYNC_FT : 605 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 606 NoItinerary, FrmOther>; 607 608// Mul, Div 609class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 610 list<Register> DefRegs> : 611 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 612 itin, FrmR> { 613 let isCommutable = 1; 614 let Defs = DefRegs; 615 let neverHasSideEffects = 1; 616} 617 618class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO, 619 list<Register> DefRegs> : 620 InstSE<(outs), (ins RO:$rs, RO:$rt), 621 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin, 622 FrmR> { 623 let Defs = DefRegs; 624} 625 626// Move from Hi/Lo 627class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 628 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 629 let Uses = UseRegs; 630 let neverHasSideEffects = 1; 631} 632 633class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 634 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 635 let Defs = DefRegs; 636 let neverHasSideEffects = 1; 637} 638 639class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 640 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 641 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 642 let isCodeGenOnly = 1; 643 let DecoderMethod = "DecodeMem"; 644} 645 646// Count Leading Ones/Zeros in Word 647class CountLeading0<string opstr, RegisterOperand RO>: 648 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 649 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 650 Requires<[HasBitCount, HasStdEnc]>; 651 652class CountLeading1<string opstr, RegisterOperand RO>: 653 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 654 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 655 Requires<[HasBitCount, HasStdEnc]>; 656 657 658// Sign Extend in Register. 659class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 660 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 661 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 662 let Predicates = [HasSEInReg, HasStdEnc]; 663} 664 665// Subword Swap 666class SubwordSwap<string opstr, RegisterOperand RO>: 667 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 668 NoItinerary, FrmR> { 669 let Predicates = [HasSwap, HasStdEnc]; 670 let neverHasSideEffects = 1; 671} 672 673// Read Hardware 674class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 675 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 676 IIAlu, FrmR>; 677 678// Ext and Ins 679class ExtBase<string opstr, RegisterOperand RO>: 680 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 681 !strconcat(opstr, " $rt, $rs, $pos, $size"), 682 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 683 FrmR> { 684 let Predicates = [HasMips32r2, HasStdEnc]; 685} 686 687class InsBase<string opstr, RegisterOperand RO>: 688 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 689 !strconcat(opstr, " $rt, $rs, $pos, $size"), 690 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 691 NoItinerary, FrmR> { 692 let Predicates = [HasMips32r2, HasStdEnc]; 693 let Constraints = "$src = $rt"; 694} 695 696// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 697class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 698 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 699 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 700 701multiclass Atomic2Ops32<PatFrag Op> { 702 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 703 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 704 Requires<[IsN64, HasStdEnc]> { 705 let DecoderNamespace = "Mips64"; 706 } 707} 708 709// Atomic Compare & Swap. 710class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 711 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 712 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 713 714multiclass AtomicCmpSwap32<PatFrag Op> { 715 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 716 Requires<[NotN64, HasStdEnc]>; 717 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 718 Requires<[IsN64, HasStdEnc]> { 719 let DecoderNamespace = "Mips64"; 720 } 721} 722 723class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 724 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 725 [], NoItinerary, FrmI> { 726 let DecoderMethod = "DecodeMem"; 727 let mayLoad = 1; 728} 729 730class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 731 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 732 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 733 let DecoderMethod = "DecodeMem"; 734 let mayStore = 1; 735 let Constraints = "$rt = $dst"; 736} 737 738class MFC3OP<dag outs, dag ins, string asmstr> : 739 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 740 741//===----------------------------------------------------------------------===// 742// Pseudo instructions 743//===----------------------------------------------------------------------===// 744 745// Return RA. 746let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 747def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 748 749let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 750def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 751 [(callseq_start timm:$amt)]>; 752def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 753 [(callseq_end timm:$amt1, timm:$amt2)]>; 754} 755 756let usesCustomInserter = 1 in { 757 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 758 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 759 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 760 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 761 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 762 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 763 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 764 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 765 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 766 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 767 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 768 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 769 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 770 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 771 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 772 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 773 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 774 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 775 776 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 777 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 778 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 779 780 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 781 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 782 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 783} 784 785//===----------------------------------------------------------------------===// 786// Instruction definition 787//===----------------------------------------------------------------------===// 788//===----------------------------------------------------------------------===// 789// MipsI Instructions 790//===----------------------------------------------------------------------===// 791 792/// Arithmetic Instructions (ALU Immediate) 793def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 794 ADDI_FM<0x9>, IsAsCheapAsAMove; 795def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 796def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 797def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 798def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 799 ADDI_FM<0xc>; 800def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 801 ADDI_FM<0xd>; 802def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 803 ADDI_FM<0xe>; 804def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 805 806/// Arithmetic Instructions (3-Operand, R-Type) 807def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>; 808def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 809def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 810def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 811def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 812def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 813def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 814def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 815def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 816def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 817def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 818 819/// Shift Instructions 820def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 821 SRA_FM<0, 0>; 822def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 823 SRA_FM<2, 0>; 824def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 825 SRA_FM<3, 0>; 826def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 827def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 828def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 829 830// Rotate Instructions 831let Predicates = [HasMips32r2, HasStdEnc] in { 832 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>, 833 SRA_FM<2, 1>; 834 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>; 835} 836 837/// Load and Store Instructions 838/// aligned 839defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 840defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; 841defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; 842defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 843defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; 844defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 845defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 846defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 847 848/// load/store left/right 849defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 850defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 851defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 852defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 853 854def SYNC : SYNC_FT, SYNC_FM; 855 856/// Load-linked, Store-conditional 857let Predicates = [NotN64, HasStdEnc] in { 858 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 859 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 860} 861 862let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 863 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 864 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 865} 866 867/// Jump and Branch Instructions 868def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 869 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 870def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 871def B : UncondBranch<"b">, B_FM; 872def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 873def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 874def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 875def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 876def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 877def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 878 879def BAL_BR: BAL_FT, BAL_FM; 880 881def JAL : JumpLink<"jal">, FJ<3>; 882def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 883def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 884def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 885def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 886def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 887def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 888 889def RET : RetBase<CPURegs>, MTLO_FM<8>; 890 891// Exception handling related node and instructions. 892// The conversion sequence is: 893// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 894// MIPSeh_return -> (stack change + indirect branch) 895// 896// MIPSeh_return takes the place of regular return instruction 897// but takes two arguments (V1, V0) which are used for storing 898// the offset and return address respectively. 899def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 900 901def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 902 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 903 904let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 905 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 906 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 907 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 908 CPU64Regs:$dst), 909 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 910} 911 912/// Multiply and Divide Instructions. 913def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>; 914def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>; 915def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>, 916 MULT_FM<0, 0x1a>; 917def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>, 918 MULT_FM<0, 0x1b>; 919 920def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 921def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 922def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 923def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 924 925/// Sign Ext In Register Instructions. 926def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 927def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 928 929/// Count Leading 930def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 931def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 932 933/// Word Swap Bytes Within Halfwords 934def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 935 936/// No operation. 937def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 938 939// FrameIndexes are legalized when they are operands from load/store 940// instructions. The same not happens for stack address copies, so an 941// add op with mem ComplexPattern is used and the stack address copy 942// can be matched. It's similar to Sparc LEA_ADDRi 943def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 944 945// MADD*/MSUB* 946def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; 947def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; 948def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; 949def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; 950 951def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 952 953def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 954def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 955 956/// Move Control Registers From/To CPU Registers 957def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 958 (ins CPURegsOpnd:$rd, uimm16:$sel), 959 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 960 961def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 962 (ins CPURegsOpnd:$rt), 963 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 964 965def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 966 (ins CPURegsOpnd:$rd, uimm16:$sel), 967 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 968 969def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 970 (ins CPURegsOpnd:$rt), 971 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 972 973//===----------------------------------------------------------------------===// 974// Instruction aliases 975//===----------------------------------------------------------------------===// 976def : InstAlias<"move $dst, $src", 977 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 978 Requires<[NotMips64]>; 979def : InstAlias<"move $dst, $src", 980 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 0>, 981 Requires<[NotMips64]>; 982def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 983def : InstAlias<"addu $rs, $rt, $imm", 984 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 985def : InstAlias<"add $rs, $rt, $imm", 986 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 987def : InstAlias<"and $rs, $rt, $imm", 988 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 989def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 990 Requires<[NotMips64]>; 991def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 992def : InstAlias<"not $rt, $rs", 993 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 994def : InstAlias<"neg $rt, $rs", 995 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 996def : InstAlias<"negu $rt, $rs", 997 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 998def : InstAlias<"slt $rs, $rt, $imm", 999 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1000def : InstAlias<"xor $rs, $rt, $imm", 1001 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 1002 Requires<[NotMips64]>; 1003def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1004def : InstAlias<"mfc0 $rt, $rd", 1005 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1006def : InstAlias<"mtc0 $rt, $rd", 1007 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1008def : InstAlias<"mfc2 $rt, $rd", 1009 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1010def : InstAlias<"mtc2 $rt, $rd", 1011 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1012 1013//===----------------------------------------------------------------------===// 1014// Assembler Pseudo Instructions 1015//===----------------------------------------------------------------------===// 1016 1017class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1018 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1019 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1020def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1021 1022class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1023 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1024 !strconcat(instr_asm, "\t$rt, $addr")> ; 1025def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1026 1027class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1028 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1029 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1030def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1031 1032 1033 1034//===----------------------------------------------------------------------===// 1035// Arbitrary patterns that map to one or more instructions 1036//===----------------------------------------------------------------------===// 1037 1038// Small immediates 1039def : MipsPat<(i32 immSExt16:$in), 1040 (ADDiu ZERO, imm:$in)>; 1041def : MipsPat<(i32 immZExt16:$in), 1042 (ORi ZERO, imm:$in)>; 1043def : MipsPat<(i32 immLow16Zero:$in), 1044 (LUi (HI16 imm:$in))>; 1045 1046// Arbitrary immediates 1047def : MipsPat<(i32 imm:$imm), 1048 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1049 1050// Carry MipsPatterns 1051def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1052 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1053def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1054 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1055def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1056 (ADDiu CPURegs:$src, imm:$imm)>; 1057 1058// Call 1059def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1060 (JAL tglobaladdr:$dst)>; 1061def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1062 (JAL texternalsym:$dst)>; 1063//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1064// (JALR CPURegs:$dst)>; 1065 1066// Tail call 1067def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1068 (TAILCALL tglobaladdr:$dst)>; 1069def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1070 (TAILCALL texternalsym:$dst)>; 1071// hi/lo relocs 1072def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1073def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1074def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1075def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1076def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1077def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1078 1079def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1080def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1081def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1082def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1083def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1084def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1085 1086def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1087 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1088def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1089 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1090def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1091 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1092def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1093 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1094def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1095 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1096 1097// gp_rel relocs 1098def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1099 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1100def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1101 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1102 1103// wrapper_pic 1104class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1105 MipsPat<(MipsWrapper RC:$gp, node:$in), 1106 (ADDiuOp RC:$gp, node:$in)>; 1107 1108def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1109def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1110def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1111def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1112def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1113def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1114 1115// Mips does not have "not", so we expand our way 1116def : MipsPat<(not CPURegs:$in), 1117 (NOR CPURegsOpnd:$in, ZERO)>; 1118 1119// extended loads 1120let Predicates = [NotN64, HasStdEnc] in { 1121 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1122 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1123 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1124} 1125let Predicates = [IsN64, HasStdEnc] in { 1126 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1127 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1128 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1129} 1130 1131// peepholes 1132let Predicates = [NotN64, HasStdEnc] in { 1133 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1134} 1135let Predicates = [IsN64, HasStdEnc] in { 1136 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1137} 1138 1139// brcond patterns 1140multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1141 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1142 Instruction SLTiuOp, Register ZEROReg> { 1143def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1144 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1145def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1146 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1147 1148def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1149 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1150def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1151 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1152def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1153 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1154def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1155 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1156 1157def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1158 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1159def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1160 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1161 1162def : MipsPat<(brcond RC:$cond, bb:$dst), 1163 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1164} 1165 1166defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1167 1168// setcc patterns 1169multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1170 Instruction SLTuOp, Register ZEROReg> { 1171 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1172 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1173 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1174 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1175} 1176 1177multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1178 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1179 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1180 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1181 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1182} 1183 1184multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1185 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1186 (SLTOp RC:$rhs, RC:$lhs)>; 1187 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1188 (SLTuOp RC:$rhs, RC:$lhs)>; 1189} 1190 1191multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1192 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1193 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1194 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1195 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1196} 1197 1198multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1199 Instruction SLTiuOp> { 1200 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1201 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1202 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1203 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1204} 1205 1206defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1207defm : SetlePats<CPURegs, SLT, SLTu>; 1208defm : SetgtPats<CPURegs, SLT, SLTu>; 1209defm : SetgePats<CPURegs, SLT, SLTu>; 1210defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1211 1212// bswap pattern 1213def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1214 1215//===----------------------------------------------------------------------===// 1216// Floating Point Support 1217//===----------------------------------------------------------------------===// 1218 1219include "MipsInstrFPU.td" 1220include "Mips64InstrInfo.td" 1221include "MipsCondMov.td" 1222 1223// 1224// Mips16 1225 1226include "Mips16InstrFormats.td" 1227include "Mips16InstrInfo.td" 1228 1229// DSP 1230include "MipsDSPInstrFormats.td" 1231include "MipsDSPInstrInfo.td" 1232 1233