MipsInstrInfo.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 27def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 29def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 34def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 35 36def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 37 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Tail call 56def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 58 59// Hi and Lo nodes are used to handle global addresses. Used on 60// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 61// static model. (nothing to do with Mips Registers Hi and Lo) 62def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 63def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 64def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 65 66// TlsGd node is used to handle General Dynamic TLS 67def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 68 69// TprelHi and TprelLo nodes are used to handle Local Exec TLS 70def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 71def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 72 73// Thread pointer 74def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 75 76// Return 77def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 79 80// These are target-independent nodes, but have target-specific formats. 81def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 83def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 84 [SDNPHasChain, SDNPSideEffect, 85 SDNPOptInGlue, SDNPOutGlue]>; 86 87// Nodes used to extract LO/HI registers. 88def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 89def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 90 91// Node used to insert 32-bit integers to LOHI register pair. 92def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 93 94// Mult nodes. 95def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 97 98// MAdd*/MSub* nodes 99def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 101def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 103 104// DivRem(u) nodes 105def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 106def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 107def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 108 [SDNPOutGlue]>; 109def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 110 [SDNPOutGlue]>; 111 112// Target constant nodes that are not part of any isel patterns and remain 113// unchanged can cause instructions with illegal operands to be emitted. 114// Wrapper node patterns give the instruction selector a chance to replace 115// target constant nodes that would otherwise remain unchanged with ADDiu 116// nodes. Without these wrapper node patterns, the following conditional move 117// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 118// compiled: 119// movn %got(d)($gp), %got(c)($gp), $4 120// This instruction is illegal since movn can take only register operands. 121 122def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 123 124def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 125 126def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 127def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 128 129def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 131def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 133def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 135def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 137def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 139def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 141def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 143def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 145 146//===----------------------------------------------------------------------===// 147// Mips Instruction Predicate Definitions. 148//===----------------------------------------------------------------------===// 149def HasMips2 : Predicate<"Subtarget.hasMips2()">, 150 AssemblerPredicate<"FeatureMips2">; 151def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">, 152 AssemblerPredicate<"FeatureMips3_32">; 153def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">, 154 AssemblerPredicate<"FeatureMips3_32r2">; 155def HasMips3 : Predicate<"Subtarget.hasMips3()">, 156 AssemblerPredicate<"FeatureMips3">; 157def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">, 158 AssemblerPredicate<"FeatureMips4_32">; 159def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">, 160 AssemblerPredicate<"FeatureMips4_32r2">; 161def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">, 162 AssemblerPredicate<"FeatureMips5_32r2">; 163def HasMips32 : Predicate<"Subtarget.hasMips32()">, 164 AssemblerPredicate<"FeatureMips32">; 165def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 166 AssemblerPredicate<"FeatureMips32r2">; 167def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">, 168 AssemblerPredicate<"FeatureMips32r6">; 169def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">, 170 AssemblerPredicate<"!FeatureMips32r6">; 171def IsGP64bit : Predicate<"Subtarget.isGP64bit()">, 172 AssemblerPredicate<"FeatureGP64Bit">; 173def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">, 174 AssemblerPredicate<"!FeatureGP64Bit">; 175def HasMips64 : Predicate<"Subtarget.hasMips64()">, 176 AssemblerPredicate<"FeatureMips64">; 177def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 178 AssemblerPredicate<"FeatureMips64r2">; 179def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">, 180 AssemblerPredicate<"FeatureMips64r6">; 181def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">, 182 AssemblerPredicate<"!FeatureMips64r6">; 183def IsN64 : Predicate<"Subtarget.isABI_N64()">, 184 AssemblerPredicate<"FeatureN64">; 185def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 186 AssemblerPredicate<"FeatureMips16">; 187def HasCnMips : Predicate<"Subtarget.hasCnMips()">, 188 AssemblerPredicate<"FeatureCnMips">; 189def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 190 AssemblerPredicate<"FeatureMips32">; 191def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 192 AssemblerPredicate<"FeatureMips32">; 193def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 194def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 195 AssemblerPredicate<"!FeatureMips16">; 196def NotDSP : Predicate<"!Subtarget.hasDSP()">; 197def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, 198 AssemblerPredicate<"FeatureMicroMips">; 199def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, 200 AssemblerPredicate<"!FeatureMicroMips">; 201def IsLE : Predicate<"Subtarget.isLittle()">; 202def IsBE : Predicate<"!Subtarget.isLittle()">; 203def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">; 204 205//===----------------------------------------------------------------------===// 206// Mips GPR size adjectives. 207// They are mutually exclusive. 208//===----------------------------------------------------------------------===// 209 210class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; } 211class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; } 212 213//===----------------------------------------------------------------------===// 214// Mips ISA/ASE membership and instruction group membership adjectives. 215// They are mutually exclusive. 216//===----------------------------------------------------------------------===// 217 218// FIXME: I'd prefer to use additive predicates to build the instruction sets 219// but we are short on assembler feature bits at the moment. Using a 220// subtractive predicate will hopefully keep us under the 32 predicate 221// limit long enough to develop an alternative way to handle P1||P2 222// predicates. 223class ISA_MIPS1_NOT_32R6_64R6 { 224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6]; 225} 226class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; } 227class ISA_MIPS2_NOT_32R6_64R6 { 228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6]; 229} 230class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; } 231class ISA_MIPS3_NOT_32R6_64R6 { 232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6]; 233} 234class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; } 235class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; } 236class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; } 237class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; } 238class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; } 239class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; } 240 241// The portions of MIPS-III that were also added to MIPS32 242class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; } 243 244// The portions of MIPS-III that were also added to MIPS32 245class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; } 246 247// The portions of MIPS-IV that were also added to MIPS32 248class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; } 249 250// The portions of MIPS-IV that were also added to MIPS32R2 251class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; } 252 253// The portions of MIPS-V that were also added to MIPS32R2 254class INSN_MIPS5_32R2 { list<Predicate> InsnPredicates = [HasMips5_32r2]; } 255 256//===----------------------------------------------------------------------===// 257 258class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl { 259 let EncodingPredicates = [HasStdEnc]; 260} 261 262class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> : 263 InstAlias<Asm, Result, Emit>, PredicateControl; 264 265class IsCommutable { 266 bit isCommutable = 1; 267} 268 269class IsBranch { 270 bit isBranch = 1; 271} 272 273class IsReturn { 274 bit isReturn = 1; 275} 276 277class IsCall { 278 bit isCall = 1; 279} 280 281class IsTailCall { 282 bit isCall = 1; 283 bit isTerminator = 1; 284 bit isReturn = 1; 285 bit isBarrier = 1; 286 bit hasExtraSrcRegAllocReq = 1; 287 bit isCodeGenOnly = 1; 288} 289 290class IsAsCheapAsAMove { 291 bit isAsCheapAsAMove = 1; 292} 293 294class NeverHasSideEffects { 295 bit neverHasSideEffects = 1; 296} 297 298//===----------------------------------------------------------------------===// 299// Instruction format superclass 300//===----------------------------------------------------------------------===// 301 302include "MipsInstrFormats.td" 303 304//===----------------------------------------------------------------------===// 305// Mips Operand, Complex Patterns and Transformations Definitions. 306//===----------------------------------------------------------------------===// 307 308def MipsJumpTargetAsmOperand : AsmOperandClass { 309 let Name = "JumpTarget"; 310 let ParserMethod = "ParseJumpTarget"; 311 let PredicateMethod = "isImm"; 312 let RenderMethod = "addImmOperands"; 313} 314 315// Instruction operand types 316def jmptarget : Operand<OtherVT> { 317 let EncoderMethod = "getJumpTargetOpValue"; 318 let ParserMatchClass = MipsJumpTargetAsmOperand; 319} 320def brtarget : Operand<OtherVT> { 321 let EncoderMethod = "getBranchTargetOpValue"; 322 let OperandType = "OPERAND_PCREL"; 323 let DecoderMethod = "DecodeBranchTarget"; 324 let ParserMatchClass = MipsJumpTargetAsmOperand; 325} 326def calltarget : Operand<iPTR> { 327 let EncoderMethod = "getJumpTargetOpValue"; 328 let ParserMatchClass = MipsJumpTargetAsmOperand; 329} 330 331def simm10 : Operand<i32>; 332 333def simm16 : Operand<i32> { 334 let DecoderMethod= "DecodeSimm16"; 335} 336 337def simm19_lsl2 : Operand<i32> { 338 let EncoderMethod = "getSimm19Lsl2Encoding"; 339 let DecoderMethod = "DecodeSimm19Lsl2"; 340} 341 342def simm20 : Operand<i32> { 343} 344 345def uimm20 : Operand<i32> { 346} 347 348def uimm10 : Operand<i32> { 349} 350 351def simm16_64 : Operand<i64> { 352 let DecoderMethod = "DecodeSimm16"; 353} 354 355// Zero 356def uimmz : Operand<i32> { 357 let PrintMethod = "printUnsignedImm"; 358} 359 360// Unsigned Operand 361def uimm2 : Operand<i32> { 362 let PrintMethod = "printUnsignedImm"; 363} 364 365def uimm3 : Operand<i32> { 366 let PrintMethod = "printUnsignedImm"; 367} 368 369def uimm5 : Operand<i32> { 370 let PrintMethod = "printUnsignedImm"; 371} 372 373def uimm6 : Operand<i32> { 374 let PrintMethod = "printUnsignedImm"; 375} 376 377def uimm16 : Operand<i32> { 378 let PrintMethod = "printUnsignedImm"; 379} 380 381def pcrel16 : Operand<i32> { 382} 383 384def MipsMemAsmOperand : AsmOperandClass { 385 let Name = "Mem"; 386 let ParserMethod = "parseMemOperand"; 387} 388 389def MipsInvertedImmoperand : AsmOperandClass { 390 let Name = "InvNum"; 391 let RenderMethod = "addImmOperands"; 392 let ParserMethod = "parseInvNum"; 393} 394 395def InvertedImOperand : Operand<i32> { 396 let ParserMatchClass = MipsInvertedImmoperand; 397} 398 399def InvertedImOperand64 : Operand<i64> { 400 let ParserMatchClass = MipsInvertedImmoperand; 401} 402 403class mem_generic : Operand<iPTR> { 404 let PrintMethod = "printMemOperand"; 405 let MIOperandInfo = (ops ptr_rc, simm16); 406 let EncoderMethod = "getMemEncoding"; 407 let ParserMatchClass = MipsMemAsmOperand; 408 let OperandType = "OPERAND_MEMORY"; 409} 410 411// Address operand 412def mem : mem_generic; 413 414// MSA specific address operand 415def mem_msa : mem_generic { 416 let MIOperandInfo = (ops ptr_rc, simm10); 417 let EncoderMethod = "getMSAMemEncoding"; 418} 419 420def mem_ea : Operand<iPTR> { 421 let PrintMethod = "printMemOperandEA"; 422 let MIOperandInfo = (ops ptr_rc, simm16); 423 let EncoderMethod = "getMemEncoding"; 424 let OperandType = "OPERAND_MEMORY"; 425} 426 427def PtrRC : Operand<iPTR> { 428 let MIOperandInfo = (ops ptr_rc); 429 let DecoderMethod = "DecodePtrRegisterClass"; 430 let ParserMatchClass = GPR32AsmOperand; 431} 432 433// size operand of ext instruction 434def size_ext : Operand<i32> { 435 let EncoderMethod = "getSizeExtEncoding"; 436 let DecoderMethod = "DecodeExtSize"; 437} 438 439// size operand of ins instruction 440def size_ins : Operand<i32> { 441 let EncoderMethod = "getSizeInsEncoding"; 442 let DecoderMethod = "DecodeInsSize"; 443} 444 445// Transformation Function - get the lower 16 bits. 446def LO16 : SDNodeXForm<imm, [{ 447 return getImm(N, N->getZExtValue() & 0xFFFF); 448}]>; 449 450// Transformation Function - get the higher 16 bits. 451def HI16 : SDNodeXForm<imm, [{ 452 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 453}]>; 454 455// Plus 1. 456def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 457 458// Node immediate is zero (e.g. insve.d) 459def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>; 460 461// Node immediate fits as 16-bit sign extended on target immediate. 462// e.g. addi, andi 463def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 464 465// Node immediate fits as 16-bit sign extended on target immediate. 466// e.g. addi, andi 467def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 468 469// Node immediate fits as 15-bit sign extended on target immediate. 470// e.g. addi, andi 471def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 472 473// Node immediate fits as 16-bit zero extended on target immediate. 474// The LO16 param means that only the lower 16 bits of the node 475// immediate are caught. 476// e.g. addiu, sltiu 477def immZExt16 : PatLeaf<(imm), [{ 478 if (N->getValueType(0) == MVT::i32) 479 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 480 else 481 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 482}], LO16>; 483 484// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 485def immLow16Zero : PatLeaf<(imm), [{ 486 int64_t Val = N->getSExtValue(); 487 return isInt<32>(Val) && !(Val & 0xffff); 488}]>; 489 490// shamt field must fit in 5 bits. 491def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 492 493// True if (N + 1) fits in 16-bit field. 494def immSExt16Plus1 : PatLeaf<(imm), [{ 495 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 496}]>; 497 498// Mips Address Mode! SDNode frameindex could possibily be a match 499// since load and store instructions from stack used it. 500def addr : 501 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 502 503def addrRegImm : 504 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 505 506def addrRegReg : 507 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 508 509def addrDefault : 510 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 511 512def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>; 513 514//===----------------------------------------------------------------------===// 515// Instructions specific format 516//===----------------------------------------------------------------------===// 517 518// Arithmetic and logical instructions with 3 register operands. 519class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 520 InstrItinClass Itin = NoItinerary, 521 SDPatternOperator OpNode = null_frag>: 522 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 523 !strconcat(opstr, "\t$rd, $rs, $rt"), 524 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 525 let isCommutable = isComm; 526 let isReMaterializable = 1; 527 let TwoOperandAliasConstraint = "$rd = $rs"; 528} 529 530// Arithmetic and logical instructions with 2 register operands. 531class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 532 InstrItinClass Itin = NoItinerary, 533 SDPatternOperator imm_type = null_frag, 534 SDPatternOperator OpNode = null_frag> : 535 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 536 !strconcat(opstr, "\t$rt, $rs, $imm16"), 537 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 538 Itin, FrmI, opstr> { 539 let isReMaterializable = 1; 540 let TwoOperandAliasConstraint = "$rs = $rt"; 541} 542 543// Arithmetic Multiply ADD/SUB 544class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> : 545 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 546 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> { 547 let Defs = [HI0, LO0]; 548 let Uses = [HI0, LO0]; 549 let isCommutable = isComm; 550} 551 552// Logical 553class LogicNOR<string opstr, RegisterOperand RO>: 554 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 555 !strconcat(opstr, "\t$rd, $rs, $rt"), 556 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> { 557 let isCommutable = 1; 558} 559 560// Shifts 561class shift_rotate_imm<string opstr, Operand ImmOpnd, 562 RegisterOperand RO, InstrItinClass itin, 563 SDPatternOperator OpNode = null_frag, 564 SDPatternOperator PF = null_frag> : 565 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 566 !strconcat(opstr, "\t$rd, $rt, $shamt"), 567 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> { 568 let TwoOperandAliasConstraint = "$rt = $rd"; 569} 570 571class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin, 572 SDPatternOperator OpNode = null_frag>: 573 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 574 !strconcat(opstr, "\t$rd, $rt, $rs"), 575 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR, 576 opstr>; 577 578// Load Upper Imediate 579class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 580 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 581 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove { 582 let neverHasSideEffects = 1; 583 let isReMaterializable = 1; 584} 585 586// Memory Load/Store 587class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 588 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 589 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 590 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 591 let DecoderMethod = "DecodeMem"; 592 let canFoldAsLoad = 1; 593 let mayLoad = 1; 594} 595 596class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 597 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 598 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 599 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 600 let DecoderMethod = "DecodeMem"; 601 let mayStore = 1; 602} 603 604// Load/Store Left/Right 605let canFoldAsLoad = 1 in 606class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 607 InstrItinClass Itin> : 608 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 609 !strconcat(opstr, "\t$rt, $addr"), 610 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 611 let DecoderMethod = "DecodeMem"; 612 string Constraints = "$src = $rt"; 613} 614 615class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 616 InstrItinClass Itin> : 617 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 618 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 619 let DecoderMethod = "DecodeMem"; 620} 621 622// Conditional Branch 623class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, 624 RegisterOperand RO> : 625 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 626 !strconcat(opstr, "\t$rs, $rt, $offset"), 627 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 628 FrmI, opstr> { 629 let isBranch = 1; 630 let isTerminator = 1; 631 let hasDelaySlot = 1; 632 let Defs = [AT]; 633} 634 635class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, 636 RegisterOperand RO> : 637 InstSE<(outs), (ins RO:$rs, opnd:$offset), 638 !strconcat(opstr, "\t$rs, $offset"), 639 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, 640 FrmI, opstr> { 641 let isBranch = 1; 642 let isTerminator = 1; 643 let hasDelaySlot = 1; 644 let Defs = [AT]; 645} 646 647// SetCC 648class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 649 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 650 !strconcat(opstr, "\t$rd, $rs, $rt"), 651 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 652 II_SLT_SLTU, FrmR, opstr>; 653 654class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 655 RegisterOperand RO>: 656 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 657 !strconcat(opstr, "\t$rt, $rs, $imm16"), 658 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 659 II_SLTI_SLTIU, FrmI, opstr>; 660 661// Jump 662class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 663 SDPatternOperator targetoperator, string bopstr> : 664 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 665 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> { 666 let isTerminator=1; 667 let isBarrier=1; 668 let hasDelaySlot = 1; 669 let DecoderMethod = "DecodeJumpTarget"; 670 let Defs = [AT]; 671} 672 673// Unconditional branch 674class UncondBranch<Instruction BEQInst> : 675 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, 676 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 677 let isBranch = 1; 678 let isTerminator = 1; 679 let isBarrier = 1; 680 let hasDelaySlot = 1; 681 let AdditionalPredicates = [RelocPIC]; 682 let Defs = [AT]; 683} 684 685// Base class for indirect branch and return instruction classes. 686let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 687class JumpFR<string opstr, RegisterOperand RO, 688 SDPatternOperator operator = null_frag>: 689 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, 690 FrmR, opstr>; 691 692// Indirect branch 693class IndirectBranch<string opstr, RegisterOperand RO> : 694 JumpFR<opstr, RO, brind> { 695 let isBranch = 1; 696 let isIndirectBranch = 1; 697} 698 699// Return instruction 700class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> { 701 let isReturn = 1; 702 let isCodeGenOnly = 1; 703 let hasCtrlDep = 1; 704 let hasExtraSrcRegAllocReq = 1; 705} 706 707// Jump and Link (Call) 708let isCall=1, hasDelaySlot=1, Defs = [RA] in { 709 class JumpLink<string opstr, DAGOperand opnd> : 710 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 711 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> { 712 let DecoderMethod = "DecodeJumpTarget"; 713 } 714 715 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 716 Register RetReg, RegisterOperand ResRO = RO>: 717 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 718 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 719 720 class JumpLinkReg<string opstr, RegisterOperand RO>: 721 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 722 [], IIBranch, FrmR>; 723 724 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> : 725 InstSE<(outs), (ins RO:$rs, opnd:$offset), 726 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; 727 728} 729 730let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 731 hasExtraSrcRegAllocReq = 1, Defs = [AT] in { 732 class TailCall<Instruction JumpInst> : 733 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>, 734 PseudoInstExpansion<(JumpInst jmptarget:$target)>; 735 736 class TailCallReg<RegisterOperand RO, Instruction JRInst, 737 RegisterOperand ResRO = RO> : 738 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>, 739 PseudoInstExpansion<(JRInst ResRO:$rs)>; 740} 741 742class BAL_BR_Pseudo<Instruction RealInst> : 743 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 744 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 745 let isBranch = 1; 746 let isTerminator = 1; 747 let isBarrier = 1; 748 let hasDelaySlot = 1; 749 let Defs = [RA]; 750} 751 752// Syscall 753class SYS_FT<string opstr> : 754 InstSE<(outs), (ins uimm20:$code_), 755 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>; 756// Break 757class BRK_FT<string opstr> : 758 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 759 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, 760 FrmOther, opstr>; 761 762// (D)Eret 763class ER_FT<string opstr> : 764 InstSE<(outs), (ins), 765 opstr, [], NoItinerary, FrmOther, opstr>; 766 767// Interrupts 768class DEI_FT<string opstr, RegisterOperand RO> : 769 InstSE<(outs RO:$rt), (ins), 770 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>; 771 772// Wait 773class WAIT_FT<string opstr> : 774 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>; 775 776// Sync 777let hasSideEffects = 1 in 778class SYNC_FT<string opstr> : 779 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 780 NoItinerary, FrmOther, opstr>; 781 782let hasSideEffects = 1 in 783class TEQ_FT<string opstr, RegisterOperand RO> : 784 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 785 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, 786 FrmI, opstr>; 787 788class TEQI_FT<string opstr, RegisterOperand RO> : 789 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 790 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>; 791// Mul, Div 792class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 793 list<Register> DefRegs> : 794 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 795 itin, FrmR, opstr> { 796 let isCommutable = 1; 797 let Defs = DefRegs; 798 let neverHasSideEffects = 1; 799} 800 801// Pseudo multiply/divide instruction with explicit accumulator register 802// operands. 803class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 804 SDPatternOperator OpNode, InstrItinClass Itin, 805 bit IsComm = 1, bit HasSideEffects = 0, 806 bit UsesCustomInserter = 0> : 807 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 808 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 809 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 810 let isCommutable = IsComm; 811 let hasSideEffects = HasSideEffects; 812 let usesCustomInserter = UsesCustomInserter; 813} 814 815// Pseudo multiply add/sub instruction with explicit accumulator register 816// operands. 817class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode, 818 InstrItinClass itin> 819 : PseudoSE<(outs ACC64:$ac), 820 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 821 [(set ACC64:$ac, 822 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 823 itin>, 824 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 825 string Constraints = "$acin = $ac"; 826} 827 828class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 829 list<Register> DefRegs> : 830 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 831 [], itin, FrmR, opstr> { 832 let Defs = DefRegs; 833} 834 835// Move from Hi/Lo 836class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 837 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 838 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>; 839 840class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 841 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, 842 FrmR, opstr> { 843 let Uses = [UseReg]; 844 let neverHasSideEffects = 1; 845} 846 847class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> 848 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), 849 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], 850 II_MTHI_MTLO>; 851 852class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 853 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO, 854 FrmR, opstr> { 855 let Defs = DefRegs; 856 let neverHasSideEffects = 1; 857} 858 859class EffectiveAddress<string opstr, RegisterOperand RO> : 860 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 861 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI, 862 !strconcat(opstr, "_lea")> { 863 let isCodeGenOnly = 1; 864 let DecoderMethod = "DecodeMem"; 865} 866 867// Count Leading Ones/Zeros in Word 868class CountLeading0<string opstr, RegisterOperand RO>: 869 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 870 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>; 871 872class CountLeading1<string opstr, RegisterOperand RO>: 873 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 874 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>; 875 876// Sign Extend in Register. 877class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO, 878 InstrItinClass itin> : 879 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 880 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>; 881 882// Subword Swap 883class SubwordSwap<string opstr, RegisterOperand RO>: 884 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 885 NoItinerary, FrmR, opstr> { 886 let neverHasSideEffects = 1; 887} 888 889// Read Hardware 890class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 891 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 892 II_RDHWR, FrmR>; 893 894// Ext and Ins 895class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 896 SDPatternOperator Op = null_frag>: 897 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size), 898 !strconcat(opstr, " $rt, $rs, $pos, $size"), 899 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary, 900 FrmR, opstr>, ISA_MIPS32R2; 901 902class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 903 SDPatternOperator Op = null_frag>: 904 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), 905 !strconcat(opstr, " $rt, $rs, $pos, $size"), 906 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], 907 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 { 908 let Constraints = "$src = $rt"; 909} 910 911// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 912class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 913 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 914 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 915 916// Atomic Compare & Swap. 917class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 918 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 919 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 920 921class LLBase<string opstr, RegisterOperand RO> : 922 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 923 [], NoItinerary, FrmI> { 924 let DecoderMethod = "DecodeMem"; 925 let mayLoad = 1; 926} 927 928class SCBase<string opstr, RegisterOperand RO> : 929 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 930 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 931 let DecoderMethod = "DecodeMem"; 932 let mayStore = 1; 933 let Constraints = "$rt = $dst"; 934} 935 936class MFC3OP<string asmstr, RegisterOperand RO> : 937 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 938 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 939 940class TrapBase<Instruction RealInst> 941 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>, 942 PseudoInstExpansion<(RealInst 0, 0)> { 943 let isBarrier = 1; 944 let isTerminator = 1; 945 let isCodeGenOnly = 1; 946} 947 948//===----------------------------------------------------------------------===// 949// Pseudo instructions 950//===----------------------------------------------------------------------===// 951 952// Return RA. 953let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 954def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 955 956let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 957def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 958 [(callseq_start timm:$amt)]>; 959def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 960 [(callseq_end timm:$amt1, timm:$amt2)]>; 961} 962 963let usesCustomInserter = 1 in { 964 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 965 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 966 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 967 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 968 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 969 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 970 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 971 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 972 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 973 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 974 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 975 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 976 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 977 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 978 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 979 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 980 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 981 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 982 983 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 984 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 985 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 986 987 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 988 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 989 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 990} 991 992/// Pseudo instructions for loading and storing accumulator registers. 993let isPseudo = 1, isCodeGenOnly = 1 in { 994 def LOAD_ACC64 : Load<"", ACC64>; 995 def STORE_ACC64 : Store<"", ACC64>; 996} 997 998// We need these two pseudo instructions to avoid offset calculation for long 999// branches. See the comment in file MipsLongBranch.cpp for detailed 1000// explanation. 1001 1002// Expands to: lui $dst, %hi($tgt - $baltgt) 1003def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst), 1004 (ins brtarget:$tgt, brtarget:$baltgt), []>; 1005 1006// Expands to: addiu $dst, $src, %lo($tgt - $baltgt) 1007def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), 1008 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>; 1009 1010//===----------------------------------------------------------------------===// 1011// Instruction definition 1012//===----------------------------------------------------------------------===// 1013//===----------------------------------------------------------------------===// 1014// MipsI Instructions 1015//===----------------------------------------------------------------------===// 1016 1017/// Arithmetic Instructions (ALU Immediate) 1018def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, 1019 add>, 1020 ADDI_FM<0x9>, IsAsCheapAsAMove; 1021def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>, 1022 ISA_MIPS1_NOT_32R6_64R6; 1023def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 1024 SLTI_FM<0xa>; 1025def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 1026 SLTI_FM<0xb>; 1027def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, 1028 and>, 1029 ADDI_FM<0xc>; 1030def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, 1031 or>, 1032 ADDI_FM<0xd>; 1033def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, 1034 xor>, 1035 ADDI_FM<0xe>; 1036def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 1037 1038/// Arithmetic Instructions (3-Operand, R-Type) 1039def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, 1040 ADD_FM<0, 0x21>; 1041def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, 1042 ADD_FM<0, 0x23>; 1043let Defs = [HI0, LO0] in 1044def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, 1045 ADD_FM<0x1c, 2>, ISA_MIPS32; 1046def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 1047def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 1048def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 1049def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 1050def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, 1051 ADD_FM<0, 0x24>; 1052def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, 1053 ADD_FM<0, 0x25>; 1054def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, 1055 ADD_FM<0, 0x26>; 1056def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 1057 1058/// Shift Instructions 1059def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, 1060 immZExt5>, SRA_FM<0, 0>; 1061def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, 1062 immZExt5>, SRA_FM<2, 0>; 1063def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, 1064 immZExt5>, SRA_FM<3, 0>; 1065def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, 1066 SRLV_FM<4, 0>; 1067def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, 1068 SRLV_FM<6, 0>; 1069def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, 1070 SRLV_FM<7, 0>; 1071 1072// Rotate Instructions 1073def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, 1074 immZExt5>, 1075 SRA_FM<2, 1>, ISA_MIPS32R2; 1076def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, 1077 SRLV_FM<6, 1>, ISA_MIPS32R2; 1078 1079/// Load and Store Instructions 1080/// aligned 1081def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; 1082def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, 1083 LW_FM<0x24>; 1084def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, 1085 LW_FM<0x21>; 1086def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; 1087def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, 1088 LW_FM<0x23>; 1089def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>; 1090def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; 1091def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; 1092 1093/// load/store left/right 1094let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1095 AdditionalPredicates = [NotInMicroMips] in { 1096def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>, 1097 ISA_MIPS1_NOT_32R6_64R6; 1098def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>, 1099 ISA_MIPS1_NOT_32R6_64R6; 1100def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>, 1101 ISA_MIPS1_NOT_32R6_64R6; 1102def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>, 1103 ISA_MIPS1_NOT_32R6_64R6; 1104} 1105 1106def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM; 1107def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 1108def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; 1109def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; 1110def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; 1111def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; 1112def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; 1113 1114def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, 1115 ISA_MIPS2_NOT_32R6_64R6; 1116def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, 1117 ISA_MIPS2_NOT_32R6_64R6; 1118def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, 1119 ISA_MIPS2_NOT_32R6_64R6; 1120def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, 1121 ISA_MIPS2_NOT_32R6_64R6; 1122def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, 1123 ISA_MIPS2_NOT_32R6_64R6; 1124def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, 1125 ISA_MIPS2_NOT_32R6_64R6; 1126 1127def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>; 1128def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; 1129def TRAP : TrapBase<BREAK>; 1130 1131def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32; 1132def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32; 1133 1134def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; 1135def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; 1136 1137let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1138 AdditionalPredicates = [NotInMicroMips] in { 1139def WAIT : WAIT_FT<"wait">, WAIT_FM; 1140 1141/// Load-linked, Store-conditional 1142def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2; 1143def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2; 1144} 1145 1146/// Jump and Branch Instructions 1147def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>, 1148 AdditionalRequires<[RelocStatic]>, IsBranch; 1149def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>; 1150def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; 1151def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; 1152def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, 1153 BGEZ_FM<1, 1>; 1154def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, 1155 BGEZ_FM<7, 0>; 1156def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, 1157 BGEZ_FM<6, 0>; 1158def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, 1159 BGEZ_FM<1, 0>; 1160def B : UncondBranch<BEQ>; 1161 1162def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; 1163let AdditionalPredicates = [NotInMicroMips] in { 1164def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 1165def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 1166} 1167def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>; 1168def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>; 1169def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>; 1170def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 1171def TAILCALL : TailCall<J>; 1172def TAILCALL_R : TailCallReg<GPR32Opnd, JR>; 1173 1174def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>; 1175 1176// Exception handling related node and instructions. 1177// The conversion sequence is: 1178// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1179// MIPSeh_return -> (stack change + indirect branch) 1180// 1181// MIPSeh_return takes the place of regular return instruction 1182// but takes two arguments (V1, V0) which are used for storing 1183// the offset and return address respectively. 1184def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1185 1186def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1188 1189let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1190 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1191 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1192 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1193 GPR64:$dst), 1194 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1195} 1196 1197/// Multiply and Divide Instructions. 1198def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, 1199 MULT_FM<0, 0x18>; 1200def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, 1201 MULT_FM<0, 0x19>; 1202def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, 1203 MULT_FM<0, 0x1a>; 1204def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, 1205 MULT_FM<0, 0x1b>; 1206 1207def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; 1208def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; 1209let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1210 AdditionalPredicates = [NotInMicroMips] in { 1211def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>; 1212def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>; 1213} 1214 1215/// Sign Ext In Register Instructions. 1216def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, 1217 SEB_FM<0x10, 0x20>, ISA_MIPS32R2; 1218def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, 1219 SEB_FM<0x18, 0x20>, ISA_MIPS32R2; 1220 1221/// Count Leading 1222def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32; 1223def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32; 1224 1225/// Word Swap Bytes Within Halfwords 1226def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2; 1227 1228/// No operation. 1229def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1230 1231// FrameIndexes are legalized when they are operands from load/store 1232// instructions. The same not happens for stack address copies, so an 1233// add op with mem ComplexPattern is used and the stack address copy 1234// can be matched. It's similar to Sparc LEA_ADDRi 1235def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1236 1237// MADD*/MSUB* 1238def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, ISA_MIPS32; 1239def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, ISA_MIPS32; 1240def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, ISA_MIPS32; 1241def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, ISA_MIPS32; 1242 1243let AdditionalPredicates = [NotDSP] in { 1244def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>; 1245def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>; 1246def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>; 1247def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>; 1248def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>; 1249def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>; 1250def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>; 1251def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>; 1252def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>; 1253} 1254 1255def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV, 1256 0, 1, 1>; 1257def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, 1258 0, 1, 1>; 1259 1260def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1261 1262def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; 1263def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; 1264 1265/// Move Control Registers From/To CPU Registers 1266def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32; 1267def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32; 1268def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1269def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1270 1271class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1272 FrmOther>; 1273def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>; 1274def EHB : Barrier<"ehb">, BARRIER_FM<3>; 1275def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2; 1276 1277class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1278 FrmOther>; 1279def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>; 1280def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>; 1281def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>; 1282def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>; 1283 1284//===----------------------------------------------------------------------===// 1285// Instruction aliases 1286//===----------------------------------------------------------------------===// 1287def : MipsInstAlias<"move $dst, $src", 1288 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1289 GPR_32 { 1290 let AdditionalPredicates = [NotInMicroMips]; 1291} 1292def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; 1293def : MipsInstAlias<"addu $rs, $rt, $imm", 1294 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1295def : MipsInstAlias<"add $rs, $rt, $imm", 1296 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1297def : MipsInstAlias<"and $rs, $rt, $imm", 1298 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1299def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1300let Predicates = [NotInMicroMips] in { 1301def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1302} 1303def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1304def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1305def : MipsInstAlias<"not $rt, $rs", 1306 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1307def : MipsInstAlias<"neg $rt, $rs", 1308 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1309def : MipsInstAlias<"negu $rt", 1310 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; 1311def : MipsInstAlias<"negu $rt, $rs", 1312 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1313def : MipsInstAlias<"slt $rs, $rt, $imm", 1314 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1315def : MipsInstAlias<"sltu $rt, $rs, $imm", 1316 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>; 1317def : MipsInstAlias<"xor $rs, $rt, $imm", 1318 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1319def : MipsInstAlias<"or $rs, $rt, $imm", 1320 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1321def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1322def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1323def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1324def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1325def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1326def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1327def : MipsInstAlias<"bnez $rs,$offset", 1328 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1329def : MipsInstAlias<"beqz $rs,$offset", 1330 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1331def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; 1332 1333def : MipsInstAlias<"break", (BREAK 0, 0), 1>; 1334def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1335def : MipsInstAlias<"ei", (EI ZERO), 1>; 1336def : MipsInstAlias<"di", (DI ZERO), 1>; 1337 1338def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1339def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1340def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1341 1>; 1342def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1343def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1344 1>; 1345def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1346def : MipsInstAlias<"sll $rd, $rt, $rs", 1347 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1348def : MipsInstAlias<"sub, $rd, $rs, $imm", 1349 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, 1350 InvertedImOperand:$imm), 0>; 1351def : MipsInstAlias<"sub $rs, $imm", 1352 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), 1353 0>; 1354def : MipsInstAlias<"subu, $rd, $rs, $imm", 1355 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, 1356 InvertedImOperand:$imm), 0>; 1357def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, 1358 InvertedImOperand:$imm), 0>; 1359def : MipsInstAlias<"sra $rd, $rt, $rs", 1360 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1361def : MipsInstAlias<"srl $rd, $rt, $rs", 1362 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1363//===----------------------------------------------------------------------===// 1364// Assembler Pseudo Instructions 1365//===----------------------------------------------------------------------===// 1366 1367class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1368 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1369 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1370def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>; 1371 1372class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1373 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1374 !strconcat(instr_asm, "\t$rt, $addr")> ; 1375def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1376 1377class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1378 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1379 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1380def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; 1381 1382//===----------------------------------------------------------------------===// 1383// Arbitrary patterns that map to one or more instructions 1384//===----------------------------------------------------------------------===// 1385 1386// Load/store pattern templates. 1387class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1388 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1389 1390class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1391 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1392 1393// Small immediates 1394def : MipsPat<(i32 immSExt16:$in), 1395 (ADDiu ZERO, imm:$in)>; 1396def : MipsPat<(i32 immZExt16:$in), 1397 (ORi ZERO, imm:$in)>; 1398def : MipsPat<(i32 immLow16Zero:$in), 1399 (LUi (HI16 imm:$in))>; 1400 1401// Arbitrary immediates 1402def : MipsPat<(i32 imm:$imm), 1403 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1404 1405// Carry MipsPatterns 1406def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1407 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1408let AdditionalPredicates = [NotDSP] in { 1409 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1410 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1411 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1412 (ADDiu GPR32:$src, imm:$imm)>; 1413} 1414 1415// Call 1416def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1417 (JAL tglobaladdr:$dst)>; 1418def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1419 (JAL texternalsym:$dst)>; 1420//def : MipsPat<(MipsJmpLink GPR32:$dst), 1421// (JALR GPR32:$dst)>; 1422 1423// Tail call 1424def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1425 (TAILCALL tglobaladdr:$dst)>; 1426def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1427 (TAILCALL texternalsym:$dst)>; 1428// hi/lo relocs 1429def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1430def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1431def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1432def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1433def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1434def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1435 1436def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1437def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1438def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1439def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1440def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1441def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1442 1443def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1444 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1445def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1446 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1447def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1448 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1449def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1450 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1451def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1452 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1453 1454// gp_rel relocs 1455def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1456 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1457def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1458 (ADDiu GPR32:$gp, tconstpool:$in)>; 1459 1460// wrapper_pic 1461class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1462 MipsPat<(MipsWrapper RC:$gp, node:$in), 1463 (ADDiuOp RC:$gp, node:$in)>; 1464 1465def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1466def : WrapperPat<tconstpool, ADDiu, GPR32>; 1467def : WrapperPat<texternalsym, ADDiu, GPR32>; 1468def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1469def : WrapperPat<tjumptable, ADDiu, GPR32>; 1470def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1471 1472// Mips does not have "not", so we expand our way 1473def : MipsPat<(not GPR32:$in), 1474 (NOR GPR32Opnd:$in, ZERO)>; 1475 1476// extended loads 1477def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1478def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1479def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1480 1481// peepholes 1482def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1483 1484// brcond patterns 1485multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1486 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1487 Instruction SLTiuOp, Register ZEROReg> { 1488def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1489 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1490def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1491 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1492 1493def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1494 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1495def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1496 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1497def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1498 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1499def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1500 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1501def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1502 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1503def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1504 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1505 1506def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1507 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1508def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1509 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1510 1511def : MipsPat<(brcond RC:$cond, bb:$dst), 1512 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1513} 1514 1515defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1516 1517def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1518 (BLEZ i32:$lhs, bb:$dst)>; 1519def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1520 (BGEZ i32:$lhs, bb:$dst)>; 1521 1522// setcc patterns 1523multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1524 Instruction SLTuOp, Register ZEROReg> { 1525 def : MipsPat<(seteq RC:$lhs, 0), 1526 (SLTiuOp RC:$lhs, 1)>; 1527 def : MipsPat<(setne RC:$lhs, 0), 1528 (SLTuOp ZEROReg, RC:$lhs)>; 1529 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1530 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1531 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1532 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1533} 1534 1535multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1536 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1537 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1538 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1539 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1540} 1541 1542multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1543 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1544 (SLTOp RC:$rhs, RC:$lhs)>; 1545 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1546 (SLTuOp RC:$rhs, RC:$lhs)>; 1547} 1548 1549multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1550 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1551 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1552 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1553 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1554} 1555 1556multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1557 Instruction SLTiuOp> { 1558 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1559 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1560 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1561 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1562} 1563 1564defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1565defm : SetlePats<GPR32, SLT, SLTu>; 1566defm : SetgtPats<GPR32, SLT, SLTu>; 1567defm : SetgePats<GPR32, SLT, SLTu>; 1568defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1569 1570// bswap pattern 1571def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1572 1573// Load halfword/word patterns. 1574let AddedComplexity = 40 in { 1575 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1576 def : LoadRegImmPat<LH, i32, sextloadi16>; 1577 def : LoadRegImmPat<LW, i32, load>; 1578} 1579 1580//===----------------------------------------------------------------------===// 1581// Floating Point Support 1582//===----------------------------------------------------------------------===// 1583 1584include "MipsInstrFPU.td" 1585include "Mips64InstrInfo.td" 1586include "MipsCondMov.td" 1587 1588include "Mips32r6InstrInfo.td" 1589include "Mips64r6InstrInfo.td" 1590 1591// 1592// Mips16 1593 1594include "Mips16InstrFormats.td" 1595include "Mips16InstrInfo.td" 1596 1597// DSP 1598include "MipsDSPInstrFormats.td" 1599include "MipsDSPInstrInfo.td" 1600 1601// MSA 1602include "MipsMSAInstrFormats.td" 1603include "MipsMSAInstrInfo.td" 1604 1605// Micromips 1606include "MicroMipsInstrFormats.td" 1607include "MicroMipsInstrInfo.td" 1608include "MicroMipsInstrFPU.td" 1609