MipsInstrInfo.td revision e72fac60e3dbcf14ec68cedc1e86feafec1652eb
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 15-bit sign extended on target immediate. 302// e.g. addi, andi 303def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 304 305// Node immediate fits as 16-bit zero extended on target immediate. 306// The LO16 param means that only the lower 16 bits of the node 307// immediate are caught. 308// e.g. addiu, sltiu 309def immZExt16 : PatLeaf<(imm), [{ 310 if (N->getValueType(0) == MVT::i32) 311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 312 else 313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 314}], LO16>; 315 316// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 317def immLow16Zero : PatLeaf<(imm), [{ 318 int64_t Val = N->getSExtValue(); 319 return isInt<32>(Val) && !(Val & 0xffff); 320}]>; 321 322// shamt field must fit in 5 bits. 323def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 324 325// Mips Address Mode! SDNode frameindex could possibily be a match 326// since load and store instructions from stack used it. 327def addr : 328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 329 330//===----------------------------------------------------------------------===// 331// Instructions specific format 332//===----------------------------------------------------------------------===// 333 334// Arithmetic and logical instructions with 3 register operands. 335class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 336 InstrItinClass Itin = NoItinerary, 337 SDPatternOperator OpNode = null_frag>: 338 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 339 !strconcat(opstr, "\t$rd, $rs, $rt"), 340 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { 341 let isCommutable = isComm; 342 let isReMaterializable = 1; 343 string BaseOpcode; 344 string Arch; 345} 346 347// Arithmetic and logical instructions with 2 register operands. 348class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 349 SDPatternOperator imm_type = null_frag, 350 SDPatternOperator OpNode = null_frag> : 351 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 352 !strconcat(opstr, "\t$rt, $rs, $imm16"), 353 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> { 354 let isReMaterializable = 1; 355} 356 357// Arithmetic Multiply ADD/SUB 358class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> : 359 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 360 !strconcat(opstr, "\t$rs, $rt"), 361 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> { 362 let Defs = [HI, LO]; 363 let Uses = [HI, LO]; 364 let isCommutable = isComm; 365} 366 367// Logical 368class LogicNOR<string opstr, RegisterOperand RC>: 369 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 370 !strconcat(opstr, "\t$rd, $rs, $rt"), 371 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 372 let isCommutable = 1; 373} 374 375// Shifts 376class shift_rotate_imm<string opstr, Operand ImmOpnd, 377 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 378 SDPatternOperator PF = null_frag> : 379 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 380 !strconcat(opstr, "\t$rd, $rt, $shamt"), 381 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 382 383class shift_rotate_reg<string opstr, RegisterOperand RC, 384 SDPatternOperator OpNode = null_frag>: 385 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 386 !strconcat(opstr, "\t$rd, $rt, $rs"), 387 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>; 388 389// Load Upper Imediate 390class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 391 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 392 [], IIAlu, FrmI>, IsAsCheapAsAMove { 393 let neverHasSideEffects = 1; 394 let isReMaterializable = 1; 395} 396 397class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 398 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 399 bits<21> addr; 400 let Inst{25-21} = addr{20-16}; 401 let Inst{15-0} = addr{15-0}; 402 let DecoderMethod = "DecodeMem"; 403} 404 405// Memory Load/Store 406class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 407 Operand MemOpnd> : 408 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 409 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 410 let DecoderMethod = "DecodeMem"; 411 let canFoldAsLoad = 1; 412} 413 414class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 415 Operand MemOpnd> : 416 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 417 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 418 let DecoderMethod = "DecodeMem"; 419} 420 421multiclass LoadM<string opstr, RegisterClass RC, 422 SDPatternOperator OpNode = null_frag> { 423 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 424 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 425 let DecoderNamespace = "Mips64"; 426 let isCodeGenOnly = 1; 427 } 428} 429 430multiclass StoreM<string opstr, RegisterClass RC, 431 SDPatternOperator OpNode = null_frag> { 432 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 433 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 434 let DecoderNamespace = "Mips64"; 435 let isCodeGenOnly = 1; 436 } 437} 438 439// Load/Store Left/Right 440let canFoldAsLoad = 1 in 441class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 442 Operand MemOpnd> : 443 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 444 !strconcat(opstr, "\t$rt, $addr"), 445 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 446 let DecoderMethod = "DecodeMem"; 447 string Constraints = "$src = $rt"; 448} 449 450class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 451 Operand MemOpnd>: 452 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 453 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 454 let DecoderMethod = "DecodeMem"; 455} 456 457multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 458 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 459 Requires<[NotN64, HasStdEnc]>; 460 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 461 Requires<[IsN64, HasStdEnc]> { 462 let DecoderNamespace = "Mips64"; 463 let isCodeGenOnly = 1; 464 } 465} 466 467multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 468 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 469 Requires<[NotN64, HasStdEnc]>; 470 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 471 Requires<[IsN64, HasStdEnc]> { 472 let DecoderNamespace = "Mips64"; 473 let isCodeGenOnly = 1; 474 } 475} 476 477// Conditional Branch 478class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 479 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 480 !strconcat(opstr, "\t$rs, $rt, $offset"), 481 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 482 FrmI> { 483 let isBranch = 1; 484 let isTerminator = 1; 485 let hasDelaySlot = 1; 486 let Defs = [AT]; 487} 488 489class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 490 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 491 !strconcat(opstr, "\t$rs, $offset"), 492 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 493 let isBranch = 1; 494 let isTerminator = 1; 495 let hasDelaySlot = 1; 496 let Defs = [AT]; 497} 498 499// SetCC 500class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 501 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 502 !strconcat(opstr, "\t$rd, $rs, $rt"), 503 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 504 505class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 506 RegisterClass RC>: 507 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 508 !strconcat(opstr, "\t$rt, $rs, $imm16"), 509 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 510 IIAlu, FrmI>; 511 512// Jump 513class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 514 SDPatternOperator targetoperator> : 515 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 516 [(operator targetoperator:$target)], IIBranch, FrmJ> { 517 let isTerminator=1; 518 let isBarrier=1; 519 let hasDelaySlot = 1; 520 let DecoderMethod = "DecodeJumpTarget"; 521 let Defs = [AT]; 522} 523 524// Unconditional branch 525class UncondBranch<string opstr> : 526 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 527 [(br bb:$offset)], IIBranch, FrmI> { 528 let isBranch = 1; 529 let isTerminator = 1; 530 let isBarrier = 1; 531 let hasDelaySlot = 1; 532 let Predicates = [RelocPIC, HasStdEnc]; 533 let Defs = [AT]; 534} 535 536// Base class for indirect branch and return instruction classes. 537let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 538class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 539 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 540 541// Indirect branch 542class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 543 let isBranch = 1; 544 let isIndirectBranch = 1; 545} 546 547// Return instruction 548class RetBase<RegisterClass RC>: JumpFR<RC> { 549 let isReturn = 1; 550 let isCodeGenOnly = 1; 551 let hasCtrlDep = 1; 552 let hasExtraSrcRegAllocReq = 1; 553} 554 555// Jump and Link (Call) 556let isCall=1, hasDelaySlot=1, Defs = [RA] in { 557 class JumpLink<string opstr> : 558 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 559 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 560 let DecoderMethod = "DecodeJumpTarget"; 561 } 562 563 class JumpLinkReg<string opstr, RegisterClass RC>: 564 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), 565 [(MipsJmpLink RC:$rs)], IIBranch, FrmR>; 566 567 class BGEZAL_FT<string opstr, RegisterOperand RO> : 568 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 569 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 570 571} 572 573class BAL_FT : 574 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 575 let isBranch = 1; 576 let isTerminator = 1; 577 let isBarrier = 1; 578 let hasDelaySlot = 1; 579 let Defs = [RA]; 580} 581 582// Sync 583let hasSideEffects = 1 in 584class SYNC_FT : 585 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 586 NoItinerary, FrmOther>; 587 588// Mul, Div 589class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 590 list<Register> DefRegs> : 591 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 592 itin, FrmR> { 593 let isCommutable = 1; 594 let Defs = DefRegs; 595 let neverHasSideEffects = 1; 596} 597 598class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO, 599 list<Register> DefRegs> : 600 InstSE<(outs), (ins RO:$rs, RO:$rt), 601 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin, 602 FrmR> { 603 let Defs = DefRegs; 604} 605 606// Move from Hi/Lo 607class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 608 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 609 let Uses = UseRegs; 610 let neverHasSideEffects = 1; 611} 612 613class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 614 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 615 let Defs = DefRegs; 616 let neverHasSideEffects = 1; 617} 618 619class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 620 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 621 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 622 let isCodeGenOnly = 1; 623 let DecoderMethod = "DecodeMem"; 624} 625 626// Count Leading Ones/Zeros in Word 627class CountLeading0<string opstr, RegisterOperand RO>: 628 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 629 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 630 Requires<[HasBitCount, HasStdEnc]>; 631 632class CountLeading1<string opstr, RegisterOperand RO>: 633 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 634 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 635 Requires<[HasBitCount, HasStdEnc]>; 636 637 638// Sign Extend in Register. 639class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 640 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 641 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 642 let Predicates = [HasSEInReg, HasStdEnc]; 643} 644 645// Subword Swap 646class SubwordSwap<string opstr, RegisterOperand RO>: 647 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 648 NoItinerary, FrmR> { 649 let Predicates = [HasSwap, HasStdEnc]; 650 let neverHasSideEffects = 1; 651} 652 653// Read Hardware 654class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 655 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 656 IIAlu, FrmR>; 657 658// Ext and Ins 659class ExtBase<string opstr, RegisterOperand RO>: 660 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 661 !strconcat(opstr, " $rt, $rs, $pos, $size"), 662 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 663 FrmR> { 664 let Predicates = [HasMips32r2, HasStdEnc]; 665} 666 667class InsBase<string opstr, RegisterOperand RO>: 668 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 669 !strconcat(opstr, " $rt, $rs, $pos, $size"), 670 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 671 NoItinerary, FrmR> { 672 let Predicates = [HasMips32r2, HasStdEnc]; 673 let Constraints = "$src = $rt"; 674} 675 676// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 677class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 678 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 679 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 680 681multiclass Atomic2Ops32<PatFrag Op> { 682 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 683 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 684 Requires<[IsN64, HasStdEnc]> { 685 let DecoderNamespace = "Mips64"; 686 } 687} 688 689// Atomic Compare & Swap. 690class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 691 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 692 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 693 694multiclass AtomicCmpSwap32<PatFrag Op> { 695 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 696 Requires<[NotN64, HasStdEnc]>; 697 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 698 Requires<[IsN64, HasStdEnc]> { 699 let DecoderNamespace = "Mips64"; 700 } 701} 702 703class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 704 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 705 [], NoItinerary, FrmI> { 706 let DecoderMethod = "DecodeMem"; 707 let mayLoad = 1; 708} 709 710class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 711 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 712 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 713 let DecoderMethod = "DecodeMem"; 714 let mayStore = 1; 715 let Constraints = "$rt = $dst"; 716} 717 718class MFC3OP<dag outs, dag ins, string asmstr> : 719 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 720 721//===----------------------------------------------------------------------===// 722// Pseudo instructions 723//===----------------------------------------------------------------------===// 724 725// Return RA. 726let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 727def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 728 729let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 730def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 731 [(callseq_start timm:$amt)]>; 732def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 733 [(callseq_end timm:$amt1, timm:$amt2)]>; 734} 735 736let usesCustomInserter = 1 in { 737 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 738 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 739 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 740 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 741 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 742 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 743 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 744 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 745 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 746 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 747 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 748 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 749 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 750 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 751 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 752 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 753 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 754 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 755 756 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 757 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 758 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 759 760 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 761 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 762 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 763} 764 765//===----------------------------------------------------------------------===// 766// Instruction definition 767//===----------------------------------------------------------------------===// 768//===----------------------------------------------------------------------===// 769// MipsI Instructions 770//===----------------------------------------------------------------------===// 771 772/// Arithmetic Instructions (ALU Immediate) 773def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 774 ADDI_FM<0x9>, IsAsCheapAsAMove; 775def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 776def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 777def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 778def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 779 ADDI_FM<0xc>; 780def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 781 ADDI_FM<0xd>; 782def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 783 ADDI_FM<0xe>; 784def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 785 786/// Arithmetic Instructions (3-Operand, R-Type) 787def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>; 788def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 789def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 790def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 791def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 792def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 793def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 794def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 795def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 796def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 797def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 798 799/// Shift Instructions 800def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 801 SRA_FM<0, 0>; 802def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 803 SRA_FM<2, 0>; 804def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 805 SRA_FM<3, 0>; 806def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 807def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 808def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 809 810// Rotate Instructions 811let Predicates = [HasMips32r2, HasStdEnc] in { 812 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>, 813 SRA_FM<2, 1>; 814 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>; 815} 816 817/// Load and Store Instructions 818/// aligned 819defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 820defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; 821defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; 822defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 823defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; 824defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 825defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 826defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 827 828/// load/store left/right 829defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 830defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 831defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 832defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 833 834def SYNC : SYNC_FT, SYNC_FM; 835 836/// Load-linked, Store-conditional 837let Predicates = [NotN64, HasStdEnc] in { 838 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 839 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 840} 841 842let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 843 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 844 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 845} 846 847/// Jump and Branch Instructions 848def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 849 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 850def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 851def B : UncondBranch<"b">, B_FM; 852def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 853def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 854def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 855def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 856def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 857def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 858 859def BAL_BR: BAL_FT, BAL_FM; 860 861def JAL : JumpLink<"jal">, FJ<3>; 862def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 863def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 864def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 865def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 866def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 867 868def RET : RetBase<CPURegs>, MTLO_FM<8>; 869 870/// Multiply and Divide Instructions. 871def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>; 872def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>; 873def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>, 874 MULT_FM<0, 0x1a>; 875def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>, 876 MULT_FM<0, 0x1b>; 877 878def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 879def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 880def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 881def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 882 883/// Sign Ext In Register Instructions. 884def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 885def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 886 887/// Count Leading 888def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 889def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 890 891/// Word Swap Bytes Within Halfwords 892def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 893 894/// No operation. 895/// FIXME: NOP should be an alias of "sll $0, $0, 0". 896def NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM; 897 898// FrameIndexes are legalized when they are operands from load/store 899// instructions. The same not happens for stack address copies, so an 900// add op with mem ComplexPattern is used and the stack address copy 901// can be matched. It's similar to Sparc LEA_ADDRi 902def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 903 904// MADD*/MSUB* 905def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; 906def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; 907def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; 908def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; 909 910def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 911 912def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 913def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 914 915/// Move Control Registers From/To CPU Registers 916def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 917 (ins CPURegsOpnd:$rd, uimm16:$sel), 918 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 919 920def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 921 (ins CPURegsOpnd:$rt), 922 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 923 924def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 925 (ins CPURegsOpnd:$rd, uimm16:$sel), 926 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 927 928def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 929 (ins CPURegsOpnd:$rt), 930 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 931 932//===----------------------------------------------------------------------===// 933// Instruction aliases 934//===----------------------------------------------------------------------===// 935def : InstAlias<"move $dst,$src", (ADDu CPURegsOpnd:$dst, 936 CPURegsOpnd:$src,ZERO)>, Requires<[NotMips64]>; 937def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset)>; 938def : InstAlias<"addu $rs, $rt, $imm", 939 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; 940def : InstAlias<"add $rs, $rt, $imm", 941 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; 942def : InstAlias<"and $rs, $rt, $imm", 943 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; 944def : InstAlias<"j $rs", (JR CPURegs:$rs)>, Requires<[NotMips64]>; 945def : InstAlias<"not $rt, $rs", (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO)>; 946def : InstAlias<"neg $rt, $rs", (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs)>; 947def : InstAlias<"negu $rt, $rs", (SUBu CPURegsOpnd:$rt, ZERO, 948 CPURegsOpnd:$rs)>; 949def : InstAlias<"slt $rs, $rt, $imm", 950 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm)>; 951def : InstAlias<"xor $rs, $rt, $imm", 952 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>, 953 Requires<[NotMips64]>; 954def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0)>; 955def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt)>; 956def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0)>; 957def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt)>; 958 959//===----------------------------------------------------------------------===// 960// Assembler Pseudo Instructions 961//===----------------------------------------------------------------------===// 962 963class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 964 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 965 !strconcat(instr_asm, "\t$rt, $imm32")> ; 966def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 967 968class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 969 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 970 !strconcat(instr_asm, "\t$rt, $addr")> ; 971def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 972 973class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 974 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 975 !strconcat(instr_asm, "\t$rt, $imm32")> ; 976def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 977 978 979 980//===----------------------------------------------------------------------===// 981// Arbitrary patterns that map to one or more instructions 982//===----------------------------------------------------------------------===// 983 984// Small immediates 985def : MipsPat<(i32 immSExt16:$in), 986 (ADDiu ZERO, imm:$in)>; 987def : MipsPat<(i32 immZExt16:$in), 988 (ORi ZERO, imm:$in)>; 989def : MipsPat<(i32 immLow16Zero:$in), 990 (LUi (HI16 imm:$in))>; 991 992// Arbitrary immediates 993def : MipsPat<(i32 imm:$imm), 994 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 995 996// Carry MipsPatterns 997def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 998 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 999def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1000 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1001def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1002 (ADDiu CPURegs:$src, imm:$imm)>; 1003 1004// Call 1005def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1006 (JAL tglobaladdr:$dst)>; 1007def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1008 (JAL texternalsym:$dst)>; 1009//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1010// (JALR CPURegs:$dst)>; 1011 1012// Tail call 1013def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1014 (TAILCALL tglobaladdr:$dst)>; 1015def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1016 (TAILCALL texternalsym:$dst)>; 1017// hi/lo relocs 1018def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1019def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1020def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1021def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1022def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1023def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1024 1025def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1026def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1027def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1028def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1029def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1030def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1031 1032def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1033 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1034def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1035 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1036def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1037 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1038def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1039 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1040def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1041 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1042 1043// gp_rel relocs 1044def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1045 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1046def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1047 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1048 1049// wrapper_pic 1050class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1051 MipsPat<(MipsWrapper RC:$gp, node:$in), 1052 (ADDiuOp RC:$gp, node:$in)>; 1053 1054def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1055def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1056def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1057def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1058def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1059def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1060 1061// Mips does not have "not", so we expand our way 1062def : MipsPat<(not CPURegs:$in), 1063 (NOR CPURegsOpnd:$in, ZERO)>; 1064 1065// extended loads 1066let Predicates = [NotN64, HasStdEnc] in { 1067 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1068 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1069 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1070} 1071let Predicates = [IsN64, HasStdEnc] in { 1072 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1073 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1074 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1075} 1076 1077// peepholes 1078let Predicates = [NotN64, HasStdEnc] in { 1079 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1080} 1081let Predicates = [IsN64, HasStdEnc] in { 1082 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1083} 1084 1085// brcond patterns 1086multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1087 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1088 Instruction SLTiuOp, Register ZEROReg> { 1089def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1090 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1091def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1092 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1093 1094def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1095 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1096def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1097 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1098def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1099 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1100def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1101 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1102 1103def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1104 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1105def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1106 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1107 1108def : MipsPat<(brcond RC:$cond, bb:$dst), 1109 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1110} 1111 1112defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1113 1114// setcc patterns 1115multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1116 Instruction SLTuOp, Register ZEROReg> { 1117 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1118 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1119 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1120 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1121} 1122 1123multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1124 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1125 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1126 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1127 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1128} 1129 1130multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1131 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1132 (SLTOp RC:$rhs, RC:$lhs)>; 1133 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1134 (SLTuOp RC:$rhs, RC:$lhs)>; 1135} 1136 1137multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1138 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1139 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1140 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1141 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1142} 1143 1144multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1145 Instruction SLTiuOp> { 1146 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1147 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1148 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1149 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1150} 1151 1152defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1153defm : SetlePats<CPURegs, SLT, SLTu>; 1154defm : SetgtPats<CPURegs, SLT, SLTu>; 1155defm : SetgePats<CPURegs, SLT, SLTu>; 1156defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1157 1158// bswap pattern 1159def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1160 1161//===----------------------------------------------------------------------===// 1162// Floating Point Support 1163//===----------------------------------------------------------------------===// 1164 1165include "MipsInstrFPU.td" 1166include "Mips64InstrInfo.td" 1167include "MipsCondMov.td" 1168 1169// 1170// Mips16 1171 1172include "Mips16InstrFormats.td" 1173include "Mips16InstrInfo.td" 1174 1175// DSP 1176include "MipsDSPInstrFormats.td" 1177include "MipsDSPInstrInfo.td" 1178 1179