MipsInstrInfo.td revision f3c0c77bc34706cc3c2bbc5e4aaae984f52d01a7
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsBranch { 177 bit isBranch = 1; 178} 179 180class IsReturn { 181 bit isReturn = 1; 182} 183 184class IsCall { 185 bit isCall = 1; 186} 187 188class IsTailCall { 189 bit isCall = 1; 190 bit isTerminator = 1; 191 bit isReturn = 1; 192 bit isBarrier = 1; 193 bit hasExtraSrcRegAllocReq = 1; 194 bit isCodeGenOnly = 1; 195} 196 197class IsAsCheapAsAMove { 198 bit isAsCheapAsAMove = 1; 199} 200 201class NeverHasSideEffects { 202 bit neverHasSideEffects = 1; 203} 204 205//===----------------------------------------------------------------------===// 206// Instruction format superclass 207//===----------------------------------------------------------------------===// 208 209include "MipsInstrFormats.td" 210 211//===----------------------------------------------------------------------===// 212// Mips Operand, Complex Patterns and Transformations Definitions. 213//===----------------------------------------------------------------------===// 214 215// Instruction operand types 216def jmptarget : Operand<OtherVT> { 217 let EncoderMethod = "getJumpTargetOpValue"; 218} 219def brtarget : Operand<OtherVT> { 220 let EncoderMethod = "getBranchTargetOpValue"; 221 let OperandType = "OPERAND_PCREL"; 222 let DecoderMethod = "DecodeBranchTarget"; 223} 224def calltarget : Operand<iPTR> { 225 let EncoderMethod = "getJumpTargetOpValue"; 226} 227def calltarget64: Operand<i64>; 228def simm16 : Operand<i32> { 229 let DecoderMethod= "DecodeSimm16"; 230} 231def simm16_64 : Operand<i64>; 232def shamt : Operand<i32>; 233 234// Unsigned Operand 235def uimm16 : Operand<i32> { 236 let PrintMethod = "printUnsignedImm"; 237} 238 239def MipsMemAsmOperand : AsmOperandClass { 240 let Name = "Mem"; 241 let ParserMethod = "parseMemOperand"; 242} 243 244// Address operand 245def mem : Operand<i32> { 246 let PrintMethod = "printMemOperand"; 247 let MIOperandInfo = (ops CPURegs, simm16); 248 let EncoderMethod = "getMemEncoding"; 249 let ParserMatchClass = MipsMemAsmOperand; 250} 251 252def mem64 : Operand<i64> { 253 let PrintMethod = "printMemOperand"; 254 let MIOperandInfo = (ops CPU64Regs, simm16_64); 255 let EncoderMethod = "getMemEncoding"; 256 let ParserMatchClass = MipsMemAsmOperand; 257} 258 259def mem_ea : Operand<i32> { 260 let PrintMethod = "printMemOperandEA"; 261 let MIOperandInfo = (ops CPURegs, simm16); 262 let EncoderMethod = "getMemEncoding"; 263} 264 265def mem_ea_64 : Operand<i64> { 266 let PrintMethod = "printMemOperandEA"; 267 let MIOperandInfo = (ops CPU64Regs, simm16_64); 268 let EncoderMethod = "getMemEncoding"; 269} 270 271// size operand of ext instruction 272def size_ext : Operand<i32> { 273 let EncoderMethod = "getSizeExtEncoding"; 274 let DecoderMethod = "DecodeExtSize"; 275} 276 277// size operand of ins instruction 278def size_ins : Operand<i32> { 279 let EncoderMethod = "getSizeInsEncoding"; 280 let DecoderMethod = "DecodeInsSize"; 281} 282 283// Transformation Function - get the lower 16 bits. 284def LO16 : SDNodeXForm<imm, [{ 285 return getImm(N, N->getZExtValue() & 0xFFFF); 286}]>; 287 288// Transformation Function - get the higher 16 bits. 289def HI16 : SDNodeXForm<imm, [{ 290 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 291}]>; 292 293// Node immediate fits as 16-bit sign extended on target immediate. 294// e.g. addi, andi 295def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 296 297// Node immediate fits as 16-bit zero extended on target immediate. 298// The LO16 param means that only the lower 16 bits of the node 299// immediate are caught. 300// e.g. addiu, sltiu 301def immZExt16 : PatLeaf<(imm), [{ 302 if (N->getValueType(0) == MVT::i32) 303 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 304 else 305 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 306}], LO16>; 307 308// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 309def immLow16Zero : PatLeaf<(imm), [{ 310 int64_t Val = N->getSExtValue(); 311 return isInt<32>(Val) && !(Val & 0xffff); 312}]>; 313 314// shamt field must fit in 5 bits. 315def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 316 317// Mips Address Mode! SDNode frameindex could possibily be a match 318// since load and store instructions from stack used it. 319def addr : 320 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 321 322//===----------------------------------------------------------------------===// 323// Instructions specific format 324//===----------------------------------------------------------------------===// 325 326/// Move Control Registers From/To CPU Registers 327def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 328 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 329def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 330 331def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 332 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 333def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 334 335def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 336 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 337def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 338 339def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 340 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 341def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 342 343// Arithmetic and logical instructions with 3 register operands. 344class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, 345 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 346 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 347 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 348 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> { 349 let shamt = 0; 350 let isCommutable = isComm; 351 let isReMaterializable = 1; 352} 353 354class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm, 355 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 356 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 357 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> { 358 let shamt = 0; 359 let isCommutable = isComm; 360} 361 362// Arithmetic and logical instructions with 2 register operands. 363class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode, 364 Operand Od, PatLeaf imm_type, RegisterClass RC> : 365 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 366 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 367 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> { 368 let isReMaterializable = 1; 369} 370 371class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode, 372 Operand Od, PatLeaf imm_type, RegisterClass RC> : 373 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 374 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>; 375 376// Arithmetic Multiply ADD/SUB 377let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 378class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 379 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 380 !strconcat(instr_asm, "\t$rs, $rt"), 381 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 382 let rd = 0; 383 let shamt = 0; 384 let isCommutable = isComm; 385} 386 387// Logical 388class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 389 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 390 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 391 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 392 let shamt = 0; 393 let isCommutable = 1; 394} 395 396// Shifts 397class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm, 398 SDNode OpNode, PatFrag PF, Operand ImmOpnd, 399 RegisterClass RC>: 400 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 401 !strconcat(instr_asm, "\t$rd, $rt, $shamt"), 402 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> { 403 let rs = isRotate; 404} 405 406// 32-bit shift instructions. 407class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm, 408 SDNode OpNode>: 409 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>; 410 411class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, 412 SDNode OpNode, RegisterClass RC>: 413 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 414 !strconcat(instr_asm, "\t$rd, $rt, $rs"), 415 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { 416 let shamt = isRotate; 417} 418 419// Load Upper Imediate 420class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 421 FI<op, (outs RC:$rt), (ins Imm:$imm16), 422 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { 423 let rs = 0; 424 let neverHasSideEffects = 1; 425 let isReMaterializable = 1; 426} 427 428class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 429 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 430 bits<21> addr; 431 let Inst{25-21} = addr{20-16}; 432 let Inst{15-0} = addr{15-0}; 433 let DecoderMethod = "DecodeMem"; 434} 435 436// Memory Load/Store 437let canFoldAsLoad = 1 in 438class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 439 Operand MemOpnd, bit Pseudo>: 440 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 441 !strconcat(instr_asm, "\t$rt, $addr"), 442 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 443 let isPseudo = Pseudo; 444} 445 446class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 447 Operand MemOpnd, bit Pseudo>: 448 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 449 !strconcat(instr_asm, "\t$rt, $addr"), 450 [(OpNode RC:$rt, addr:$addr)], IIStore> { 451 let isPseudo = Pseudo; 452} 453 454// 32-bit load. 455multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 456 bit Pseudo = 0> { 457 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 458 Requires<[NotN64, HasStdEnc]>; 459 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 460 Requires<[IsN64, HasStdEnc]> { 461 let DecoderNamespace = "Mips64"; 462 let isCodeGenOnly = 1; 463 } 464} 465 466// 64-bit load. 467multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 468 bit Pseudo = 0> { 469 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 470 Requires<[NotN64, HasStdEnc]>; 471 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 472 Requires<[IsN64, HasStdEnc]> { 473 let DecoderNamespace = "Mips64"; 474 let isCodeGenOnly = 1; 475 } 476} 477 478// 32-bit store. 479multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 480 bit Pseudo = 0> { 481 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 482 Requires<[NotN64, HasStdEnc]>; 483 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 484 Requires<[IsN64, HasStdEnc]> { 485 let DecoderNamespace = "Mips64"; 486 let isCodeGenOnly = 1; 487 } 488} 489 490// 64-bit store. 491multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 492 bit Pseudo = 0> { 493 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 494 Requires<[NotN64, HasStdEnc]>; 495 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 496 Requires<[IsN64, HasStdEnc]> { 497 let DecoderNamespace = "Mips64"; 498 let isCodeGenOnly = 1; 499 } 500} 501 502// Load/Store Left/Right 503let canFoldAsLoad = 1 in 504class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 505 RegisterClass RC, Operand MemOpnd> : 506 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 507 !strconcat(instr_asm, "\t$rt, $addr"), 508 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 509 string Constraints = "$src = $rt"; 510} 511 512class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 513 RegisterClass RC, Operand MemOpnd>: 514 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 515 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 516 IIStore>; 517 518// 32-bit load left/right. 519multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 520 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 521 Requires<[NotN64, HasStdEnc]>; 522 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 523 Requires<[IsN64, HasStdEnc]> { 524 let DecoderNamespace = "Mips64"; 525 let isCodeGenOnly = 1; 526 } 527} 528 529// 64-bit load left/right. 530multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 531 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 532 Requires<[NotN64, HasStdEnc]>; 533 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 534 Requires<[IsN64, HasStdEnc]> { 535 let DecoderNamespace = "Mips64"; 536 let isCodeGenOnly = 1; 537 } 538} 539 540// 32-bit store left/right. 541multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 542 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 543 Requires<[NotN64, HasStdEnc]>; 544 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 545 Requires<[IsN64, HasStdEnc]> { 546 let DecoderNamespace = "Mips64"; 547 let isCodeGenOnly = 1; 548 } 549} 550 551// 64-bit store left/right. 552multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 553 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 554 Requires<[NotN64, HasStdEnc]>; 555 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 556 Requires<[IsN64, HasStdEnc]> { 557 let DecoderNamespace = "Mips64"; 558 let isCodeGenOnly = 1; 559 } 560} 561 562// Conditional Branch 563class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>: 564 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 565 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 566 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { 567 let isBranch = 1; 568 let isTerminator = 1; 569 let hasDelaySlot = 1; 570 let Defs = [AT]; 571} 572 573class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op, 574 RegisterClass RC>: 575 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16), 576 !strconcat(instr_asm, "\t$rs, $imm16"), 577 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { 578 let rt = _rt; 579 let isBranch = 1; 580 let isTerminator = 1; 581 let hasDelaySlot = 1; 582 let Defs = [AT]; 583} 584 585// SetCC 586class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 587 RegisterClass RC>: 588 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 589 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 590 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 591 IIAlu> { 592 let shamt = 0; 593} 594 595class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 596 PatLeaf imm_type, RegisterClass RC>: 597 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 598 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 599 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 600 IIAlu>; 601 602// Jump 603class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 604 SDPatternOperator operator, SDPatternOperator targetoperator>: 605 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 606 [(operator targetoperator:$target)], IIBranch> { 607 let isTerminator=1; 608 let isBarrier=1; 609 let hasDelaySlot = 1; 610 let DecoderMethod = "DecodeJumpTarget"; 611 let Defs = [AT]; 612} 613 614// Unconditional branch 615class UncondBranch<bits<6> op, string instr_asm>: 616 BranchBase<op, (outs), (ins brtarget:$imm16), 617 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 618 let rs = 0; 619 let rt = 0; 620 let isBranch = 1; 621 let isTerminator = 1; 622 let isBarrier = 1; 623 let hasDelaySlot = 1; 624 let Predicates = [RelocPIC, HasStdEnc]; 625 let Defs = [AT]; 626} 627 628// Base class for indirect branch and return instruction classes. 629let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 630class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 631 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 632 let rt = 0; 633 let rd = 0; 634 let shamt = 0; 635} 636 637// Indirect branch 638class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 639 let isBranch = 1; 640 let isIndirectBranch = 1; 641} 642 643// Return instruction 644class RetBase<RegisterClass RC>: JumpFR<RC> { 645 let isReturn = 1; 646 let isCodeGenOnly = 1; 647 let hasCtrlDep = 1; 648 let hasExtraSrcRegAllocReq = 1; 649} 650 651// Jump and Link (Call) 652let isCall=1, hasDelaySlot=1, Defs = [RA] in { 653 class JumpLink<bits<6> op, string instr_asm>: 654 FJ<op, (outs), (ins calltarget:$target), 655 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 656 IIBranch> { 657 let DecoderMethod = "DecodeJumpTarget"; 658 } 659 660 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 661 RegisterClass RC>: 662 FR<op, func, (outs), (ins RC:$rs), 663 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 664 let rt = 0; 665 let rd = 31; 666 let shamt = 0; 667 } 668 669 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 670 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 671 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 672 let rt = _rt; 673 } 674} 675 676// Mul, Div 677class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 678 RegisterClass RC, list<Register> DefRegs>: 679 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 680 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 681 let rd = 0; 682 let shamt = 0; 683 let isCommutable = 1; 684 let Defs = DefRegs; 685 let neverHasSideEffects = 1; 686} 687 688class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 689 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 690 691class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 692 RegisterClass RC, list<Register> DefRegs>: 693 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 694 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 695 [(op RC:$rs, RC:$rt)], itin> { 696 let rd = 0; 697 let shamt = 0; 698 let Defs = DefRegs; 699} 700 701class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 702 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 703 704// Move from Hi/Lo 705class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 706 list<Register> UseRegs>: 707 FR<0x00, func, (outs RC:$rd), (ins), 708 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 709 let rs = 0; 710 let rt = 0; 711 let shamt = 0; 712 let Uses = UseRegs; 713 let neverHasSideEffects = 1; 714} 715 716class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 717 list<Register> DefRegs>: 718 FR<0x00, func, (outs), (ins RC:$rs), 719 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 720 let rt = 0; 721 let rd = 0; 722 let shamt = 0; 723 let Defs = DefRegs; 724 let neverHasSideEffects = 1; 725} 726 727class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 728 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 729 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 730 let isCodeGenOnly = 1; 731} 732 733// Count Leading Ones/Zeros in Word 734class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 735 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 736 !strconcat(instr_asm, "\t$rd, $rs"), 737 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 738 Requires<[HasBitCount, HasStdEnc]> { 739 let shamt = 0; 740 let rt = rd; 741} 742 743class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 744 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 745 !strconcat(instr_asm, "\t$rd, $rs"), 746 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 747 Requires<[HasBitCount, HasStdEnc]> { 748 let shamt = 0; 749 let rt = rd; 750} 751 752// Sign Extend in Register. 753class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 754 RegisterClass RC>: 755 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 756 !strconcat(instr_asm, "\t$rd, $rt"), 757 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 758 let rs = 0; 759 let shamt = sa; 760 let Predicates = [HasSEInReg, HasStdEnc]; 761} 762 763// Subword Swap 764class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 765 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 766 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 767 let rs = 0; 768 let shamt = sa; 769 let Predicates = [HasSwap, HasStdEnc]; 770 let neverHasSideEffects = 1; 771} 772 773// Read Hardware 774class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 775 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 776 "rdhwr\t$rt, $rd", [], IIAlu> { 777 let rs = 0; 778 let shamt = 0; 779} 780 781// Ext and Ins 782class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 783 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 784 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 785 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 786 bits<5> pos; 787 bits<5> sz; 788 let rd = sz; 789 let shamt = pos; 790 let Predicates = [HasMips32r2, HasStdEnc]; 791} 792 793class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 794 FR<0x1f, _funct, (outs RC:$rt), 795 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 796 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 797 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 798 NoItinerary> { 799 bits<5> pos; 800 bits<5> sz; 801 let rd = sz; 802 let shamt = pos; 803 let Predicates = [HasMips32r2, HasStdEnc]; 804 let Constraints = "$src = $rt"; 805} 806 807// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 808class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 809 RegisterClass PRC> : 810 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 811 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 812 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 813 814multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 815 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 816 Requires<[NotN64, HasStdEnc]>; 817 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 818 Requires<[IsN64, HasStdEnc]> { 819 let DecoderNamespace = "Mips64"; 820 } 821} 822 823// Atomic Compare & Swap. 824class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 825 RegisterClass PRC> : 826 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 827 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 828 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 829 830multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 831 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 832 Requires<[NotN64, HasStdEnc]>; 833 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 834 Requires<[IsN64, HasStdEnc]> { 835 let DecoderNamespace = "Mips64"; 836 } 837} 838 839class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 840 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 841 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 842 let mayLoad = 1; 843} 844 845class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 846 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 847 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 848 let mayStore = 1; 849 let Constraints = "$rt = $dst"; 850} 851 852//===----------------------------------------------------------------------===// 853// Pseudo instructions 854//===----------------------------------------------------------------------===// 855 856// Return RA. 857let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 858def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 859 860let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 861def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 862 "!ADJCALLSTACKDOWN $amt", 863 [(callseq_start timm:$amt)]>; 864def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 865 "!ADJCALLSTACKUP $amt1", 866 [(callseq_end timm:$amt1, timm:$amt2)]>; 867} 868 869// When handling PIC code the assembler needs .cpload and .cprestore 870// directives. If the real instructions corresponding these directives 871// are used, we have the same behavior, but get also a bunch of warnings 872// from the assembler. 873let neverHasSideEffects = 1 in 874def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 875 ".cprestore\t$loc", []>; 876 877let usesCustomInserter = 1 in { 878 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 879 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 880 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 881 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 882 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 883 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 884 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 885 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 886 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 887 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 888 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 889 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 890 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 891 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 892 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 893 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 894 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 895 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 896 897 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 898 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 899 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 900 901 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 902 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 903 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 904} 905 906//===----------------------------------------------------------------------===// 907// Instruction definition 908//===----------------------------------------------------------------------===// 909 910class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 911 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 912 !strconcat(instr_asm, "\t$rt, $imm32")> ; 913def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 914 915class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 916 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 917 !strconcat(instr_asm, "\t$rt, $addr")> ; 918def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 919 920class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 921 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 922 !strconcat(instr_asm, "\t$rt, $imm32")> ; 923def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 924 925//===----------------------------------------------------------------------===// 926// MipsI Instructions 927//===----------------------------------------------------------------------===// 928 929/// Arithmetic Instructions (ALU Immediate) 930def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>, 931 IsAsCheapAsAMove; 932def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; 933def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 934def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 935def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; 936def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; 937def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; 938def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 939 940/// Arithmetic Instructions (3-Operand, R-Type) 941def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; 942def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>; 943def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; 944def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>; 945def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 946def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 947def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; 948def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; 949def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; 950def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 951 952/// Shift Instructions 953def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; 954def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>; 955def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>; 956def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>; 957def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>; 958def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>; 959 960// Rotate Instructions 961let Predicates = [HasMips32r2, HasStdEnc] in { 962 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>; 963 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>; 964} 965 966/// Load and Store Instructions 967/// aligned 968defm LB : LoadM32<0x20, "lb", sextloadi8>; 969defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 970defm LH : LoadM32<0x21, "lh", sextloadi16>; 971defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 972defm LW : LoadM32<0x23, "lw", load>; 973defm SB : StoreM32<0x28, "sb", truncstorei8>; 974defm SH : StoreM32<0x29, "sh", truncstorei16>; 975defm SW : StoreM32<0x2b, "sw", store>; 976 977/// load/store left/right 978defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 979defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 980defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 981defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 982 983let hasSideEffects = 1 in 984def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 985 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 986{ 987 bits<5> stype; 988 let Opcode = 0; 989 let Inst{25-11} = 0; 990 let Inst{10-6} = stype; 991 let Inst{5-0} = 15; 992} 993 994/// Load-linked, Store-conditional 995def LL : LLBase<0x30, "ll", CPURegs, mem>, 996 Requires<[NotN64, HasStdEnc]>; 997def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 998 Requires<[IsN64, HasStdEnc]> { 999 let DecoderNamespace = "Mips64"; 1000} 1001 1002def SC : SCBase<0x38, "sc", CPURegs, mem>, 1003 Requires<[NotN64, HasStdEnc]>; 1004def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 1005 Requires<[IsN64, HasStdEnc]> { 1006 let DecoderNamespace = "Mips64"; 1007} 1008 1009/// Jump and Branch Instructions 1010def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 1011 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 1012def JR : IndirectBranch<CPURegs>; 1013def B : UncondBranch<0x04, "b">; 1014def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; 1015def BNE : CBranch<0x05, "bne", setne, CPURegs>; 1016def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; 1017def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 1018def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; 1019def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; 1020 1021let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 1022 hasDelaySlot = 1, Defs = [RA] in 1023def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 1024 1025def JAL : JumpLink<0x03, "jal">; 1026def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 1027def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 1028def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 1029def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 1030def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 1031 1032def RET : RetBase<CPURegs>; 1033 1034/// Multiply and Divide Instructions. 1035def MULT : Mult32<0x18, "mult", IIImul>; 1036def MULTu : Mult32<0x19, "multu", IIImul>; 1037def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 1038def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 1039 1040def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1041def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1042def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1043def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1044 1045/// Sign Ext In Register Instructions. 1046def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1047def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1048 1049/// Count Leading 1050def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1051def CLO : CountLeading1<0x21, "clo", CPURegs>; 1052 1053/// Word Swap Bytes Within Halfwords 1054def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1055 1056/// No operation 1057let addr=0 in 1058 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1059 1060// FrameIndexes are legalized when they are operands from load/store 1061// instructions. The same not happens for stack address copies, so an 1062// add op with mem ComplexPattern is used and the stack address copy 1063// can be matched. It's similar to Sparc LEA_ADDRi 1064def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1065 1066// MADD*/MSUB* 1067def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1068def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1069def MSUB : MArithR<4, "msub", MipsMSub>; 1070def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1071 1072// MUL is a assembly macro in the current used ISAs. In recent ISA's 1073// it is a real instruction. 1074def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, 1075 Requires<[HasStdEnc]>; 1076 1077def RDHWR : ReadHardware<CPURegs, HWRegs>; 1078 1079def EXT : ExtBase<0, "ext", CPURegs>; 1080def INS : InsBase<4, "ins", CPURegs>; 1081 1082//===----------------------------------------------------------------------===// 1083// Instruction aliases 1084//===----------------------------------------------------------------------===// 1085def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1086def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1087def : InstAlias<"addu $rs,$rt,$imm", 1088 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1089def : InstAlias<"add $rs,$rt,$imm", 1090 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1091def : InstAlias<"and $rs,$rt,$imm", 1092 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1093def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1094def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1095def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1096def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1097def : InstAlias<"slt $rs,$rt,$imm", 1098 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1099def : InstAlias<"xor $rs,$rt,$imm", 1100 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1101 1102//===----------------------------------------------------------------------===// 1103// Arbitrary patterns that map to one or more instructions 1104//===----------------------------------------------------------------------===// 1105 1106// Small immediates 1107def : MipsPat<(i32 immSExt16:$in), 1108 (ADDiu ZERO, imm:$in)>; 1109def : MipsPat<(i32 immZExt16:$in), 1110 (ORi ZERO, imm:$in)>; 1111def : MipsPat<(i32 immLow16Zero:$in), 1112 (LUi (HI16 imm:$in))>; 1113 1114// Arbitrary immediates 1115def : MipsPat<(i32 imm:$imm), 1116 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1117 1118// Carry MipsPatterns 1119def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1120 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1121def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1122 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1123def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1124 (ADDiu CPURegs:$src, imm:$imm)>; 1125 1126// Call 1127def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1128 (JAL tglobaladdr:$dst)>; 1129def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1130 (JAL texternalsym:$dst)>; 1131//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1132// (JALR CPURegs:$dst)>; 1133 1134// Tail call 1135def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1136 (TAILCALL tglobaladdr:$dst)>; 1137def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1138 (TAILCALL texternalsym:$dst)>; 1139// hi/lo relocs 1140def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1141def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1142def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1143def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1144def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1145def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1146 1147def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1148def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1149def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1150def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1151def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1152def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1153 1154def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1155 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1156def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1157 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1158def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1159 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1160def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1161 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1162def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1163 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1164 1165// gp_rel relocs 1166def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1167 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1168def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1169 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1170 1171// wrapper_pic 1172class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1173 MipsPat<(MipsWrapper RC:$gp, node:$in), 1174 (ADDiuOp RC:$gp, node:$in)>; 1175 1176def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1177def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1178def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1179def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1180def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1181def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1182 1183// Mips does not have "not", so we expand our way 1184def : MipsPat<(not CPURegs:$in), 1185 (NOR CPURegs:$in, ZERO)>; 1186 1187// extended loads 1188let Predicates = [NotN64, HasStdEnc] in { 1189 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1190 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1191 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1192} 1193let Predicates = [IsN64, HasStdEnc] in { 1194 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1195 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1196 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1197} 1198 1199// peepholes 1200let Predicates = [NotN64, HasStdEnc] in { 1201 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1202} 1203let Predicates = [IsN64, HasStdEnc] in { 1204 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1205} 1206 1207// brcond patterns 1208multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1209 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1210 Instruction SLTiuOp, Register ZEROReg> { 1211def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1212 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1213def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1214 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1215 1216def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1217 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1218def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1219 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1220def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1221 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1222def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1223 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1224 1225def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1226 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1227def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1228 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1229 1230def : MipsPat<(brcond RC:$cond, bb:$dst), 1231 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1232} 1233 1234defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1235 1236// setcc patterns 1237multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1238 Instruction SLTuOp, Register ZEROReg> { 1239 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1240 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1241 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1242 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1243} 1244 1245multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1246 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1247 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1248 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1249 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1250} 1251 1252multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1253 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1254 (SLTOp RC:$rhs, RC:$lhs)>; 1255 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1256 (SLTuOp RC:$rhs, RC:$lhs)>; 1257} 1258 1259multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1260 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1261 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1262 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1263 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1264} 1265 1266multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1267 Instruction SLTiuOp> { 1268 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1269 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1270 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1271 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1272} 1273 1274defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1275defm : SetlePats<CPURegs, SLT, SLTu>; 1276defm : SetgtPats<CPURegs, SLT, SLTu>; 1277defm : SetgePats<CPURegs, SLT, SLTu>; 1278defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1279 1280// bswap pattern 1281def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1282 1283//===----------------------------------------------------------------------===// 1284// Floating Point Support 1285//===----------------------------------------------------------------------===// 1286 1287include "MipsInstrFPU.td" 1288include "Mips64InstrInfo.td" 1289include "MipsCondMov.td" 1290 1291// 1292// Mips16 1293 1294include "Mips16InstrFormats.td" 1295include "Mips16InstrInfo.td" 1296 1297// DSP 1298include "MipsDSPInstrFormats.td" 1299include "MipsDSPInstrInfo.td" 1300 1301