MipsMCInstLower.cpp revision 3185f9a2ea80afec30064b7cd095f82c31dc154e 
1//===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains code to lower Mips MachineInstrs to their corresponding
11// MCInst records.
12//
13//===----------------------------------------------------------------------===//
14#include "MipsMCInstLower.h"
15#include "MipsAsmPrinter.h"
16#include "MipsInstrInfo.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineInstr.h"
20#include "llvm/CodeGen/MachineOperand.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/Target/Mangler.h"
25
26using namespace llvm;
27
28MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter)
29  : AsmPrinter(asmprinter) {}
30
31void MipsMCInstLower::Initialize(Mangler *M, MCContext *C) {
32  Mang = M;
33  Ctx = C;
34}
35
36MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
37                                              MachineOperandType MOTy,
38                                              unsigned Offset) const {
39  MCSymbolRefExpr::VariantKind Kind;
40  const MCSymbol *Symbol;
41
42  switch(MO.getTargetFlags()) {
43  default:                   llvm_unreachable("Invalid target flag!");
44  case MipsII::MO_NO_FLAG:   Kind = MCSymbolRefExpr::VK_None; break;
45  case MipsII::MO_GPREL:     Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
46  case MipsII::MO_GOT_CALL:  Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
47  case MipsII::MO_GOT16:     Kind = MCSymbolRefExpr::VK_Mips_GOT16; break;
48  case MipsII::MO_GOT:       Kind = MCSymbolRefExpr::VK_Mips_GOT; break;
49  case MipsII::MO_ABS_HI:    Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break;
50  case MipsII::MO_ABS_LO:    Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break;
51  case MipsII::MO_TLSGD:     Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break;
52  case MipsII::MO_TLSLDM:    Kind = MCSymbolRefExpr::VK_Mips_TLSLDM; break;
53  case MipsII::MO_DTPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_HI; break;
54  case MipsII::MO_DTPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_LO; break;
55  case MipsII::MO_GOTTPREL:  Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break;
56  case MipsII::MO_TPREL_HI:  Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break;
57  case MipsII::MO_TPREL_LO:  Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break;
58  case MipsII::MO_GPOFF_HI:  Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break;
59  case MipsII::MO_GPOFF_LO:  Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break;
60  case MipsII::MO_GOT_DISP:  Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break;
61  case MipsII::MO_GOT_PAGE:  Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break;
62  case MipsII::MO_GOT_OFST:  Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break;
63  case MipsII::MO_HIGHER:    Kind = MCSymbolRefExpr::VK_Mips_HIGHER; break;
64  case MipsII::MO_HIGHEST:   Kind = MCSymbolRefExpr::VK_Mips_HIGHEST; break;
65  }
66
67  switch (MOTy) {
68  case MachineOperand::MO_MachineBasicBlock:
69    Symbol = MO.getMBB()->getSymbol();
70    break;
71
72  case MachineOperand::MO_GlobalAddress:
73    Symbol = Mang->getSymbol(MO.getGlobal());
74    Offset += MO.getOffset();
75    break;
76
77  case MachineOperand::MO_BlockAddress:
78    Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
79    Offset += MO.getOffset();
80    break;
81
82  case MachineOperand::MO_ExternalSymbol:
83    Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
84    Offset += MO.getOffset();
85    break;
86
87  case MachineOperand::MO_JumpTableIndex:
88    Symbol = AsmPrinter.GetJTISymbol(MO.getIndex());
89    break;
90
91  case MachineOperand::MO_ConstantPoolIndex:
92    Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
93    Offset += MO.getOffset();
94    break;
95
96  default:
97    llvm_unreachable("<unknown operand type>");
98  }
99
100  const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx);
101
102  if (!Offset)
103    return MCOperand::CreateExpr(MCSym);
104
105  // Assume offset is never negative.
106  assert(Offset > 0);
107
108  const MCConstantExpr *OffsetExpr =  MCConstantExpr::Create(Offset, *Ctx);
109  const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx);
110  return MCOperand::CreateExpr(Add);
111}
112
113/*
114static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand &Opnd0,
115                         const MCOperand &Opnd1,
116                         const MCOperand &Opnd2 = MCOperand()) {
117  Inst.setOpcode(Opc);
118  Inst.addOperand(Opnd0);
119  Inst.addOperand(Opnd1);
120  if (Opnd2.isValid())
121    Inst.addOperand(Opnd2);
122}
123*/
124
125MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
126                                        unsigned offset) const {
127  MachineOperandType MOTy = MO.getType();
128
129  switch (MOTy) {
130  default: llvm_unreachable("unknown operand type");
131  case MachineOperand::MO_Register:
132    // Ignore all implicit register operands.
133    if (MO.isImplicit()) break;
134    return MCOperand::CreateReg(MO.getReg());
135  case MachineOperand::MO_Immediate:
136    return MCOperand::CreateImm(MO.getImm() + offset);
137  case MachineOperand::MO_MachineBasicBlock:
138  case MachineOperand::MO_GlobalAddress:
139  case MachineOperand::MO_ExternalSymbol:
140  case MachineOperand::MO_JumpTableIndex:
141  case MachineOperand::MO_ConstantPoolIndex:
142  case MachineOperand::MO_BlockAddress:
143    return LowerSymbolOperand(MO, MOTy, offset);
144  case MachineOperand::MO_RegisterMask:
145    break;
146 }
147
148  return MCOperand();
149}
150
151void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
152  OutMI.setOpcode(MI->getOpcode());
153
154  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
155    const MachineOperand &MO = MI->getOperand(i);
156    MCOperand MCOp = LowerOperand(MO);
157
158    if (MCOp.isValid())
159      OutMI.addOperand(MCOp);
160  }
161}
162
163// If the D<shift> instruction has a shift amount that is greater
164// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
165void MipsMCInstLower::LowerLargeShift(const MachineInstr *MI,
166                                      MCInst& Inst,
167                                      int64_t Shift) {
168  // rt
169  Inst.addOperand(LowerOperand(MI->getOperand(0)));
170  // rd
171  Inst.addOperand(LowerOperand(MI->getOperand(1)));
172  // saminus32
173  Inst.addOperand(MCOperand::CreateImm(Shift));
174
175  switch (MI->getOpcode()) {
176  default:
177    // Calling function is not synchronized
178    llvm_unreachable("Unexpected shift instruction");
179    break;
180  case Mips::DSLL:
181    Inst.setOpcode(Mips::DSLL32);
182    break;
183  case Mips::DSRL:
184    Inst.setOpcode(Mips::DSRL32);
185    break;
186  case Mips::DSRA:
187    Inst.setOpcode(Mips::DSRA32);
188    break;
189  }
190}
191
192// Pick a DEXT or DINS instruction variant based on the pos and size operands
193void MipsMCInstLower::LowerDextDins(const MachineInstr *MI,  MCInst& Inst) {
194  int Opcode = MI->getOpcode();
195
196  if (Opcode == Mips::DEXT)
197    assert(MI->getNumOperands() == 4 &&
198           "Invalid no. of machine operands for DEXT!");
199  else // Only DEXT and DINS are possible
200    assert(MI->getNumOperands() == 5 &&
201           "Invalid no. of machine operands for DINS!");
202
203  assert(MI->getOperand(2).isImm());
204  int64_t pos = MI->getOperand(2).getImm();
205  assert(MI->getOperand(3).isImm());
206  int64_t size = MI->getOperand(3).getImm();
207
208  // rt
209  Inst.addOperand(LowerOperand(MI->getOperand(0)));
210  // rs
211  Inst.addOperand(LowerOperand(MI->getOperand(1)));
212
213  if (size <= 32) {
214    if ((pos < 32)) { // DEXT/DINS
215      Inst.addOperand(MCOperand::CreateImm(pos));
216      Inst.addOperand(MCOperand::CreateImm(size));
217      Inst.setOpcode(Opcode);
218    } else { // DEXTU/DINSU
219      Inst.addOperand(MCOperand::CreateImm(pos - 32));
220      Inst.addOperand(MCOperand::CreateImm(size));
221      Inst.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
222    }
223  } else { // DEXTM/DINSM
224    assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
225    Inst.addOperand(MCOperand::CreateImm(pos));
226    Inst.addOperand(MCOperand::CreateImm(size - 32));
227    Inst.setOpcode(Mips::DEXTM);
228    Inst.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
229  }
230}
231