MipsMCInstLower.cpp revision b22c9289b0dd8255f63038e9bb8229111eb082ae
1f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson//===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===// 2f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// 3f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// The LLVM Compiler Infrastructure 4f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// 5f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// This file is distributed under the University of Illinois Open Source 6f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// License. See LICENSE.TXT for details. 7f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// 8f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson//===----------------------------------------------------------------------===// 9f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// 10f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// This file contains code to lower Mips MachineInstrs to their corresponding 11f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// MCInst records. 12f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson// 13f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson//===----------------------------------------------------------------------===// 14f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 15f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "MipsMCInstLower.h" 16f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "MipsAsmPrinter.h" 17f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "MipsInstrInfo.h" 18f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "MCTargetDesc/MipsBaseInfo.h" 19f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "llvm/CodeGen/MachineFunction.h" 20f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "llvm/CodeGen/MachineInstr.h" 21f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "llvm/CodeGen/MachineOperand.h" 22f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "llvm/MC/MCContext.h" 23f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "llvm/MC/MCExpr.h" 24f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "llvm/MC/MCInst.h" 25f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson#include "llvm/Target/Mangler.h" 26f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 27f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodsonusing namespace llvm; 28f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 29f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian HodsonMipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter) 30f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson : AsmPrinter(asmprinter) {} 31f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 32f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodsonvoid MipsMCInstLower::Initialize(Mangler *M, MCContext *C) { 33f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Mang = M; 34f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Ctx = C; 35f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson} 36f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 37f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian HodsonMCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, 38f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson MachineOperandType MOTy, 39f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson unsigned Offset) const { 40f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson MCSymbolRefExpr::VariantKind Kind; 41f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson const MCSymbol *Symbol; 42f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 43f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson switch(MO.getTargetFlags()) { 44f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson default: llvm_unreachable("Invalid target flag!"); 45f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break; 46f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break; 47f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break; 48f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GOT16: Kind = MCSymbolRefExpr::VK_Mips_GOT16; break; 49f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break; 50f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break; 51f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break; 52f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break; 53f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_TLSLDM: Kind = MCSymbolRefExpr::VK_Mips_TLSLDM; break; 54f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_DTPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_HI; break; 55f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_DTPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_LO; break; 56f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break; 57f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break; 58f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break; 59f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break; 60f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break; 61f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break; 62f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break; 63f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break; 64f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_HIGHER: Kind = MCSymbolRefExpr::VK_Mips_HIGHER; break; 65f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MipsII::MO_HIGHEST: Kind = MCSymbolRefExpr::VK_Mips_HIGHEST; break; 66f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson } 67f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 68f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson switch (MOTy) { 69f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MachineOperand::MO_MachineBasicBlock: 70f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Symbol = MO.getMBB()->getSymbol(); 71f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson break; 72f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 73f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MachineOperand::MO_GlobalAddress: 74f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Symbol = Mang->getSymbol(MO.getGlobal()); 75f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Offset += MO.getOffset(); 76f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson break; 77f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 78f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MachineOperand::MO_BlockAddress: 79f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()); 80f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Offset += MO.getOffset(); 81f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson break; 82f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 83f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MachineOperand::MO_ExternalSymbol: 84f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName()); 85f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Offset += MO.getOffset(); 86f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson break; 87f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 88f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MachineOperand::MO_JumpTableIndex: 89f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Symbol = AsmPrinter.GetJTISymbol(MO.getIndex()); 90f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson break; 91f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 92f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson case MachineOperand::MO_ConstantPoolIndex: 93f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Symbol = AsmPrinter.GetCPISymbol(MO.getIndex()); 94f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Offset += MO.getOffset(); 95f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson break; 96f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 97f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson default: 98f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson llvm_unreachable("<unknown operand type>"); 99f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson } 100f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 101f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx); 102f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 103f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson if (!Offset) 104f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson return MCOperand::CreateExpr(MCSym); 105f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 106f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson // Assume offset is never negative. 107f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson assert(Offset > 0); 108f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 109f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx); 110f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx); 111f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson return MCOperand::CreateExpr(Add); 112f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson} 113f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 114f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson/* 115f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodsonstatic void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand &Opnd0, 116f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson const MCOperand &Opnd1, 117f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson const MCOperand &Opnd2 = MCOperand()) { 118f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Inst.setOpcode(Opc); 119f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Inst.addOperand(Opnd0); 120f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Inst.addOperand(Opnd1); 121f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson if (Opnd2.isValid()) 122f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson Inst.addOperand(Opnd2); 123f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson} 124f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson*/ 125f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian Hodson 126f4c12fce1ee58e670f9c3fce46c40296ba9ee8a2Ian HodsonMCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO, 127 unsigned offset) const { 128 MachineOperandType MOTy = MO.getType(); 129 130 switch (MOTy) { 131 default: llvm_unreachable("unknown operand type"); 132 case MachineOperand::MO_Register: 133 // Ignore all implicit register operands. 134 if (MO.isImplicit()) break; 135 return MCOperand::CreateReg(MO.getReg()); 136 case MachineOperand::MO_Immediate: 137 return MCOperand::CreateImm(MO.getImm() + offset); 138 case MachineOperand::MO_MachineBasicBlock: 139 case MachineOperand::MO_GlobalAddress: 140 case MachineOperand::MO_ExternalSymbol: 141 case MachineOperand::MO_JumpTableIndex: 142 case MachineOperand::MO_ConstantPoolIndex: 143 case MachineOperand::MO_BlockAddress: 144 return LowerSymbolOperand(MO, MOTy, offset); 145 case MachineOperand::MO_RegisterMask: 146 break; 147 } 148 149 return MCOperand(); 150} 151 152void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 153 OutMI.setOpcode(MI->getOpcode()); 154 155 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 156 const MachineOperand &MO = MI->getOperand(i); 157 MCOperand MCOp = LowerOperand(MO); 158 159 if (MCOp.isValid()) 160 OutMI.addOperand(MCOp); 161 } 162} 163 164// If the D<shift> instruction has a shift amount that is greater 165// than 31 (checked in calling routine), lower it to a D<shift>32 instruction 166void MipsMCInstLower::LowerLargeShift(const MachineInstr *MI, 167 MCInst& Inst, 168 int64_t Shift) { 169 // rt 170 Inst.addOperand(LowerOperand(MI->getOperand(0))); 171 // rd 172 Inst.addOperand(LowerOperand(MI->getOperand(1))); 173 // saminus32 174 Inst.addOperand(MCOperand::CreateImm(Shift)); 175 176 switch (MI->getOpcode()) { 177 default: 178 // Calling function is not synchronized 179 llvm_unreachable("Unexpected shift instruction"); 180 break; 181 case Mips::DSLL: 182 Inst.setOpcode(Mips::DSLL32); 183 break; 184 case Mips::DSRL: 185 Inst.setOpcode(Mips::DSRL32); 186 break; 187 case Mips::DSRA: 188 Inst.setOpcode(Mips::DSRA32); 189 break; 190 } 191} 192