MipsMSAInstrFormats.td revision 006cff8d7b60ddf632f8642f01693dace7827d8b 
1//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasMSA : Predicate<"Subtarget.hasMSA()">,
11             AssemblerPredicate<"FeatureMSA">;
12
13class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14  let Predicates = [HasMSA];
15  let Inst{31-26} = 0b011110;
16}
17
18class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19                InstrItinClass itin = IIPseudo>:
20  MipsPseudo<outs, ins, pattern, itin> {
21  let Predicates = [HasMSA];
22}
23
24class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
25  bits<5> ws;
26  bits<5> wd;
27  bits<3> m;
28
29  let Inst{25-23} = major;
30  let Inst{22-19} = 0b1110;
31  let Inst{18-16} = m;
32  let Inst{15-11} = ws;
33  let Inst{10-6} = wd;
34  let Inst{5-0} = minor;
35}
36
37class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
38  bits<5> ws;
39  bits<5> wd;
40  bits<4> m;
41
42  let Inst{25-23} = major;
43  let Inst{22-20} = 0b110;
44  let Inst{19-16} = m;
45  let Inst{15-11} = ws;
46  let Inst{10-6} = wd;
47  let Inst{5-0} = minor;
48}
49
50class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
51  bits<5> ws;
52  bits<5> wd;
53  bits<5> m;
54
55  let Inst{25-23} = major;
56  let Inst{22-21} = 0b10;
57  let Inst{20-16} = m;
58  let Inst{15-11} = ws;
59  let Inst{10-6} = wd;
60  let Inst{5-0} = minor;
61}
62
63class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
64  bits<5> ws;
65  bits<5> wd;
66  bits<6> m;
67
68  let Inst{25-23} = major;
69  let Inst{22} = 0b0;
70  let Inst{21-16} = m;
71  let Inst{15-11} = ws;
72  let Inst{10-6} = wd;
73  let Inst{5-0} = minor;
74}
75
76class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
77  bits<5> rs;
78  bits<5> wd;
79
80  let Inst{25-18} = major;
81  let Inst{17-16} = df;
82  let Inst{15-11} = rs;
83  let Inst{10-6} = wd;
84  let Inst{5-0} = minor;
85}
86
87class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
88  bits<5> ws;
89  bits<5> wd;
90
91  let Inst{25-18} = major;
92  let Inst{17-16} = df;
93  let Inst{15-11} = ws;
94  let Inst{10-6} = wd;
95  let Inst{5-0} = minor;
96}
97
98class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
99  bits<5> ws;
100  bits<5> wd;
101
102  let Inst{25-17} = major;
103  let Inst{16} = df;
104  let Inst{15-11} = ws;
105  let Inst{10-6} = wd;
106  let Inst{5-0} = minor;
107}
108
109class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
110  bits<5> wt;
111  bits<5> ws;
112  bits<5> wd;
113
114  let Inst{25-23} = major;
115  let Inst{22-21} = df;
116  let Inst{20-16} = wt;
117  let Inst{15-11} = ws;
118  let Inst{10-6} = wd;
119  let Inst{5-0} = minor;
120}
121
122class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
123  bits<5> wt;
124  bits<5> ws;
125  bits<5> wd;
126
127  let Inst{25-22} = major;
128  let Inst{21} = df;
129  let Inst{20-16} = wt;
130  let Inst{15-11} = ws;
131  let Inst{10-6} = wd;
132  let Inst{5-0} = minor;
133}
134
135class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
136  bits<5> rt;
137  bits<5> ws;
138  bits<5> wd;
139
140  let Inst{25-23} = major;
141  let Inst{22-21} = df;
142  let Inst{20-16} = rt;
143  let Inst{15-11} = ws;
144  let Inst{10-6} = wd;
145  let Inst{5-0} = minor;
146}
147
148class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
149  let Inst{25-16} = major;
150  let Inst{5-0} = minor;
151}
152
153class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
154  bits<5> rd;
155  bits<5> cs;
156
157  let Inst{25-16} = major;
158  let Inst{15-11} = cs;
159  let Inst{10-6} = rd;
160  let Inst{5-0} = minor;
161}
162
163class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
164  bits<5> rs;
165  bits<5> cd;
166
167  let Inst{25-16} = major;
168  let Inst{15-11} = rs;
169  let Inst{10-6} = cd;
170  let Inst{5-0} = minor;
171}
172
173class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
174  bits<4> n;
175  bits<5> ws;
176  bits<5> wd;
177
178  let Inst{25-22} = major;
179  let Inst{21-20} = 0b00;
180  let Inst{19-16} = n{3-0};
181  let Inst{15-11} = ws;
182  let Inst{10-6} = wd;
183  let Inst{5-0} = minor;
184}
185
186class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
187  bits<4> n;
188  bits<5> ws;
189  bits<5> wd;
190
191  let Inst{25-22} = major;
192  let Inst{21-19} = 0b100;
193  let Inst{18-16} = n{2-0};
194  let Inst{15-11} = ws;
195  let Inst{10-6} = wd;
196  let Inst{5-0} = minor;
197}
198
199class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
200  bits<4> n;
201  bits<5> ws;
202  bits<5> wd;
203
204  let Inst{25-22} = major;
205  let Inst{21-18} = 0b1100;
206  let Inst{17-16} = n{1-0};
207  let Inst{15-11} = ws;
208  let Inst{10-6} = wd;
209  let Inst{5-0} = minor;
210}
211
212class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
213  bits<4> n;
214  bits<5> ws;
215  bits<5> wd;
216
217  let Inst{25-22} = major;
218  let Inst{21-17} = 0b11100;
219  let Inst{16} = n{0};
220  let Inst{15-11} = ws;
221  let Inst{10-6} = wd;
222  let Inst{5-0} = minor;
223}
224
225class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
226  bits<4> n;
227  bits<5> ws;
228  bits<5> rd;
229
230  let Inst{25-22} = major;
231  let Inst{21-20} = 0b00;
232  let Inst{19-16} = n{3-0};
233  let Inst{15-11} = ws;
234  let Inst{10-6} = rd;
235  let Inst{5-0} = minor;
236}
237
238class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
239  bits<4> n;
240  bits<5> ws;
241  bits<5> rd;
242
243  let Inst{25-22} = major;
244  let Inst{21-19} = 0b100;
245  let Inst{18-16} = n{2-0};
246  let Inst{15-11} = ws;
247  let Inst{10-6} = rd;
248  let Inst{5-0} = minor;
249}
250
251class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
252  bits<4> n;
253  bits<5> ws;
254  bits<5> rd;
255
256  let Inst{25-22} = major;
257  let Inst{21-18} = 0b1100;
258  let Inst{17-16} = n{1-0};
259  let Inst{15-11} = ws;
260  let Inst{10-6} = rd;
261  let Inst{5-0} = minor;
262}
263
264class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
265  bits<6> n;
266  bits<5> rs;
267  bits<5> wd;
268
269  let Inst{25-22} = major;
270  let Inst{21-20} = 0b00;
271  let Inst{19-16} = n{3-0};
272  let Inst{15-11} = rs;
273  let Inst{10-6} = wd;
274  let Inst{5-0} = minor;
275}
276
277class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
278  bits<6> n;
279  bits<5> rs;
280  bits<5> wd;
281
282  let Inst{25-22} = major;
283  let Inst{21-19} = 0b100;
284  let Inst{18-16} = n{2-0};
285  let Inst{15-11} = rs;
286  let Inst{10-6} = wd;
287  let Inst{5-0} = minor;
288}
289
290class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
291  bits<6> n;
292  bits<5> rs;
293  bits<5> wd;
294
295  let Inst{25-22} = major;
296  let Inst{21-18} = 0b1100;
297  let Inst{17-16} = n{1-0};
298  let Inst{15-11} = rs;
299  let Inst{10-6} = wd;
300  let Inst{5-0} = minor;
301}
302
303class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
304  bits<5> imm;
305  bits<5> ws;
306  bits<5> wd;
307
308  let Inst{25-23} = major;
309  let Inst{22-21} = df;
310  let Inst{20-16} = imm;
311  let Inst{15-11} = ws;
312  let Inst{10-6} = wd;
313  let Inst{5-0} = minor;
314}
315
316class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
317  bits<8> u8;
318  bits<5> ws;
319  bits<5> wd;
320
321  let Inst{25-24} = major;
322  let Inst{23-16} = u8;
323  let Inst{15-11} = ws;
324  let Inst{10-6} = wd;
325  let Inst{5-0} = minor;
326}
327
328class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
329  let Inst{25-23} = major;
330  let Inst{22-21} = df;
331  let Inst{5-0} = minor;
332}
333
334class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
335  bits<5> wt;
336  bits<5> ws;
337  bits<5> wd;
338
339  let Inst{25-21} = major;
340  let Inst{20-16} = wt;
341  let Inst{15-11} = ws;
342  let Inst{10-6} = wd;
343  let Inst{5-0} = minor;
344}
345
346class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
347  let Inst{25-21} = major;
348  let Inst{5-0} = minor;
349}
350
351class SPECIAL_LSA_FMT: MSAInst {
352  let Inst{25-21} = 0b000000;
353  let Inst{10-8} = 0b000;
354  let Inst{5-0} = 0b000101;
355}
356