MipsMSAInstrFormats.td revision 1327c089221da78b1bfd61067162023e520085ed 
1//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasMSA : Predicate<"Subtarget.hasMSA()">,
11             AssemblerPredicate<"FeatureMSA">;
12
13class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14  let Predicates = [HasMSA];
15  let Inst{31-26} = 0b011110;
16}
17
18class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19                InstrItinClass itin = IIPseudo>:
20  MipsPseudo<outs, ins, pattern, itin> {
21  let Predicates = [HasMSA];
22}
23
24class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
25  let Inst{25-23} = major;
26  let Inst{22-19} = 0b1110;
27  let Inst{5-0} = minor;
28}
29
30class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
31  let Inst{25-23} = major;
32  let Inst{22-20} = 0b110;
33  let Inst{5-0} = minor;
34}
35
36class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
37  let Inst{25-23} = major;
38  let Inst{22-21} = 0b10;
39  let Inst{5-0} = minor;
40}
41
42class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
43  let Inst{25-23} = major;
44  let Inst{22} = 0b0;
45  let Inst{5-0} = minor;
46}
47
48class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
49  let Inst{25-18} = major;
50  let Inst{17-16} = df;
51  let Inst{5-0} = minor;
52}
53
54class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
55  bits<5> ws;
56  bits<5> wd;
57
58  let Inst{25-17} = major;
59  let Inst{16} = df;
60  let Inst{15-11} = ws;
61  let Inst{10-6} = wd;
62  let Inst{5-0} = minor;
63}
64
65class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
66  bits<5> wt;
67  bits<5> ws;
68  bits<5> wd;
69
70  let Inst{25-23} = major;
71  let Inst{22-21} = df;
72  let Inst{20-16} = wt;
73  let Inst{15-11} = ws;
74  let Inst{10-6} = wd;
75  let Inst{5-0} = minor;
76}
77
78class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
79  bits<5> wt;
80  bits<5> ws;
81  bits<5> wd;
82
83  let Inst{25-22} = major;
84  let Inst{21} = df;
85  let Inst{20-16} = wt;
86  let Inst{15-11} = ws;
87  let Inst{10-6} = wd;
88  let Inst{5-0} = minor;
89}
90
91class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
92  let Inst{25-16} = major;
93  let Inst{5-0} = minor;
94}
95
96class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
97  let Inst{25-22} = major;
98  let Inst{21-20} = 0b00;
99  let Inst{5-0} = minor;
100}
101
102class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
103  let Inst{25-22} = major;
104  let Inst{21-19} = 0b100;
105  let Inst{5-0} = minor;
106}
107
108class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
109  let Inst{25-22} = major;
110  let Inst{21-18} = 0b1100;
111  let Inst{5-0} = minor;
112}
113
114class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
115  let Inst{25-22} = major;
116  let Inst{21-17} = 0b11100;
117  let Inst{5-0} = minor;
118}
119
120class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
121  let Inst{25-23} = major;
122  let Inst{22-21} = df;
123  let Inst{5-0} = minor;
124}
125
126class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
127  let Inst{25-24} = major;
128  let Inst{5-0} = minor;
129}
130
131class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
132  let Inst{25-23} = major;
133  let Inst{22-21} = df;
134  let Inst{5-0} = minor;
135}
136
137class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
138  let Inst{25-21} = major;
139  let Inst{5-0} = minor;
140}
141
142class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
143  let Inst{25-21} = major;
144  let Inst{5-0} = minor;
145}
146