MipsMSAInstrFormats.td revision 45ecbfc8e58923131068dced0cf89348ac61208f 
1//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasMSA : Predicate<"Subtarget.hasMSA()">,
11             AssemblerPredicate<"FeatureMSA">;
12
13class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14  let Predicates = [HasMSA];
15  let Inst{31-26} = 0b011110;
16}
17
18class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19                InstrItinClass itin = IIPseudo>:
20  MipsPseudo<outs, ins, pattern, itin> {
21  let Predicates = [HasMSA];
22}
23
24class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
25  let Inst{25-23} = major;
26  let Inst{22-19} = 0b1110;
27  let Inst{5-0} = minor;
28}
29
30class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
31  let Inst{25-23} = major;
32  let Inst{22-20} = 0b110;
33  let Inst{5-0} = minor;
34}
35
36class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
37  let Inst{25-23} = major;
38  let Inst{22-21} = 0b10;
39  let Inst{5-0} = minor;
40}
41
42class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
43  let Inst{25-23} = major;
44  let Inst{22} = 0b0;
45  let Inst{5-0} = minor;
46}
47
48class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
49  bits<5> rs;
50  bits<5> wd;
51
52  let Inst{25-18} = major;
53  let Inst{17-16} = df;
54  let Inst{15-11} = rs;
55  let Inst{10-6} = wd;
56  let Inst{5-0} = minor;
57}
58
59class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
60  bits<5> ws;
61  bits<5> wd;
62
63  let Inst{25-18} = major;
64  let Inst{17-16} = df;
65  let Inst{15-11} = ws;
66  let Inst{10-6} = wd;
67  let Inst{5-0} = minor;
68}
69
70class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
71  bits<5> ws;
72  bits<5> wd;
73
74  let Inst{25-17} = major;
75  let Inst{16} = df;
76  let Inst{15-11} = ws;
77  let Inst{10-6} = wd;
78  let Inst{5-0} = minor;
79}
80
81class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
82  bits<5> wt;
83  bits<5> ws;
84  bits<5> wd;
85
86  let Inst{25-23} = major;
87  let Inst{22-21} = df;
88  let Inst{20-16} = wt;
89  let Inst{15-11} = ws;
90  let Inst{10-6} = wd;
91  let Inst{5-0} = minor;
92}
93
94class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
95  bits<5> wt;
96  bits<5> ws;
97  bits<5> wd;
98
99  let Inst{25-22} = major;
100  let Inst{21} = df;
101  let Inst{20-16} = wt;
102  let Inst{15-11} = ws;
103  let Inst{10-6} = wd;
104  let Inst{5-0} = minor;
105}
106
107class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
108  let Inst{25-16} = major;
109  let Inst{5-0} = minor;
110}
111
112class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
113  let Inst{25-22} = major;
114  let Inst{21-20} = 0b00;
115  let Inst{5-0} = minor;
116}
117
118class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
119  let Inst{25-22} = major;
120  let Inst{21-19} = 0b100;
121  let Inst{5-0} = minor;
122}
123
124class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
125  let Inst{25-22} = major;
126  let Inst{21-18} = 0b1100;
127  let Inst{5-0} = minor;
128}
129
130class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
131  let Inst{25-22} = major;
132  let Inst{21-17} = 0b11100;
133  let Inst{5-0} = minor;
134}
135
136class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
137  bits<6> n;
138  bits<5> rs;
139  bits<5> wd;
140
141  let Inst{25-22} = major;
142  let Inst{21-20} = 0b00;
143  let Inst{19-16} = n{3-0};
144  let Inst{15-11} = rs;
145  let Inst{10-6} = wd;
146  let Inst{5-0} = minor;
147}
148
149class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
150  bits<6> n;
151  bits<5> rs;
152  bits<5> wd;
153
154  let Inst{25-22} = major;
155  let Inst{21-19} = 0b100;
156  let Inst{18-16} = n{2-0};
157  let Inst{15-11} = rs;
158  let Inst{10-6} = wd;
159  let Inst{5-0} = minor;
160}
161
162class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
163  bits<6> n;
164  bits<5> rs;
165  bits<5> wd;
166
167  let Inst{25-22} = major;
168  let Inst{21-18} = 0b1100;
169  let Inst{17-16} = n{1-0};
170  let Inst{15-11} = rs;
171  let Inst{10-6} = wd;
172  let Inst{5-0} = minor;
173}
174
175class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
176  bits<5> imm;
177  bits<5> ws;
178  bits<5> wd;
179
180  let Inst{25-23} = major;
181  let Inst{22-21} = df;
182  let Inst{20-16} = imm;
183  let Inst{15-11} = ws;
184  let Inst{10-6} = wd;
185  let Inst{5-0} = minor;
186}
187
188class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
189  bits<8> u8;
190  bits<5> ws;
191  bits<5> wd;
192
193  let Inst{25-24} = major;
194  let Inst{23-16} = u8;
195  let Inst{15-11} = ws;
196  let Inst{10-6} = wd;
197  let Inst{5-0} = minor;
198}
199
200class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
201  let Inst{25-23} = major;
202  let Inst{22-21} = df;
203  let Inst{5-0} = minor;
204}
205
206class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
207  let Inst{25-21} = major;
208  let Inst{5-0} = minor;
209}
210
211class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
212  let Inst{25-21} = major;
213  let Inst{5-0} = minor;
214}
215