MipsMSAInstrFormats.td revision 52244da7f2b3def646900520668b859343b84a33 
1//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasMSA : Predicate<"Subtarget.hasMSA()">,
11             AssemblerPredicate<"FeatureMSA">;
12
13class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14  let Predicates = [HasMSA];
15  let Inst{31-26} = 0b011110;
16}
17
18class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19                InstrItinClass itin = IIPseudo>:
20  MipsPseudo<outs, ins, pattern, itin> {
21  let Predicates = [HasMSA];
22}
23
24class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
25  bits<5> ws;
26  bits<5> wd;
27  bits<3> m;
28
29  let Inst{25-23} = major;
30  let Inst{22-19} = 0b1110;
31  let Inst{18-16} = m;
32  let Inst{15-11} = ws;
33  let Inst{10-6} = wd;
34  let Inst{5-0} = minor;
35}
36
37class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
38  bits<5> ws;
39  bits<5> wd;
40  bits<4> m;
41
42  let Inst{25-23} = major;
43  let Inst{22-20} = 0b110;
44  let Inst{19-16} = m;
45  let Inst{15-11} = ws;
46  let Inst{10-6} = wd;
47  let Inst{5-0} = minor;
48}
49
50class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
51  bits<5> ws;
52  bits<5> wd;
53  bits<5> m;
54
55  let Inst{25-23} = major;
56  let Inst{22-21} = 0b10;
57  let Inst{20-16} = m;
58  let Inst{15-11} = ws;
59  let Inst{10-6} = wd;
60  let Inst{5-0} = minor;
61}
62
63class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
64  bits<5> ws;
65  bits<5> wd;
66  bits<6> m;
67
68  let Inst{25-23} = major;
69  let Inst{22} = 0b0;
70  let Inst{21-16} = m;
71  let Inst{15-11} = ws;
72  let Inst{10-6} = wd;
73  let Inst{5-0} = minor;
74}
75
76class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
77  bits<5> rs;
78  bits<5> wd;
79
80  let Inst{25-18} = major;
81  let Inst{17-16} = df;
82  let Inst{15-11} = rs;
83  let Inst{10-6} = wd;
84  let Inst{5-0} = minor;
85}
86
87class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
88  bits<5> ws;
89  bits<5> wd;
90
91  let Inst{25-18} = major;
92  let Inst{17-16} = df;
93  let Inst{15-11} = ws;
94  let Inst{10-6} = wd;
95  let Inst{5-0} = minor;
96}
97
98class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
99  bits<5> ws;
100  bits<5> wd;
101
102  let Inst{25-17} = major;
103  let Inst{16} = df;
104  let Inst{15-11} = ws;
105  let Inst{10-6} = wd;
106  let Inst{5-0} = minor;
107}
108
109class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
110  bits<5> wt;
111  bits<5> ws;
112  bits<5> wd;
113
114  let Inst{25-23} = major;
115  let Inst{22-21} = df;
116  let Inst{20-16} = wt;
117  let Inst{15-11} = ws;
118  let Inst{10-6} = wd;
119  let Inst{5-0} = minor;
120}
121
122class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
123  bits<5> wt;
124  bits<5> ws;
125  bits<5> wd;
126
127  let Inst{25-22} = major;
128  let Inst{21} = df;
129  let Inst{20-16} = wt;
130  let Inst{15-11} = ws;
131  let Inst{10-6} = wd;
132  let Inst{5-0} = minor;
133}
134
135class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
136  let Inst{25-16} = major;
137  let Inst{5-0} = minor;
138}
139
140class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
141  bits<4> n;
142  bits<5> ws;
143  bits<5> wd;
144
145  let Inst{25-22} = major;
146  let Inst{21-20} = 0b00;
147  let Inst{19-16} = n{3-0};
148  let Inst{15-11} = ws;
149  let Inst{10-6} = wd;
150  let Inst{5-0} = minor;
151}
152
153class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
154  bits<4> n;
155  bits<5> ws;
156  bits<5> wd;
157
158  let Inst{25-22} = major;
159  let Inst{21-19} = 0b100;
160  let Inst{18-16} = n{2-0};
161  let Inst{15-11} = ws;
162  let Inst{10-6} = wd;
163  let Inst{5-0} = minor;
164}
165
166class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
167  bits<4> n;
168  bits<5> ws;
169  bits<5> wd;
170
171  let Inst{25-22} = major;
172  let Inst{21-18} = 0b1100;
173  let Inst{17-16} = n{1-0};
174  let Inst{15-11} = ws;
175  let Inst{10-6} = wd;
176  let Inst{5-0} = minor;
177}
178
179class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
180  bits<4> n;
181  bits<5> ws;
182  bits<5> wd;
183
184  let Inst{25-22} = major;
185  let Inst{21-17} = 0b11100;
186  let Inst{16} = n{0};
187  let Inst{15-11} = ws;
188  let Inst{10-6} = wd;
189  let Inst{5-0} = minor;
190}
191
192class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
193  bits<4> n;
194  bits<5> ws;
195  bits<5> rd;
196
197  let Inst{25-22} = major;
198  let Inst{21-20} = 0b00;
199  let Inst{19-16} = n{3-0};
200  let Inst{15-11} = ws;
201  let Inst{10-6} = rd;
202  let Inst{5-0} = minor;
203}
204
205class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
206  bits<4> n;
207  bits<5> ws;
208  bits<5> rd;
209
210  let Inst{25-22} = major;
211  let Inst{21-19} = 0b100;
212  let Inst{18-16} = n{2-0};
213  let Inst{15-11} = ws;
214  let Inst{10-6} = rd;
215  let Inst{5-0} = minor;
216}
217
218class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
219  bits<4> n;
220  bits<5> ws;
221  bits<5> rd;
222
223  let Inst{25-22} = major;
224  let Inst{21-18} = 0b1100;
225  let Inst{17-16} = n{1-0};
226  let Inst{15-11} = ws;
227  let Inst{10-6} = rd;
228  let Inst{5-0} = minor;
229}
230
231class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
232  bits<6> n;
233  bits<5> rs;
234  bits<5> wd;
235
236  let Inst{25-22} = major;
237  let Inst{21-20} = 0b00;
238  let Inst{19-16} = n{3-0};
239  let Inst{15-11} = rs;
240  let Inst{10-6} = wd;
241  let Inst{5-0} = minor;
242}
243
244class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
245  bits<6> n;
246  bits<5> rs;
247  bits<5> wd;
248
249  let Inst{25-22} = major;
250  let Inst{21-19} = 0b100;
251  let Inst{18-16} = n{2-0};
252  let Inst{15-11} = rs;
253  let Inst{10-6} = wd;
254  let Inst{5-0} = minor;
255}
256
257class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
258  bits<6> n;
259  bits<5> rs;
260  bits<5> wd;
261
262  let Inst{25-22} = major;
263  let Inst{21-18} = 0b1100;
264  let Inst{17-16} = n{1-0};
265  let Inst{15-11} = rs;
266  let Inst{10-6} = wd;
267  let Inst{5-0} = minor;
268}
269
270class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
271  bits<5> imm;
272  bits<5> ws;
273  bits<5> wd;
274
275  let Inst{25-23} = major;
276  let Inst{22-21} = df;
277  let Inst{20-16} = imm;
278  let Inst{15-11} = ws;
279  let Inst{10-6} = wd;
280  let Inst{5-0} = minor;
281}
282
283class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
284  bits<8> u8;
285  bits<5> ws;
286  bits<5> wd;
287
288  let Inst{25-24} = major;
289  let Inst{23-16} = u8;
290  let Inst{15-11} = ws;
291  let Inst{10-6} = wd;
292  let Inst{5-0} = minor;
293}
294
295class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
296  let Inst{25-23} = major;
297  let Inst{22-21} = df;
298  let Inst{5-0} = minor;
299}
300
301class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
302  bits<5> wt;
303  bits<5> ws;
304  bits<5> wd;
305
306  let Inst{25-21} = major;
307  let Inst{20-16} = wt;
308  let Inst{15-11} = ws;
309  let Inst{10-6} = wd;
310  let Inst{5-0} = minor;
311}
312
313class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
314  let Inst{25-21} = major;
315  let Inst{5-0} = minor;
316}
317
318class SPECIAL_LSA_FMT: MSAInst {
319  let Inst{25-21} = 0b000000;
320  let Inst{10-8} = 0b000;
321  let Inst{5-0} = 0b000101;
322}
323