MipsMSAInstrFormats.td revision 5cb5ff8b1478ed413a9e9fae43b1496f5a97a2dc 
1//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasMSA : Predicate<"Subtarget.hasMSA()">,
11             AssemblerPredicate<"FeatureMSA">;
12
13class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14  let Predicates = [HasMSA];
15  let Inst{31-26} = 0b011110;
16}
17
18class MSACBranch : MSAInst {
19  let Inst{31-26} = 0b010001;
20}
21
22class PseudoMSA<dag outs, dag ins, list<dag> pattern,
23                InstrItinClass itin = IIPseudo>:
24  MipsPseudo<outs, ins, pattern, itin> {
25  let Predicates = [HasMSA];
26}
27
28class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
29  bits<5> ws;
30  bits<5> wd;
31  bits<3> m;
32
33  let Inst{25-23} = major;
34  let Inst{22-19} = 0b1110;
35  let Inst{18-16} = m;
36  let Inst{15-11} = ws;
37  let Inst{10-6} = wd;
38  let Inst{5-0} = minor;
39}
40
41class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
42  bits<5> ws;
43  bits<5> wd;
44  bits<4> m;
45
46  let Inst{25-23} = major;
47  let Inst{22-20} = 0b110;
48  let Inst{19-16} = m;
49  let Inst{15-11} = ws;
50  let Inst{10-6} = wd;
51  let Inst{5-0} = minor;
52}
53
54class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
55  bits<5> ws;
56  bits<5> wd;
57  bits<5> m;
58
59  let Inst{25-23} = major;
60  let Inst{22-21} = 0b10;
61  let Inst{20-16} = m;
62  let Inst{15-11} = ws;
63  let Inst{10-6} = wd;
64  let Inst{5-0} = minor;
65}
66
67class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
68  bits<5> ws;
69  bits<5> wd;
70  bits<6> m;
71
72  let Inst{25-23} = major;
73  let Inst{22} = 0b0;
74  let Inst{21-16} = m;
75  let Inst{15-11} = ws;
76  let Inst{10-6} = wd;
77  let Inst{5-0} = minor;
78}
79
80class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
81  bits<5> rs;
82  bits<5> wd;
83
84  let Inst{25-18} = major;
85  let Inst{17-16} = df;
86  let Inst{15-11} = rs;
87  let Inst{10-6} = wd;
88  let Inst{5-0} = minor;
89}
90
91class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
92  bits<5> ws;
93  bits<5> wd;
94
95  let Inst{25-18} = major;
96  let Inst{17-16} = df;
97  let Inst{15-11} = ws;
98  let Inst{10-6} = wd;
99  let Inst{5-0} = minor;
100}
101
102class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
103  bits<5> ws;
104  bits<5> wd;
105
106  let Inst{25-17} = major;
107  let Inst{16} = df;
108  let Inst{15-11} = ws;
109  let Inst{10-6} = wd;
110  let Inst{5-0} = minor;
111}
112
113class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
114  bits<5> wt;
115  bits<5> ws;
116  bits<5> wd;
117
118  let Inst{25-23} = major;
119  let Inst{22-21} = df;
120  let Inst{20-16} = wt;
121  let Inst{15-11} = ws;
122  let Inst{10-6} = wd;
123  let Inst{5-0} = minor;
124}
125
126class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
127  bits<5> wt;
128  bits<5> ws;
129  bits<5> wd;
130
131  let Inst{25-22} = major;
132  let Inst{21} = df;
133  let Inst{20-16} = wt;
134  let Inst{15-11} = ws;
135  let Inst{10-6} = wd;
136  let Inst{5-0} = minor;
137}
138
139class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
140  bits<5> rt;
141  bits<5> ws;
142  bits<5> wd;
143
144  let Inst{25-23} = major;
145  let Inst{22-21} = df;
146  let Inst{20-16} = rt;
147  let Inst{15-11} = ws;
148  let Inst{10-6} = wd;
149  let Inst{5-0} = minor;
150}
151
152class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
153  bits<5> ws;
154  bits<5> wd;
155
156  let Inst{25-16} = major;
157  let Inst{15-11} = ws;
158  let Inst{10-6} = wd;
159  let Inst{5-0} = minor;
160}
161
162class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
163  bits<5> rd;
164  bits<5> cs;
165
166  let Inst{25-16} = major;
167  let Inst{15-11} = cs;
168  let Inst{10-6} = rd;
169  let Inst{5-0} = minor;
170}
171
172class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
173  bits<5> rs;
174  bits<5> cd;
175
176  let Inst{25-16} = major;
177  let Inst{15-11} = rs;
178  let Inst{10-6} = cd;
179  let Inst{5-0} = minor;
180}
181
182class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
183  bits<4> n;
184  bits<5> ws;
185  bits<5> wd;
186
187  let Inst{25-22} = major;
188  let Inst{21-20} = 0b00;
189  let Inst{19-16} = n{3-0};
190  let Inst{15-11} = ws;
191  let Inst{10-6} = wd;
192  let Inst{5-0} = minor;
193}
194
195class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
196  bits<4> n;
197  bits<5> ws;
198  bits<5> wd;
199
200  let Inst{25-22} = major;
201  let Inst{21-19} = 0b100;
202  let Inst{18-16} = n{2-0};
203  let Inst{15-11} = ws;
204  let Inst{10-6} = wd;
205  let Inst{5-0} = minor;
206}
207
208class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
209  bits<4> n;
210  bits<5> ws;
211  bits<5> wd;
212
213  let Inst{25-22} = major;
214  let Inst{21-18} = 0b1100;
215  let Inst{17-16} = n{1-0};
216  let Inst{15-11} = ws;
217  let Inst{10-6} = wd;
218  let Inst{5-0} = minor;
219}
220
221class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
222  bits<4> n;
223  bits<5> ws;
224  bits<5> wd;
225
226  let Inst{25-22} = major;
227  let Inst{21-17} = 0b11100;
228  let Inst{16} = n{0};
229  let Inst{15-11} = ws;
230  let Inst{10-6} = wd;
231  let Inst{5-0} = minor;
232}
233
234class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
235  bits<4> n;
236  bits<5> ws;
237  bits<5> rd;
238
239  let Inst{25-22} = major;
240  let Inst{21-20} = 0b00;
241  let Inst{19-16} = n{3-0};
242  let Inst{15-11} = ws;
243  let Inst{10-6} = rd;
244  let Inst{5-0} = minor;
245}
246
247class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
248  bits<4> n;
249  bits<5> ws;
250  bits<5> rd;
251
252  let Inst{25-22} = major;
253  let Inst{21-19} = 0b100;
254  let Inst{18-16} = n{2-0};
255  let Inst{15-11} = ws;
256  let Inst{10-6} = rd;
257  let Inst{5-0} = minor;
258}
259
260class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
261  bits<4> n;
262  bits<5> ws;
263  bits<5> rd;
264
265  let Inst{25-22} = major;
266  let Inst{21-18} = 0b1100;
267  let Inst{17-16} = n{1-0};
268  let Inst{15-11} = ws;
269  let Inst{10-6} = rd;
270  let Inst{5-0} = minor;
271}
272
273class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
274  bits<6> n;
275  bits<5> rs;
276  bits<5> wd;
277
278  let Inst{25-22} = major;
279  let Inst{21-20} = 0b00;
280  let Inst{19-16} = n{3-0};
281  let Inst{15-11} = rs;
282  let Inst{10-6} = wd;
283  let Inst{5-0} = minor;
284}
285
286class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
287  bits<6> n;
288  bits<5> rs;
289  bits<5> wd;
290
291  let Inst{25-22} = major;
292  let Inst{21-19} = 0b100;
293  let Inst{18-16} = n{2-0};
294  let Inst{15-11} = rs;
295  let Inst{10-6} = wd;
296  let Inst{5-0} = minor;
297}
298
299class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
300  bits<6> n;
301  bits<5> rs;
302  bits<5> wd;
303
304  let Inst{25-22} = major;
305  let Inst{21-18} = 0b1100;
306  let Inst{17-16} = n{1-0};
307  let Inst{15-11} = rs;
308  let Inst{10-6} = wd;
309  let Inst{5-0} = minor;
310}
311
312class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
313  bits<5> imm;
314  bits<5> ws;
315  bits<5> wd;
316
317  let Inst{25-23} = major;
318  let Inst{22-21} = df;
319  let Inst{20-16} = imm;
320  let Inst{15-11} = ws;
321  let Inst{10-6} = wd;
322  let Inst{5-0} = minor;
323}
324
325class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
326  bits<8> u8;
327  bits<5> ws;
328  bits<5> wd;
329
330  let Inst{25-24} = major;
331  let Inst{23-16} = u8;
332  let Inst{15-11} = ws;
333  let Inst{10-6} = wd;
334  let Inst{5-0} = minor;
335}
336
337class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
338  bits<10> s10;
339  bits<5> wd;
340
341  let Inst{25-23} = major;
342  let Inst{22-21} = df;
343  let Inst{20-11} = s10;
344  let Inst{10-6} = wd;
345  let Inst{5-0} = minor;
346}
347
348class MSA_MI10_FMT<bits<2> df, bits<4> minor>: MSAInst {
349  bits<21> addr;
350  bits<5> wd;
351
352  let Inst{25-16} = addr{9-0};
353  let Inst{15-11} = addr{20-16};
354  let Inst{10-6} = wd;
355  let Inst{5-2} = minor;
356  let Inst{1-0} = df;
357}
358
359class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
360  bits<5> wt;
361  bits<5> ws;
362  bits<5> wd;
363
364  let Inst{25-21} = major;
365  let Inst{20-16} = wt;
366  let Inst{15-11} = ws;
367  let Inst{10-6} = wd;
368  let Inst{5-0} = minor;
369}
370
371class MSA_CBRANCH_FMT<bits<3> major, bits<2> df>: MSACBranch {
372  bits<16> offset;
373  bits<5> wt;
374
375  let Inst{25-23} = major;
376  let Inst{22-21} = df;
377  let Inst{20-16} = wt;
378  let Inst{15-0} = offset;
379}
380
381class MSA_CBRANCH_V_FMT<bits<5> major>: MSACBranch {
382  bits<16> offset;
383  bits<5> wt;
384
385  let Inst{25-21} = major;
386  let Inst{20-16} = wt;
387  let Inst{15-0} = offset;
388}
389
390class SPECIAL_LSA_FMT: MSAInst {
391  let Inst{25-21} = 0b000000;
392  let Inst{10-8} = 0b000;
393  let Inst{5-0} = 0b000101;
394}
395