MipsMSAInstrFormats.td revision b0247157c6d44363c36cffd0aeea0e2fa83d9335
1//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10def HasMSA : Predicate<"Subtarget.hasMSA()">, 11 AssemblerPredicate<"FeatureMSA">; 12 13class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { 14 let Predicates = [HasMSA]; 15 let Inst{31-26} = 0b011110; 16} 17 18class PseudoMSA<dag outs, dag ins, list<dag> pattern, 19 InstrItinClass itin = IIPseudo>: 20 MipsPseudo<outs, ins, pattern, itin> { 21 let Predicates = [HasMSA]; 22} 23 24class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst { 25 let Inst{25-23} = major; 26 let Inst{22-19} = 0b1110; 27 let Inst{5-0} = minor; 28} 29 30class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst { 31 let Inst{25-23} = major; 32 let Inst{22-20} = 0b110; 33 let Inst{5-0} = minor; 34} 35 36class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst { 37 let Inst{25-23} = major; 38 let Inst{22-21} = 0b10; 39 let Inst{5-0} = minor; 40} 41 42class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst { 43 let Inst{25-23} = major; 44 let Inst{22} = 0b0; 45 let Inst{5-0} = minor; 46} 47 48class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { 49 bits<5> rs; 50 bits<5> wd; 51 52 let Inst{25-18} = major; 53 let Inst{17-16} = df; 54 let Inst{15-11} = rs; 55 let Inst{10-6} = wd; 56 let Inst{5-0} = minor; 57} 58 59class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { 60 bits<5> ws; 61 bits<5> wd; 62 63 let Inst{25-18} = major; 64 let Inst{17-16} = df; 65 let Inst{15-11} = ws; 66 let Inst{10-6} = wd; 67 let Inst{5-0} = minor; 68} 69 70class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst { 71 bits<5> ws; 72 bits<5> wd; 73 74 let Inst{25-17} = major; 75 let Inst{16} = df; 76 let Inst{15-11} = ws; 77 let Inst{10-6} = wd; 78 let Inst{5-0} = minor; 79} 80 81class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 82 bits<5> wt; 83 bits<5> ws; 84 bits<5> wd; 85 86 let Inst{25-23} = major; 87 let Inst{22-21} = df; 88 let Inst{20-16} = wt; 89 let Inst{15-11} = ws; 90 let Inst{10-6} = wd; 91 let Inst{5-0} = minor; 92} 93 94class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst { 95 bits<5> wt; 96 bits<5> ws; 97 bits<5> wd; 98 99 let Inst{25-22} = major; 100 let Inst{21} = df; 101 let Inst{20-16} = wt; 102 let Inst{15-11} = ws; 103 let Inst{10-6} = wd; 104 let Inst{5-0} = minor; 105} 106 107class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst { 108 let Inst{25-16} = major; 109 let Inst{5-0} = minor; 110} 111 112class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst { 113 let Inst{25-22} = major; 114 let Inst{21-20} = 0b00; 115 let Inst{5-0} = minor; 116} 117 118class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst { 119 let Inst{25-22} = major; 120 let Inst{21-19} = 0b100; 121 let Inst{5-0} = minor; 122} 123 124class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst { 125 let Inst{25-22} = major; 126 let Inst{21-18} = 0b1100; 127 let Inst{5-0} = minor; 128} 129 130class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst { 131 let Inst{25-22} = major; 132 let Inst{21-17} = 0b11100; 133 let Inst{5-0} = minor; 134} 135 136class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 137 bits<5> imm; 138 bits<5> ws; 139 bits<5> wd; 140 141 let Inst{25-23} = major; 142 let Inst{22-21} = df; 143 let Inst{20-16} = imm; 144 let Inst{15-11} = ws; 145 let Inst{10-6} = wd; 146 let Inst{5-0} = minor; 147} 148 149class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst { 150 let Inst{25-24} = major; 151 let Inst{5-0} = minor; 152} 153 154class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 155 let Inst{25-23} = major; 156 let Inst{22-21} = df; 157 let Inst{5-0} = minor; 158} 159 160class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst { 161 let Inst{25-21} = major; 162 let Inst{5-0} = minor; 163} 164 165class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst { 166 let Inst{25-21} = major; 167 let Inst{5-0} = minor; 168} 169