MipsMSAInstrFormats.td revision e89c50acc8312c6cd4d3bdbf50e02ba88e54a663 
1//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasMSA : Predicate<"Subtarget.hasMSA()">,
11             AssemblerPredicate<"FeatureMSA">;
12
13class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14  let Predicates = [HasMSA];
15  let Inst{31-26} = 0b011110;
16}
17
18class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19                InstrItinClass itin = IIPseudo>:
20  MipsPseudo<outs, ins, pattern, itin> {
21  let Predicates = [HasMSA];
22}
23
24class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
25  let Inst{25-23} = major;
26  let Inst{22-19} = 0b1110;
27  let Inst{5-0} = minor;
28}
29
30class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
31  let Inst{25-23} = major;
32  let Inst{22-20} = 0b110;
33  let Inst{5-0} = minor;
34}
35
36class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
37  let Inst{25-23} = major;
38  let Inst{22-21} = 0b10;
39  let Inst{5-0} = minor;
40}
41
42class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
43  let Inst{25-23} = major;
44  let Inst{22} = 0b0;
45  let Inst{5-0} = minor;
46}
47
48class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
49  bits<5> rs;
50  bits<5> wd;
51
52  let Inst{25-18} = major;
53  let Inst{17-16} = df;
54  let Inst{15-11} = rs;
55  let Inst{10-6} = wd;
56  let Inst{5-0} = minor;
57}
58
59class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
60  bits<5> ws;
61  bits<5> wd;
62
63  let Inst{25-18} = major;
64  let Inst{17-16} = df;
65  let Inst{15-11} = ws;
66  let Inst{10-6} = wd;
67  let Inst{5-0} = minor;
68}
69
70class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
71  bits<5> ws;
72  bits<5> wd;
73
74  let Inst{25-17} = major;
75  let Inst{16} = df;
76  let Inst{15-11} = ws;
77  let Inst{10-6} = wd;
78  let Inst{5-0} = minor;
79}
80
81class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
82  bits<5> wt;
83  bits<5> ws;
84  bits<5> wd;
85
86  let Inst{25-23} = major;
87  let Inst{22-21} = df;
88  let Inst{20-16} = wt;
89  let Inst{15-11} = ws;
90  let Inst{10-6} = wd;
91  let Inst{5-0} = minor;
92}
93
94class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
95  bits<5> wt;
96  bits<5> ws;
97  bits<5> wd;
98
99  let Inst{25-22} = major;
100  let Inst{21} = df;
101  let Inst{20-16} = wt;
102  let Inst{15-11} = ws;
103  let Inst{10-6} = wd;
104  let Inst{5-0} = minor;
105}
106
107class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
108  let Inst{25-16} = major;
109  let Inst{5-0} = minor;
110}
111
112class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
113  bits<4> n;
114  bits<5> ws;
115  bits<5> wd;
116
117  let Inst{25-22} = major;
118  let Inst{21-20} = 0b00;
119  let Inst{19-16} = n{3-0};
120  let Inst{15-11} = ws;
121  let Inst{10-6} = wd;
122  let Inst{5-0} = minor;
123}
124
125class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
126  bits<4> n;
127  bits<5> ws;
128  bits<5> wd;
129
130  let Inst{25-22} = major;
131  let Inst{21-19} = 0b100;
132  let Inst{18-16} = n{2-0};
133  let Inst{15-11} = ws;
134  let Inst{10-6} = wd;
135  let Inst{5-0} = minor;
136}
137
138class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
139  bits<4> n;
140  bits<5> ws;
141  bits<5> wd;
142
143  let Inst{25-22} = major;
144  let Inst{21-18} = 0b1100;
145  let Inst{17-16} = n{1-0};
146  let Inst{15-11} = ws;
147  let Inst{10-6} = wd;
148  let Inst{5-0} = minor;
149}
150
151class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
152  bits<4> n;
153  bits<5> ws;
154  bits<5> wd;
155
156  let Inst{25-22} = major;
157  let Inst{21-17} = 0b11100;
158  let Inst{16} = n{0};
159  let Inst{15-11} = ws;
160  let Inst{10-6} = wd;
161  let Inst{5-0} = minor;
162}
163
164class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
165  bits<4> n;
166  bits<5> ws;
167  bits<5> rd;
168
169  let Inst{25-22} = major;
170  let Inst{21-20} = 0b00;
171  let Inst{19-16} = n{3-0};
172  let Inst{15-11} = ws;
173  let Inst{10-6} = rd;
174  let Inst{5-0} = minor;
175}
176
177class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
178  bits<4> n;
179  bits<5> ws;
180  bits<5> rd;
181
182  let Inst{25-22} = major;
183  let Inst{21-19} = 0b100;
184  let Inst{18-16} = n{2-0};
185  let Inst{15-11} = ws;
186  let Inst{10-6} = rd;
187  let Inst{5-0} = minor;
188}
189
190class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
191  bits<4> n;
192  bits<5> ws;
193  bits<5> rd;
194
195  let Inst{25-22} = major;
196  let Inst{21-18} = 0b1100;
197  let Inst{17-16} = n{1-0};
198  let Inst{15-11} = ws;
199  let Inst{10-6} = rd;
200  let Inst{5-0} = minor;
201}
202
203class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
204  bits<6> n;
205  bits<5> rs;
206  bits<5> wd;
207
208  let Inst{25-22} = major;
209  let Inst{21-20} = 0b00;
210  let Inst{19-16} = n{3-0};
211  let Inst{15-11} = rs;
212  let Inst{10-6} = wd;
213  let Inst{5-0} = minor;
214}
215
216class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
217  bits<6> n;
218  bits<5> rs;
219  bits<5> wd;
220
221  let Inst{25-22} = major;
222  let Inst{21-19} = 0b100;
223  let Inst{18-16} = n{2-0};
224  let Inst{15-11} = rs;
225  let Inst{10-6} = wd;
226  let Inst{5-0} = minor;
227}
228
229class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
230  bits<6> n;
231  bits<5> rs;
232  bits<5> wd;
233
234  let Inst{25-22} = major;
235  let Inst{21-18} = 0b1100;
236  let Inst{17-16} = n{1-0};
237  let Inst{15-11} = rs;
238  let Inst{10-6} = wd;
239  let Inst{5-0} = minor;
240}
241
242class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
243  bits<5> imm;
244  bits<5> ws;
245  bits<5> wd;
246
247  let Inst{25-23} = major;
248  let Inst{22-21} = df;
249  let Inst{20-16} = imm;
250  let Inst{15-11} = ws;
251  let Inst{10-6} = wd;
252  let Inst{5-0} = minor;
253}
254
255class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
256  bits<8> u8;
257  bits<5> ws;
258  bits<5> wd;
259
260  let Inst{25-24} = major;
261  let Inst{23-16} = u8;
262  let Inst{15-11} = ws;
263  let Inst{10-6} = wd;
264  let Inst{5-0} = minor;
265}
266
267class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
268  let Inst{25-23} = major;
269  let Inst{22-21} = df;
270  let Inst{5-0} = minor;
271}
272
273class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
274  bits<5> wt;
275  bits<5> ws;
276  bits<5> wd;
277
278  let Inst{25-21} = major;
279  let Inst{20-16} = wt;
280  let Inst{15-11} = ws;
281  let Inst{10-6} = wd;
282  let Inst{5-0} = minor;
283}
284
285class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
286  let Inst{25-21} = major;
287  let Inst{5-0} = minor;
288}
289